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author | Rene Ladan <rene@FreeBSD.org> | 2013-07-26 19:19:20 +0000 |
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committer | Rene Ladan <rene@FreeBSD.org> | 2013-07-26 19:19:20 +0000 |
commit | 66fee909266a1dedf3dfc1f03bb0841380d78805 (patch) | |
tree | 4c98d494bc4532b5dd5b19f4e47bcb3babf104c2 /cad/Makefile | |
parent | eec2cb8d7407c5628cc8016e7349abbee6c98e3f (diff) | |
download | ports-66fee909266a1dedf3dfc1f03bb0841380d78805.tar.gz ports-66fee909266a1dedf3dfc1f03bb0841380d78805.zip |
Notes
Diffstat (limited to 'cad/Makefile')
-rw-r--r-- | cad/Makefile | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/cad/Makefile b/cad/Makefile index 15eac7d4a836..44dd6e98709c 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -65,7 +65,6 @@ SUBDIR += netgen SUBDIR += ngspice_rework SUBDIR += opencascade - SUBDIR += opencascade-tutorial SUBDIR += openscad SUBDIR += openvsp SUBDIR += p5-GDS2 @@ -73,12 +72,10 @@ SUBDIR += pcb SUBDIR += pdnmesh SUBDIR += pythoncad - SUBDIR += qcad SUBDIR += qcad-partslib SUBDIR += qelectrotech SUBDIR += qfsm SUBDIR += qmls - SUBDIR += qucs SUBDIR += repsnapper SUBDIR += salome SUBDIR += salome-geom @@ -106,7 +103,6 @@ SUBDIR += transcalc SUBDIR += varkon SUBDIR += verilog-mode.el - SUBDIR += vipec SUBDIR += xcircuit SUBDIR += z88 |