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authorYuri Victorovich <yuri@FreeBSD.org>2019-11-23 18:20:17 +0000
committerYuri Victorovich <yuri@FreeBSD.org>2019-11-23 18:20:17 +0000
commitf50f1e39acec8697646b308c6634c800480f238d (patch)
tree2513538454e1fdfae6e9a229f2fa06f9e146965f /cad/Makefile
parentd289e590ccaf4a64e26f712cf8e905cda3b3353f (diff)
Re-add cad/oregano: Schematic capture and circuit simulator
Notes
Notes: svn path=/head/; revision=518265
Diffstat (limited to 'cad/Makefile')
-rw-r--r--cad/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile
index b586fadf124b..0c60afcc5729 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -76,6 +76,7 @@
SUBDIR += openscad
SUBDIR += openscad-devel
SUBDIR += openvsp
+ SUBDIR += oregano
SUBDIR += p5-GDS2
SUBDIR += p5-Verilog-Perl
SUBDIR += pcb