aboutsummaryrefslogtreecommitdiff
path: root/cad/Makefile
diff options
context:
space:
mode:
authorYing-Chieh Liao <ijliao@FreeBSD.org>2003-01-29 03:45:13 +0000
committerYing-Chieh Liao <ijliao@FreeBSD.org>2003-01-29 03:45:13 +0000
commit74f0872c5b982e0ba326b19c22a9901e999e6947 (patch)
tree9d64e6e7bd5a09a44e1172e569a45e970b6a30af /cad/Makefile
parent3ec050d985fd15e37e7e3040a6ae1b2e44e10745 (diff)
downloadports-74f0872c5b982e0ba326b19c22a9901e999e6947.tar.gz
ports-74f0872c5b982e0ba326b19c22a9901e999e6947.zip
add chipvault 200211
A project organizer for VHDL and Verilog RTL hardware designs
Notes
Notes: svn path=/head/; revision=74193
Diffstat (limited to 'cad/Makefile')
-rw-r--r--cad/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile
index e3ad100d5bd9..2ecb0ebac91c 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -4,6 +4,7 @@
SUBDIR += atlc
SUBDIR += cascade
SUBDIR += chipmunk
+ SUBDIR += chipvault
SUBDIR += cider
SUBDIR += electric
SUBDIR += felt