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| author | Cheng-Lung Sung <clsung@FreeBSD.org> | 2006-08-03 03:26:38 +0000 |
|---|---|---|
| committer | Cheng-Lung Sung <clsung@FreeBSD.org> | 2006-08-03 03:26:38 +0000 |
| commit | 3f4bff3a6ee423b26191dd474bc73532f2f1aee2 (patch) | |
| tree | 9e0350120aedb8437eddd87846fb63a246176149 /cad/gplcver | |
| parent | 621b506e07a8cdbefd12d154123246bec463fe9a (diff) | |
| download | ports-3f4bff3a6ee423b26191dd474bc73532f2f1aee2.tar.gz ports-3f4bff3a6ee423b26191dd474bc73532f2f1aee2.zip | |
Notes
Diffstat (limited to 'cad/gplcver')
| -rw-r--r-- | cad/gplcver/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile index 47074407390f..21ba94b9ed3b 100644 --- a/cad/gplcver/Makefile +++ b/cad/gplcver/Makefile @@ -12,7 +12,7 @@ CATEGORIES= cad MASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/ DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src -MAINTAINER= ijliao@csie.nctu.edu.tw +MAINTAINER= ijliao@FreeBSD.org COMMENT= A Verilog HDL simulator USE_BZIP2= yes |