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authorWill Andrews <will@FreeBSD.org>2003-05-16 18:18:38 +0000
committerWill Andrews <will@FreeBSD.org>2003-05-16 18:18:38 +0000
commite388d96ffa3835bd40f22a747707687f40be3ba6 (patch)
treea8e168149b9edb4e1c9f08d2aaa11c129b8833d9 /cad/iverilog/Makefile
parentd6e0250678400cac81a8aa7be33fea225ca7301a (diff)
Notes
Diffstat (limited to 'cad/iverilog/Makefile')
-rw-r--r--cad/iverilog/Makefile2
1 files changed, 0 insertions, 2 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 9a2d3da7a67c..da95c1926c41 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -15,8 +15,6 @@ DISTNAME= verilog-${PORTVERSION}
MAINTAINER= keichii@FreeBSD.org
COMMENT= Icarus Verilog is a Verilog simulation and synthesis tool
-BROKEN= "Does not install"
-
GNU_CONFIGURE= yes
USE_BISON= yes