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| author | Mark Linimon <linimon@FreeBSD.org> | 2003-10-27 10:02:34 +0000 |
|---|---|---|
| committer | Mark Linimon <linimon@FreeBSD.org> | 2003-10-27 10:02:34 +0000 |
| commit | 09752ef2627f83c9991f40b9232d0ccbdad9b118 (patch) | |
| tree | da42765adb8dd5e3a136fe212db08b4897a36e33 /cad/iverilog/Makefile | |
| parent | a8472f59813a2cd2cb7227701e70ca4b974dcae4 (diff) | |
| download | ports-09752ef2627f83c9991f40b9232d0ccbdad9b118.tar.gz ports-09752ef2627f83c9991f40b9232d0ccbdad9b118.zip | |
Notes
Diffstat (limited to 'cad/iverilog/Makefile')
| -rw-r--r-- | cad/iverilog/Makefile | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index e0ce997f4240..ca06116e2638 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -7,12 +7,10 @@ # PORTNAME= iverilog -PORTVERSION= 0.7.20030722 +PORTVERSION= 0.7.20031009 CATEGORIES= cad -#MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ -#DISTNAME= verilog-${PORTVERSION} MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ -DISTNAME= verilog-20030722 +DISTNAME= verilog-20031009 MAINTAINER= watchman@ludd.luth.se COMMENT= A Verilog simulation and synthesis tool |