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| author | Kris Kennaway <kris@FreeBSD.org> | 2003-05-06 07:23:45 +0000 |
|---|---|---|
| committer | Kris Kennaway <kris@FreeBSD.org> | 2003-05-06 07:23:45 +0000 |
| commit | 55f0f920a187efb1504e4038abe6b636af4eba76 (patch) | |
| tree | 7c84ff7ea3cb75224c06af20f90d400d89633f91 /cad/iverilog/Makefile | |
| parent | 88962b937b6673b3fda0abe1a79a021253d98a9e (diff) | |
| download | ports-55f0f920a187efb1504e4038abe6b636af4eba76.tar.gz ports-55f0f920a187efb1504e4038abe6b636af4eba76.zip | |
Notes
Diffstat (limited to 'cad/iverilog/Makefile')
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index da95c1926c41..9a2d3da7a67c 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -15,6 +15,8 @@ DISTNAME= verilog-${PORTVERSION} MAINTAINER= keichii@FreeBSD.org COMMENT= Icarus Verilog is a Verilog simulation and synthesis tool +BROKEN= "Does not install" + GNU_CONFIGURE= yes USE_BISON= yes |