diff options
| author | Ying-Chieh Liao <ijliao@FreeBSD.org> | 2001-02-13 11:02:15 +0000 |
|---|---|---|
| committer | Ying-Chieh Liao <ijliao@FreeBSD.org> | 2001-02-13 11:02:15 +0000 |
| commit | 7bf8e1d6ec95024af62dd3fd9af5eeff15b0fedb (patch) | |
| tree | a90b1970ffb0bb245333087f5be7a1ebfc60bb19 /cad/iverilog/Makefile | |
| parent | 65d8850cd8f399fddc2f6676260237801b9cf210 (diff) | |
| download | ports-7bf8e1d6ec95024af62dd3fd9af5eeff15b0fedb.tar.gz ports-7bf8e1d6ec95024af62dd3fd9af5eeff15b0fedb.zip | |
Notes
Diffstat (limited to 'cad/iverilog/Makefile')
| -rw-r--r-- | cad/iverilog/Makefile | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile new file mode 100644 index 000000000000..a85697016343 --- /dev/null +++ b/cad/iverilog/Makefile @@ -0,0 +1,23 @@ +# ex:ts=8 +# New ports collection makefile for: iverilog +# Date created: Feb 13, 2001 +# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org> +# +# $FreeBSD$ +# + +PORTNAME= iverilog +PORTVERSION= 0.4 +CATEGORIES= cad +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ +DISTNAME= verilog-${PORTVERSION} + +MAINTAINER= ijliao@FreeBSD.org + +GNU_CONFIGURE= yes + +USE_GMAKE= yes + +MAN1= iverilog.1 + +.include <bsd.port.mk> |