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| author | Michael C . Wu <keichii@FreeBSD.org> | 2003-05-19 08:24:55 +0000 |
|---|---|---|
| committer | Michael C . Wu <keichii@FreeBSD.org> | 2003-05-19 08:24:55 +0000 |
| commit | 0028c8f9cdde1683cf8fddc638313fa5b2476d89 (patch) | |
| tree | 70ab2288278175ec9b4fafd4f8a7ab98fe672eeb /cad/iverilog/Makefile | |
| parent | f5ba1f5df8a5c2365ec3b91a30eb49a6cbe945c9 (diff) | |
| download | ports-0028c8f9cdde1683cf8fddc638313fa5b2476d89.tar.gz ports-0028c8f9cdde1683cf8fddc638313fa5b2476d89.zip | |
Notes
Diffstat (limited to 'cad/iverilog/Makefile')
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index e441e1a25f97..f1048e3358d0 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -12,7 +12,7 @@ CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ DISTNAME= verilog-${PORTVERSION} -MAINTAINER= keichii@FreeBSD.org +MAINTAINER= watchman@ludd.luth.se COMMENT= A Verilog simulation and synthesis tool USE_BISON= yes |