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| author | Marcus Alves Grando <mnag@FreeBSD.org> | 2005-11-09 21:36:06 +0000 |
|---|---|---|
| committer | Marcus Alves Grando <mnag@FreeBSD.org> | 2005-11-09 21:36:06 +0000 |
| commit | 371f431d81969def6f89982af7f42ef776b9c753 (patch) | |
| tree | 521464f1038dde3cca50421a7f61cb11df3b2f40 /cad/iverilog/Makefile | |
| parent | 31f99597fd09685af725284044957b0ce7024b97 (diff) | |
| download | ports-371f431d81969def6f89982af7f42ef776b9c753.tar.gz ports-371f431d81969def6f89982af7f42ef776b9c753.zip | |
Notes
Diffstat (limited to 'cad/iverilog/Makefile')
| -rw-r--r-- | cad/iverilog/Makefile | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index 59d979997eb0..d3ba518d8539 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -7,10 +7,11 @@ # PORTNAME= iverilog -PORTVERSION= 0.8 +PORTVERSION= 0.8.1 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/ -DISTNAME= verilog-$(PORTVERSION) +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ \ + ftp://ftp.geda.seul.org/pub/geda/dist/ +DISTNAME= verilog-${PORTVERSION} MAINTAINER= watchman@ludd.ltu.se COMMENT= A Verilog simulation and synthesis tool @@ -18,6 +19,7 @@ COMMENT= A Verilog simulation and synthesis tool USE_BISON= yes USE_GMAKE= yes GNU_CONFIGURE= yes +CONFIGURE_TARGET= --build=${MACHINE_ARCH}-portbld-freebsd${OSREL} MAN1= iverilog-vpi.1 iverilog.1 vvp.1 iverilog-fpga.1 |