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| author | Niclas Zeising <zeising@FreeBSD.org> | 2012-07-03 08:28:34 +0000 |
|---|---|---|
| committer | Niclas Zeising <zeising@FreeBSD.org> | 2012-07-03 08:28:34 +0000 |
| commit | ddd37c75c939e8b158db1de3511633cc5a463bd3 (patch) | |
| tree | 6b32060e7e894ba199754b6fe16f5ec4a6b3d1ab /cad/iverilog | |
| parent | 67e67f636c9aab0ec85b3cf92f47077ea831db7f (diff) | |
| download | ports-ddd37c75c939e8b158db1de3511633cc5a463bd3.tar.gz ports-ddd37c75c939e8b158db1de3511633cc5a463bd3.zip | |
Notes
Diffstat (limited to 'cad/iverilog')
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index ba9746180fd3..587be4031ce8 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -13,7 +13,7 @@ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \ ftp://ftp.geda.seul.org/pub/geda/dist/ DISTNAME= verilog-${PORTVERSION} -MAINTAINER= zeising@daemonic.se +MAINTAINER= zeising@FreeBSD.org COMMENT= A Verilog simulation and synthesis tool LICENSE= GPLv2 |