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authorMark Linimon <linimon@FreeBSD.org>2005-10-12 06:25:10 +0000
committerMark Linimon <linimon@FreeBSD.org>2005-10-12 06:25:10 +0000
commitf5b7121c2a1a05a51ea1271056dbf262d384bd7f (patch)
tree05755f8c40d6a889602f9fd40eb41aca93806df6 /cad/iverilog
parentd679a21225d38c249b297dad3bc768a5210a7f79 (diff)
downloadports-f5b7121c2a1a05a51ea1271056dbf262d384bd7f.tar.gz
ports-f5b7121c2a1a05a51ea1271056dbf262d384bd7f.zip
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Diffstat (limited to 'cad/iverilog')
-rw-r--r--cad/iverilog/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 40d7f16f6b1d..59d979997eb0 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -12,7 +12,7 @@ CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/
DISTNAME= verilog-$(PORTVERSION)
-MAINTAINER= watchman@ludd.luth.se
+MAINTAINER= watchman@ludd.ltu.se
COMMENT= A Verilog simulation and synthesis tool
USE_BISON= yes