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| author | Sunpoet Po-Chuan Hsieh <sunpoet@FreeBSD.org> | 2017-10-12 08:09:44 +0000 |
|---|---|---|
| committer | Sunpoet Po-Chuan Hsieh <sunpoet@FreeBSD.org> | 2017-10-12 08:09:44 +0000 |
| commit | 02ff99a14770d0b9ba276031c4ea1ace73c272b8 (patch) | |
| tree | 0a0cbb933d087bbf1ad0903fbe6176128c58bff2 /cad/p5-Verilog-Perl | |
| parent | 3b482ca6aae73af87c4788524a8b687b9037ecd4 (diff) | |
| download | ports-02ff99a14770d0b9ba276031c4ea1ace73c272b8.tar.gz ports-02ff99a14770d0b9ba276031c4ea1ace73c272b8.zip | |
Convert to test framework
Approved by: portmgr (blanket)
Notes
Notes:
svn path=/head/; revision=451814
Diffstat (limited to 'cad/p5-Verilog-Perl')
| -rw-r--r-- | cad/p5-Verilog-Perl/Makefile | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile index ef676c8a61e1..bba6a7b18bc5 100644 --- a/cad/p5-Verilog-Perl/Makefile +++ b/cad/p5-Verilog-Perl/Makefile @@ -24,7 +24,4 @@ post-install: ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so -regression-test: build - make test -C ${WRKSRC} - .include <bsd.port.mk> |