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authorYuri Victorovich <yuri@FreeBSD.org>2020-10-15 22:11:24 +0000
committerYuri Victorovich <yuri@FreeBSD.org>2020-10-15 22:11:24 +0000
commit874edc67e15464675323e8a79682e1589b93e586 (patch)
tree92b874b1702b130f0e6554077a436e9fc02c73e7 /cad/verilator
parent5b61acb3072b223fb05ebaec4529639240946046 (diff)
Notes
Diffstat (limited to 'cad/verilator')
-rw-r--r--cad/verilator/Makefile6
-rw-r--r--cad/verilator/distinfo8
2 files changed, 4 insertions, 10 deletions
diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index 319f3e45c4ad..ca0cae9f42a4 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,14 +1,10 @@
# $FreeBSD$
PORTNAME= verilator
-DISTVERSION= 4.100
-PORTREVISION= 1
+DISTVERSION= 4.102
CATEGORIES= cad
MASTER_SITES= https://www.veripool.org/ftp/
-PATCH_SITES= https://github.com/${PORTNAME}/${PORTNAME}/commit/
-PATCHFILES= d750a54e90df1161cfe9502ca56f298005283372.diff:-p1 # make->gmake patch
-
MAINTAINER= yuri@FreeBSD.org
COMMENT= Synthesizable Verilog to C++ compiler
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index 3626ed9e64b6..933d7129853c 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,5 +1,3 @@
-TIMESTAMP = 1600224270
-SHA256 (verilator-4.100.tgz) = 22db8132209849bc09f567c48fe1eebea272102aa7b8eb1e39df520cc37ce16d
-SIZE (verilator-4.100.tgz) = 2747140
-SHA256 (d750a54e90df1161cfe9502ca56f298005283372.diff) = 27454dbaa502d0cd2e815416e659062a408a760d48604e18d8401499cebfa1de
-SIZE (d750a54e90df1161cfe9502ca56f298005283372.diff) = 500
+TIMESTAMP = 1602797123
+SHA256 (verilator-4.102.tgz) = 7c74f2ac4a0e8c1dbcbcf06e998dc8a389bb29469d7f491588470b859a0b8d5d
+SIZE (verilator-4.102.tgz) = 2767422