diff options
| author | Stanislav Sedov <stas@FreeBSD.org> | 2006-11-01 23:28:09 +0000 |
|---|---|---|
| committer | Stanislav Sedov <stas@FreeBSD.org> | 2006-11-01 23:28:09 +0000 |
| commit | 6538ef1938cc093b968c947a712868ba14a950a0 (patch) | |
| tree | fa8a76cd2aaca8ba00516abc0d3684ad02b6646f /cad | |
| parent | c48809861c3b858d85255a219e210f6ca306259c (diff) | |
| download | ports-6538ef1938cc093b968c947a712868ba14a950a0.tar.gz ports-6538ef1938cc093b968c947a712868ba14a950a0.zip | |
Notes
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/iverilog/Makefile | 2 | ||||
| -rw-r--r-- | cad/iverilog/distinfo | 6 | ||||
| -rw-r--r-- | cad/iverilog/files/patch-PExpr.h | 11 | ||||
| -rw-r--r-- | cad/iverilog/files/patch-vvp_decoder.cc | 10 |
4 files changed, 14 insertions, 15 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index d4e46495664a..26ea60f17d2c 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -7,7 +7,7 @@ # PORTNAME= iverilog -PORTVERSION= 0.8.2 +PORTVERSION= 0.8.3 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \ ftp://ftp.geda.seul.org/pub/geda/dist/ diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo index 3839ccbfffaf..82a7f6293c1f 100644 --- a/cad/iverilog/distinfo +++ b/cad/iverilog/distinfo @@ -1,3 +1,3 @@ -MD5 (verilog-0.8.2.tar.gz) = 41650504e4460508a0800008a2628e07 -SHA256 (verilog-0.8.2.tar.gz) = c0df02855d547b0b73d3c020f4cc884319fde8f449ab216abcb685639ff69f08 -SIZE (verilog-0.8.2.tar.gz) = 1526676 +MD5 (verilog-0.8.3.tar.gz) = ba39ba4a708908453c492acb529682f8 +SHA256 (verilog-0.8.3.tar.gz) = 799a20a193ba34d74a14128f1f4494714619a035adad967283dc51c7b994079d +SIZE (verilog-0.8.3.tar.gz) = 1568131 diff --git a/cad/iverilog/files/patch-PExpr.h b/cad/iverilog/files/patch-PExpr.h deleted file mode 100644 index 90c8212cef47..000000000000 --- a/cad/iverilog/files/patch-PExpr.h +++ /dev/null @@ -1,11 +0,0 @@ ---- PExpr.h.orig Mon Oct 2 20:26:17 2006 -+++ PExpr.h Mon Oct 2 20:26:23 2006 -@@ -324,7 +324,7 @@ - virtual NetEConst*elaborate_expr(Design*des, NetScope*, - bool sys_task_arg =false) const; - virtual NetEConst*elaborate_pexpr(Design*des, NetScope*sc) const; -- verinum* PEString::eval_const(const Design*, const NetScope*) const; -+ verinum* eval_const(const Design*, const NetScope*) const; - - virtual bool is_constant(Module*) const; - diff --git a/cad/iverilog/files/patch-vvp_decoder.cc b/cad/iverilog/files/patch-vvp_decoder.cc new file mode 100644 index 000000000000..8d64bcab031c --- /dev/null +++ b/cad/iverilog/files/patch-vvp_decoder.cc @@ -0,0 +1,10 @@ +--- vvp/decoder.cc.orig Thu Nov 2 02:00:59 2006 ++++ vvp/decoder.cc Thu Nov 2 02:01:07 2006 +@@ -22,7 +22,6 @@ + # include "functor.h" + # include "symbols.h" + # include <stdlib.h> +-# include <malloc.h> + # include <limits.h> + # include <assert.h> + |