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| author | Mark Linimon <linimon@FreeBSD.org> | 2003-11-20 03:19:37 +0000 |
|---|---|---|
| committer | Mark Linimon <linimon@FreeBSD.org> | 2003-11-20 03:19:37 +0000 |
| commit | e08f6b73c86f96b891e7c9d3c74e5ed68135f7d5 (patch) | |
| tree | f2e34257d7bd2fb9d49864a4ebef0b8cbcb4f868 /cad | |
| parent | 154b41c5dc364ac54d0338ca0bfce846596af632 (diff) | |
| download | ports-e08f6b73c86f96b891e7c9d3c74e5ed68135f7d5.tar.gz ports-e08f6b73c86f96b891e7c9d3c74e5ed68135f7d5.zip | |
Notes
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index ca06116e2638..e805d41232e4 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -15,6 +15,8 @@ DISTNAME= verilog-20031009 MAINTAINER= watchman@ludd.luth.se COMMENT= A Verilog simulation and synthesis tool +BROKEN= "fails to compile - missing definition of TIME_FMT" + USE_BISON= yes USE_GMAKE= yes GNU_CONFIGURE= yes |