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| author | Thomas Abthorpe <tabthorpe@FreeBSD.org> | 2008-10-27 15:59:26 +0000 |
|---|---|---|
| committer | Thomas Abthorpe <tabthorpe@FreeBSD.org> | 2008-10-27 15:59:26 +0000 |
| commit | 120ddc52c0b9b8127e8de4e528c4b74099b336bc (patch) | |
| tree | 7819df3364ca5c8e6c3410ff68f4dbd52d2c63fa /cad | |
| parent | 277671106d5518db0421b5b4c9fec0fde5ab686c (diff) | |
| download | ports-120ddc52c0b9b8127e8de4e528c4b74099b336bc.tar.gz ports-120ddc52c0b9b8127e8de4e528c4b74099b336bc.zip | |
Notes
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/gplcver/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile index a5a265d42a4f..2fc1d7dab79f 100644 --- a/cad/gplcver/Makefile +++ b/cad/gplcver/Makefile @@ -12,7 +12,7 @@ CATEGORIES= cad MASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/ DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src -MAINTAINER= tabthorpe@FreeBSD.org +MAINTAINER= ports@FreeBSD.org COMMENT= A Verilog HDL simulator USE_BZIP2= yes |