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| author | Emanuel Haupt <ehaupt@FreeBSD.org> | 2014-02-27 13:43:27 +0000 |
|---|---|---|
| committer | Emanuel Haupt <ehaupt@FreeBSD.org> | 2014-02-27 13:43:27 +0000 |
| commit | 73593f9a63a2b12c5b8fa2ead037dbf9ed44499a (patch) | |
| tree | dfcaca21c3ebe322b1d63d8dcd695353468e5e48 /cad | |
| parent | 5039a94cdebd9be471ee169f9508e99ddae8c980 (diff) | |
| download | ports-73593f9a63a2b12c5b8fa2ead037dbf9ed44499a.tar.gz ports-73593f9a63a2b12c5b8fa2ead037dbf9ed44499a.zip | |
Notes
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/gplcver/Makefile | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile index 2d3bc53f6ceb..b056f6edbfa3 100644 --- a/cad/gplcver/Makefile +++ b/cad/gplcver/Makefile @@ -10,17 +10,15 @@ DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src MAINTAINER= ports@FreeBSD.org COMMENT= A Verilog HDL simulator +USES= gmake USE_BZIP2= yes + BUILD_WRKSRC= ${WRKSRC}/src -USE_GMAKE= yes MAKEFILE= makefile.freebsd PLIST_FILES= bin/cver -NO_STAGE= yes -.include <bsd.port.pre.mk> - do-install: - ${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${PREFIX}/bin + ${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${STAGEDIR}${PREFIX}/bin -.include <bsd.port.post.mk> +.include <bsd.port.mk> |