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| author | Thomas Abthorpe <tabthorpe@FreeBSD.org> | 2007-08-23 04:00:04 +0000 |
|---|---|---|
| committer | Thomas Abthorpe <tabthorpe@FreeBSD.org> | 2007-08-23 04:00:04 +0000 |
| commit | 2574f69107121a3cc7cb9276abdedad5a76633c7 (patch) | |
| tree | b84cefc010abb1b2c1857ccf9deb2c66f6c9c5db /cad | |
| parent | 8a995f807e832d704dcfaad599b44b0b7434bc8a (diff) | |
| download | ports-2574f69107121a3cc7cb9276abdedad5a76633c7.tar.gz ports-2574f69107121a3cc7cb9276abdedad5a76633c7.zip | |
Notes
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/gplcver/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile index 561f9293d846..a5a265d42a4f 100644 --- a/cad/gplcver/Makefile +++ b/cad/gplcver/Makefile @@ -12,7 +12,7 @@ CATEGORIES= cad MASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/ DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src -MAINTAINER= thomas@goodking.ca +MAINTAINER= tabthorpe@FreeBSD.org COMMENT= A Verilog HDL simulator USE_BZIP2= yes |