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| author | Yuri Victorovich <yuri@FreeBSD.org> | 2021-08-25 20:24:58 +0000 |
|---|---|---|
| committer | Yuri Victorovich <yuri@FreeBSD.org> | 2021-08-25 20:28:24 +0000 |
| commit | f41cab0fade0722df7e0b5c34ace200967399ea7 (patch) | |
| tree | 7c9fecf7081a37c88cb1b90a49ccfe335427d975 /cad | |
| parent | 7890177363343a64e52af7a50dc9366d8eb837a0 (diff) | |
| download | ports-f41cab0fade0722df7e0b5c34ace200967399ea7.tar.gz ports-f41cab0fade0722df7e0b5c34ace200967399ea7.zip | |
cad/verilator: Backport the fix of bug that caused wrong C++ code generation
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/verilator/Makefile | 4 | ||||
| -rw-r--r-- | cad/verilator/distinfo | 4 |
2 files changed, 7 insertions, 1 deletions
diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile index 7cecedcda41b..5f7e8d0323f2 100644 --- a/cad/verilator/Makefile +++ b/cad/verilator/Makefile @@ -1,8 +1,12 @@ PORTNAME= verilator DISTVERSION= 4.210 +PORTREVISION= 1 CATEGORIES= cad MASTER_SITES= https://www.veripool.org/ftp/ +PATCH_SITES= https://github.com/verilator/verilator/commit/ +PATCHFILES= 9907d211ff5fa408a7eb6387ef0ceaedaeea2d32.patch:-p1 # backport of bug fix: https://github.com/verilator/verilator/commit/9907d211ff5fa408a7eb6387ef0ceaedaeea2d32 + MAINTAINER= yuri@FreeBSD.org COMMENT= Synthesizable Verilog to C++ compiler diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo index cb22cc780c7a..3f71f9bc0120 100644 --- a/cad/verilator/distinfo +++ b/cad/verilator/distinfo @@ -1,3 +1,5 @@ -TIMESTAMP = 1627977232 +TIMESTAMP = 1629920311 SHA256 (verilator-4.210.tgz) = 2a821f25e5766884e7c22076790810a386725df31ee9eac58862977b347e2018 SIZE (verilator-4.210.tgz) = 3229756 +SHA256 (9907d211ff5fa408a7eb6387ef0ceaedaeea2d32.patch) = 52418f475136134e139e70fcdacaedd9f2baa1cd17daa5c0d7e72054dcf87024 +SIZE (9907d211ff5fa408a7eb6387ef0ceaedaeea2d32.patch) = 2303 |