diff options
| author | Marcelo Araujo <araujo@FreeBSD.org> | 2012-02-06 04:35:27 +0000 |
|---|---|---|
| committer | Marcelo Araujo <araujo@FreeBSD.org> | 2012-02-06 04:35:27 +0000 |
| commit | f23ff56aea72ef3c086cc34b76efb8917aafb0fa (patch) | |
| tree | 718a1838c2368c54ac7167b2ecd6fd9312a7bb18 /devel | |
| parent | 6b99916c82401c6f70d1c93567c265ff8b885c6e (diff) | |
| download | ports-f23ff56aea72ef3c086cc34b76efb8917aafb0fa.tar.gz ports-f23ff56aea72ef3c086cc34b76efb8917aafb0fa.zip | |
Notes
Diffstat (limited to 'devel')
17 files changed, 283 insertions, 287 deletions
diff --git a/devel/psptoolchain-gdb/Makefile b/devel/psptoolchain-gdb/Makefile index fe0635b96bbb..6bb49b16050d 100644 --- a/devel/psptoolchain-gdb/Makefile +++ b/devel/psptoolchain-gdb/Makefile @@ -6,7 +6,7 @@ # PORTNAME= gdb -PORTVERSION= 6.4 +PORTVERSION= 7.3.1 CATEGORIES= devel MASTER_SITES= ${MASTER_SITE_GNU} MASTER_SITE_SUBDIR= ${PORTNAME}/ @@ -21,7 +21,12 @@ USE_BZIP2= yes USE_GMAKE= yes HAS_CONFIGURE= yes -CONFIGURE_ARGS?= --prefix=${PREFIX} --target="psp" --disable-nls --disable-install-libiberty +CONFIGURE_ARGS= --prefix=${PREFIX} \ + --target="psp" \ + --disable-werror \ + --disable-nls \ + --disable-install-libiberty \ + --mandir=${PREFIX}/man MAN1= psp-gdb.1 \ psp-gdbtui.1 \ @@ -31,7 +36,7 @@ MAN1= psp-gdb.1 \ post-patch: @${REINPLACE_CMD} -E 's/^(INFO_DEPS.*=)(.*)/\1#\2/' ${WRKSRC}/bfd/doc/Makefile.in @${REINPLACE_CMD} -E 's/^(INFO_DEPS.*=)(.*)/\1#\2/' ${WRKSRC}/gdb/doc/Makefile.in - @${REINPLACE_CMD} -E 's/^(install:.*)(install-info.*)/\1#\2/' ${WRKSRC}/etc/Makefile.in + @${REINPLACE_CMD} -E 's/^(install.*:.*)install-info(.*)/\1\2/' ${WRKSRC}/etc/Makefile.in @${REINPLACE_CMD} -E 's/^(install:)(.*)/\1#\2/' ${WRKSRC}/libiberty/Makefile.in .include <bsd.port.mk> diff --git a/devel/psptoolchain-gdb/distinfo b/devel/psptoolchain-gdb/distinfo index 1316a71b87fe..29f873181f39 100644 --- a/devel/psptoolchain-gdb/distinfo +++ b/devel/psptoolchain-gdb/distinfo @@ -1,2 +1,2 @@ -SHA256 (gdb-6.4.tar.bz2) = af6777836ab72b563a9e55467f990250e07e56c292cfac98762745c1512167ef -SIZE (gdb-6.4.tar.bz2) = 13917226 +SHA256 (gdb-7.3.1.tar.bz2) = 6d7bff716fde98d03866a1b747c0929ee7dba49bca13e01d975e0b0fa9b33a28 +SIZE (gdb-7.3.1.tar.bz2) = 19500995 diff --git a/devel/psptoolchain-gdb/files/patch-bfd-archures.c b/devel/psptoolchain-gdb/files/patch-bfd-archures.c index 09d5b976f73f..c5cbe0f231e0 100644 --- a/devel/psptoolchain-gdb/files/patch-bfd-archures.c +++ b/devel/psptoolchain-gdb/files/patch-bfd-archures.c @@ -1,10 +1,10 @@ ---- bfd/archures.c.orig 2005-10-25 18:40:09.000000000 +0100 -+++ bfd/archures.c 2007-02-08 20:06:04.000000000 +0000 -@@ -154,6 +154,7 @@ - .#define bfd_mach_mips16 16 - .#define bfd_mach_mips5 5 +--- ./bfd/archures.c.orig 2011-03-22 18:10:41.000000000 +0000 ++++ ./bfd/archures.c 2012-01-25 22:24:29.000000000 +0000 +@@ -175,6 +175,7 @@ + .#define bfd_mach_mips_loongson_2f 3002 + .#define bfd_mach_mips_loongson_3a 3003 .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *} +.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *} + .#define bfd_mach_mips_octeon 6501 + .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} .#define bfd_mach_mipsisa32 32 - .#define bfd_mach_mipsisa32r2 33 - .#define bfd_mach_mipsisa64 64 diff --git a/devel/psptoolchain-gdb/files/patch-bfd-bfd-in2.h b/devel/psptoolchain-gdb/files/patch-bfd-bfd-in2.h index 57003777bbab..22dbd818a04b 100644 --- a/devel/psptoolchain-gdb/files/patch-bfd-bfd-in2.h +++ b/devel/psptoolchain-gdb/files/patch-bfd-bfd-in2.h @@ -1,10 +1,10 @@ ---- bfd/bfd-in2.h.orig 2005-10-25 18:40:09.000000000 +0100 -+++ bfd/bfd-in2.h 2007-02-08 20:06:04.000000000 +0000 -@@ -1742,6 +1742,7 @@ - #define bfd_mach_mips16 16 - #define bfd_mach_mips5 5 +--- ./bfd/bfd-in2.h.orig 2011-03-31 08:58:19.000000000 +0000 ++++ ./bfd/bfd-in2.h 2012-01-25 22:24:29.000000000 +0000 +@@ -1862,6 +1862,7 @@ + #define bfd_mach_mips_loongson_2f 3002 + #define bfd_mach_mips_loongson_3a 3003 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ +#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */ + #define bfd_mach_mips_octeon 6501 + #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ #define bfd_mach_mipsisa32 32 - #define bfd_mach_mipsisa32r2 33 - #define bfd_mach_mipsisa64 64 diff --git a/devel/psptoolchain-gdb/files/patch-bfd-cpu-mips.c b/devel/psptoolchain-gdb/files/patch-bfd-cpu-mips.c index 6cc30abb2691..3e777dd1b5b2 100644 --- a/devel/psptoolchain-gdb/files/patch-bfd-cpu-mips.c +++ b/devel/psptoolchain-gdb/files/patch-bfd-cpu-mips.c @@ -1,20 +1,18 @@ ---- bfd/cpu-mips.c.orig 2005-05-04 16:53:06.000000000 +0100 -+++ bfd/cpu-mips.c 2007-02-08 20:06:04.000000000 +0000 -@@ -86,6 +86,7 @@ +--- ./bfd/cpu-mips.c.orig 2010-11-17 09:32:42.000000000 +0000 ++++ ./bfd/cpu-mips.c 2012-01-25 22:24:29.000000000 +0000 +@@ -89,6 +89,7 @@ I_mipsisa64, I_mipsisa64r2, I_sb1, + I_allegrex, - }; - - #define NN(index) (&arch_info_struct[(index) + 1]) -@@ -118,7 +119,8 @@ - N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), + I_loongson_2e, + I_loongson_2f, + I_loongson_3a, +@@ -129,6 +130,7 @@ N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), -- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0), -+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)), -+ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0), - }; - - /* The default architecture is mips:3000, but with a machine number of + N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)), ++ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, NN(I_allegrex)), + N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)), + N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)), + N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)), diff --git a/devel/psptoolchain-gdb/files/patch-bfd-elfxx-mips.c b/devel/psptoolchain-gdb/files/patch-bfd-elfxx-mips.c index 69b7f6c60b15..a7a0fbc1bb45 100644 --- a/devel/psptoolchain-gdb/files/patch-bfd-elfxx-mips.c +++ b/devel/psptoolchain-gdb/files/patch-bfd-elfxx-mips.c @@ -1,27 +1,26 @@ ---- bfd/elfxx-mips.c.orig 2005-10-25 17:19:08.000000000 +0100 -+++ bfd/elfxx-mips.c 2007-02-08 20:06:04.000000000 +0000 -@@ -4666,6 +4666,9 @@ +--- ./bfd/elfxx-mips.c.orig 2011-01-22 10:16:28.000000000 +0000 ++++ ./bfd/elfxx-mips.c 2012-01-25 22:24:29.000000000 +0000 +@@ -5940,14 +5940,19 @@ case E_MIPS_MACH_SB1: return bfd_mach_mips_sb1; + case E_MIPS_MACH_ALLEGREX: + return bfd_mach_mips_allegrex; + - default: - switch (flags & EF_MIPS_ARCH) - { -@@ -7950,6 +7953,10 @@ - val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1; - break; + case E_MIPS_MACH_LS2E: + return bfd_mach_mips_loongson_2e; -+ case bfd_mach_mips_allegrex: -+ val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX; -+ break; -+ - case bfd_mach_mipsisa32: - val = E_MIPS_ARCH_32; - break; -@@ -9648,6 +9655,7 @@ + case E_MIPS_MACH_LS2F: + return bfd_mach_mips_loongson_2f; + ++ /* + case E_MIPS_MACH_LS3A: + return bfd_mach_mips_loongson_3a; ++ */ + + case E_MIPS_MACH_OCTEON: + return bfd_mach_mips_octeon; +@@ -12311,6 +12316,7 @@ /* MIPS II extensions. */ { bfd_mach_mips4000, bfd_mach_mips6000 }, { bfd_mach_mipsisa32, bfd_mach_mips6000 }, diff --git a/devel/psptoolchain-gdb/files/patch-bfd-sysdep.h b/devel/psptoolchain-gdb/files/patch-bfd-sysdep.h new file mode 100644 index 000000000000..3ac30aee82a1 --- /dev/null +++ b/devel/psptoolchain-gdb/files/patch-bfd-sysdep.h @@ -0,0 +1,11 @@ +--- ./bfd/sysdep.h.orig 2009-09-02 07:18:37.000000000 +0000 ++++ ./bfd/sysdep.h 2012-01-25 22:24:22.000000000 +0000 +@@ -131,7 +131,7 @@ + extern PTR realloc (); + #endif + +-#if !HAVE_DECL_STPCPY ++#if !HAVE_DECL_STPCPY && !defined(stpcpy) + extern char *stpcpy (char *__dest, const char *__src); + #endif + diff --git a/devel/psptoolchain-gdb/files/patch-config.sub b/devel/psptoolchain-gdb/files/patch-config.sub index 3c47d3f94762..2c81d004c3cf 100644 --- a/devel/psptoolchain-gdb/files/patch-config.sub +++ b/devel/psptoolchain-gdb/files/patch-config.sub @@ -1,22 +1,22 @@ ---- config.sub.orig 2005-07-14 02:24:56.000000000 +0100 -+++ config.sub 2007-02-08 20:06:04.000000000 +0000 -@@ -256,6 +256,7 @@ +--- ./config.sub.orig 2011-03-24 11:13:32.000000000 +0000 ++++ ./config.sub 2012-01-25 22:24:29.000000000 +0000 +@@ -279,6 +279,7 @@ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ + | mipsallegrex | mipsallegrexel \ | mn10200 | mn10300 \ - | ms1 \ - | msp430 \ -@@ -335,6 +336,7 @@ + | moxie \ + | mt \ +@@ -388,6 +389,7 @@ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ + | mipsallegrex-* | mipsallegrexel-* \ | mmix-* \ - | ms1-* \ + | mt-* \ | msp430-* \ -@@ -678,6 +680,10 @@ +@@ -785,6 +787,10 @@ basic_machine=m68k-atari os=-mint ;; diff --git a/devel/psptoolchain-gdb/files/patch-gdb-remote.c b/devel/psptoolchain-gdb/files/patch-gdb-remote.c deleted file mode 100644 index 5864447b0420..000000000000 --- a/devel/psptoolchain-gdb/files/patch-gdb-remote.c +++ /dev/null @@ -1,32 +0,0 @@ ---- gdb/remote.c.orig 2005-07-20 03:56:43.000000000 +0100 -+++ gdb/remote.c 2007-02-08 20:06:12.000000000 +0000 -@@ -1953,6 +1953,7 @@ - int lose; - CORE_ADDR text_addr, data_addr, bss_addr; - struct section_offsets *offs; -+ int i; - - putpkt ("qOffsets"); - -@@ -2014,6 +2015,13 @@ - memcpy (offs, symfile_objfile->section_offsets, - SIZEOF_N_SECTION_OFFSETS (symfile_objfile->num_sections)); - -+ /* GDB is stupid, lets fix up all sections to the same address not just a few :P */ -+ -+ for(i = 0; i < symfile_objfile->num_sections; i++) -+ { -+ offs->offsets[i] = text_addr; -+ } -+#if 0 - offs->offsets[SECT_OFF_TEXT (symfile_objfile)] = text_addr; - - /* This is a temporary kludge to force data and bss to use the same offsets -@@ -2022,6 +2030,7 @@ - - offs->offsets[SECT_OFF_DATA (symfile_objfile)] = data_addr; - offs->offsets[SECT_OFF_BSS (symfile_objfile)] = data_addr; -+#endif - - objfile_relocate (symfile_objfile, offs); - } diff --git a/devel/psptoolchain-gdb/files/patch-include-bin-bugs.h b/devel/psptoolchain-gdb/files/patch-include-bin-bugs.h deleted file mode 100644 index d1894be13b6c..000000000000 --- a/devel/psptoolchain-gdb/files/patch-include-bin-bugs.h +++ /dev/null @@ -1,7 +0,0 @@ ---- include/bin-bugs.h.orig 2004-07-23 16:40:19.000000000 +0100 -+++ include/bin-bugs.h 2007-02-08 20:06:04.000000000 +0000 -@@ -1,3 +1,3 @@ - #ifndef REPORT_BUGS_TO --#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>" -+#define REPORT_BUGS_TO "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>" - #endif diff --git a/devel/psptoolchain-gdb/files/patch-include-elf-common.h b/devel/psptoolchain-gdb/files/patch-include-elf-common.h index 8c41452d02af..f8ba6565e745 100644 --- a/devel/psptoolchain-gdb/files/patch-include-elf-common.h +++ b/devel/psptoolchain-gdb/files/patch-include-elf-common.h @@ -1,10 +1,10 @@ ---- include/elf/common.h.orig 2005-09-30 16:12:52.000000000 +0100 -+++ include/elf/common.h 2007-02-08 20:06:04.000000000 +0000 -@@ -93,6 +93,7 @@ +--- ./include/elf/common.h.orig 2011-03-10 10:23:37.000000000 +0000 ++++ ./include/elf/common.h 2012-01-25 22:24:29.000000000 +0000 +@@ -96,6 +96,7 @@ #define ET_HIOS 0xFEFF /* Operating system-specific */ #define ET_LOPROC 0xFF00 /* Processor-specific */ #define ET_HIPROC 0xFFFF /* Processor-specific */ -+#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */ ++#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */ /* Values for e_machine, which identifies the architecture. These numbers - are officially assigned by registry@caldera.com. See below for a list of + are officially assigned by registry@sco.com. See below for a list of diff --git a/devel/psptoolchain-gdb/files/patch-include-elf-mips.h b/devel/psptoolchain-gdb/files/patch-include-elf-mips.h index f05c78ebf5e1..d427096918a3 100644 --- a/devel/psptoolchain-gdb/files/patch-include-elf-mips.h +++ b/devel/psptoolchain-gdb/files/patch-include-elf-mips.h @@ -1,10 +1,10 @@ ---- include/elf/mips.h.orig 2005-05-10 11:21:10.000000000 +0100 -+++ include/elf/mips.h 2007-02-08 20:06:04.000000000 +0000 -@@ -212,6 +212,7 @@ +--- ./include/elf/mips.h.orig 2010-11-11 10:23:38.000000000 +0000 ++++ ./include/elf/mips.h 2012-01-25 22:24:29.000000000 +0000 +@@ -220,6 +220,7 @@ #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5500 0x00980000 #define E_MIPS_MACH_9000 0x00990000 +#define E_MIPS_MACH_ALLEGREX 0x00A20000 - - /* Processor specific section indices. These sections do not actually - exist. Symbols with a st_shndx field corresponding to one of these + #define E_MIPS_MACH_LS2E 0x00A00000 + #define E_MIPS_MACH_LS2F 0x00A10000 + #define E_MIPS_MACH_LS3A 0x00A20000 diff --git a/devel/psptoolchain-gdb/files/patch-include-opcode-mips.h b/devel/psptoolchain-gdb/files/patch-include-opcode-mips.h index 77a9b3d7bbe7..cea54ec13f0e 100644 --- a/devel/psptoolchain-gdb/files/patch-include-opcode-mips.h +++ b/devel/psptoolchain-gdb/files/patch-include-opcode-mips.h @@ -1,8 +1,8 @@ ---- include/opcode/mips.h.orig 2005-09-06 19:42:58.000000000 +0100 -+++ include/opcode/mips.h 2007-02-08 20:06:04.000000000 +0000 -@@ -203,6 +203,83 @@ - #define MDMX_FMTSEL_VEC_QH 0x15 - #define MDMX_FMTSEL_VEC_OB 0x16 +--- ./include/opcode/mips.h.orig 2011-02-28 16:06:51.000000000 +0000 ++++ ./include/opcode/mips.h 2012-01-25 22:24:29.000000000 +0000 +@@ -238,6 +238,83 @@ + #define OP_SH_FZ 0 + #define OP_MASK_FZ 0x1f +#define OP_SH_VFPU_DELTA 0 +#define OP_MASK_VFPU_DELTA 0xfffc @@ -84,7 +84,7 @@ /* This structure holds information for a particular instruction. */ struct mips_opcode -@@ -290,6 +367,29 @@ +@@ -327,6 +404,29 @@ Requires that "+A" or "+E" occur first to set position. Enforces: 32 < (pos+size) <= 64. @@ -114,32 +114,32 @@ Floating point instructions: "D" 5 bit destination register (OP_*_FD) "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) -@@ -500,6 +600,8 @@ - #define INSN_5400 0x01000000 - /* NEC VR5500 instruction. */ - #define INSN_5500 0x02000000 +@@ -620,6 +720,8 @@ + #define INSN_SMARTMIPS 0x10000000 + /* DSP R2 ASE */ + #define INSN_DSPR2 0x20000000 +/* Sony Allegrex instruction. */ -+#define INSN_ALLEGREX 0x10000000 - /* MT ASE */ - #define INSN_MT 0x04000000 - -@@ -549,6 +651,7 @@ ++#define INSN_ALLEGREX 0x40000000 + /* ST Microelectronics Loongson 2E. */ + #define INSN_LOONGSON_2E 0x40000000 + /* ST Microelectronics Loongson 2F. */ +@@ -677,6 +779,7 @@ #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ +#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */ - - /* Test for membership in an ISA including chip specific ISAs. INSN - is pointer to an element of the opcode table; ISA is the specified -@@ -570,6 +673,7 @@ + #define CPU_LOONGSON_2E 3001 + #define CPU_LOONGSON_2F 3002 + #define CPU_LOONGSON_3A 3003 +@@ -709,6 +812,7 @@ || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ + || (cpu == CPU_ALLEGREX && ((insn)->membership & INSN_ALLEGREX) != 0) \ - || 0) /* Please keep this term for easier source merging. */ - - /* This is a list of macro expanded instructions. -@@ -685,6 +789,16 @@ + || (cpu == CPU_LOONGSON_2E \ + && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ + || (cpu == CPU_LOONGSON_2F \ +@@ -835,6 +939,16 @@ M_LL_AB, M_LLD_AB, M_LS_A, @@ -156,7 +156,7 @@ M_LW_A, M_LW_AB, M_LWC0_A, -@@ -774,6 +888,10 @@ +@@ -930,6 +1044,10 @@ M_SUB_I, M_SUBU_I, M_SUBU_I_2, @@ -167,7 +167,7 @@ M_TEQ_I, M_TGE_I, M_TGEU_I, -@@ -788,14 +906,24 @@ +@@ -944,14 +1062,24 @@ M_ULH_A, M_ULHU, M_ULHU_A, diff --git a/devel/psptoolchain-gdb/files/patch-opcodes-mips-dis.c b/devel/psptoolchain-gdb/files/patch-opcodes-mips-dis.c index c174617dba5e..f878c35cb76c 100644 --- a/devel/psptoolchain-gdb/files/patch-opcodes-mips-dis.c +++ b/devel/psptoolchain-gdb/files/patch-opcodes-mips-dis.c @@ -1,6 +1,6 @@ ---- opcodes/mips-dis.c.orig 2005-09-06 19:46:57.000000000 +0100 -+++ opcodes/mips-dis.c 2007-02-08 20:06:04.000000000 +0000 -@@ -133,6 +133,139 @@ +--- ./opcodes/mips-dis.c.orig 2011-01-11 07:22:09.000000000 +0000 ++++ ./opcodes/mips-dis.c 2012-01-25 22:24:29.000000000 +0000 +@@ -160,6 +160,139 @@ "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; @@ -140,7 +140,7 @@ static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { { 16, 1, "c0_config1" }, -@@ -288,6 +421,55 @@ +@@ -386,6 +519,54 @@ "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; @@ -192,20 +192,20 @@ + "", "[0:1]", "", "[-1:1]" +}; + -+ struct mips_abi_choice { const char * name; -@@ -363,6 +545,8 @@ +@@ -465,7 +646,8 @@ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, +- + { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. Note that MIPS-3D and MDMX are not applicable to MIPS32. (See -@@ -1147,6 +1331,349 @@ + _MIPS32 Architecture For Programmers Volume I: Introduction to the +@@ -1365,6 +1547,349 @@ (l >> OP_SH_FT) & OP_MASK_FT); break; diff --git a/devel/psptoolchain-gdb/files/patch-opcodes-mips-opc.c b/devel/psptoolchain-gdb/files/patch-opcodes-mips-opc.c index e5d48d7dc8ba..1d0da76d3bd1 100644 --- a/devel/psptoolchain-gdb/files/patch-opcodes-mips-opc.c +++ b/devel/psptoolchain-gdb/files/patch-opcodes-mips-opc.c @@ -1,14 +1,14 @@ ---- opcodes/mips-opc.c.orig 2005-09-06 19:46:57.000000000 +0100 -+++ opcodes/mips-opc.c 2007-02-08 20:06:04.000000000 +0000 -@@ -109,6 +109,7 @@ +--- ./opcodes/mips-opc.c.orig 2011-02-28 16:34:39.000000000 +0000 ++++ ./opcodes/mips-opc.c 2012-01-25 22:24:29.000000000 +0000 +@@ -120,6 +120,7 @@ #define N5 (INSN_5400 | INSN_5500) #define N54 INSN_5400 #define N55 INSN_5500 +#define AL INSN_ALLEGREX + #define IOCT INSN_OCTEON + #define XLR INSN_XLR - #define G1 (T3 \ - ) -@@ -298,6 +299,7 @@ +@@ -391,6 +392,7 @@ {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, @@ -16,18 +16,18 @@ {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, -@@ -459,7 +461,7 @@ - {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, - {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, - {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, --{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, +@@ -573,7 +575,7 @@ + {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, + {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, + {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, +-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3}, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3|AL}, - {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 }, - {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 }, - {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, -@@ -473,7 +475,9 @@ - {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, - {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, + {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3}, + {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, + {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +@@ -591,7 +593,9 @@ + {"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */ + {"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT }, {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +{"clo", "d,s", 0x00000017, 0xfc1f07ff, WR_d|RD_s, 0, AL }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, @@ -35,65 +35,68 @@ {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, -@@ -498,13 +502,15 @@ - {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +@@ -616,16 +620,16 @@ + {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 }, {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, -+{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL }, ++{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL }, {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, +-{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, -+{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL }, ++{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, + {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR }, -{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL }, {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, /* dctr and dctw are used on the r5000. */ -@@ -593,7 +599,7 @@ +@@ -714,7 +718,7 @@ {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, - {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, - {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, + {"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, + {"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, -{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, +{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5|AL }, {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, -@@ -634,10 +640,10 @@ - {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, +@@ -763,10 +767,10 @@ + {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT}, {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, --{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, -+{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32|AL }, +-{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 }, ++{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32|AL }, {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, -{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, +{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33|AL }, - {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 }, - {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 }, - {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, -@@ -646,7 +652,7 @@ - {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, - {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, + {"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, + {"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */ + {"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +@@ -775,7 +779,7 @@ + {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, + {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, -{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, +{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33|AL }, {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, - {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I33 }, - {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ -@@ -680,18 +686,10 @@ - {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, - {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, - {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, + /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with + the same hazard barrier effect. */ +@@ -817,18 +821,10 @@ + {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, + {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, + {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, -{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, -{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, --{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, --{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, +-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, -{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ --{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, --{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, +-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, @@ -102,162 +105,150 @@ +/* ldc1 is at the bottom of the table. */ +/* ldc2 is at the bottom of the table. */ +/* ldc3 is at the bottom of the table. */ -+{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL }, ++{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL }, {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, -@@ -721,8 +719,7 @@ - {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, +@@ -858,8 +854,7 @@ + {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ - {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, + {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, +/* lwc2 is at the bottom of the table. */ {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, -@@ -755,10 +752,12 @@ - {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 }, - {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, - {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, -+{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, - {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55}, - {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, - {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, - {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, -+{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, - {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55}, - {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +@@ -900,13 +895,13 @@ + {"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, + {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, + {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +-{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, ++{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1|AL }, + {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, + {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, + {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, + {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, + {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +-{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, ++{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1|AL }, + {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, -@@ -799,7 +798,7 @@ + {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, +@@ -945,7 +940,7 @@ + /* mfc2 is at the bottom of the table. */ /* mfhc2 is at the bottom of the table. */ - {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, - {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, + /* mfc3 is at the bottom of the table. */ -{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, +{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5|AL }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, -@@ -818,7 +817,7 @@ +@@ -967,7 +962,7 @@ {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, - {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, - {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, --{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, -+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL }, + {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, + {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, +-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F }, ++{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|AL }, + {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A }, {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, - {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, - {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, -@@ -831,7 +830,7 @@ + {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, +@@ -981,7 +976,7 @@ {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, - {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, - {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, --{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, + {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, + {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, +-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL }, {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, - {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, + {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, -@@ -848,8 +847,10 @@ - {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 }, - {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, +@@ -1010,8 +1005,10 @@ + {"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, -+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, ++{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, + {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, -+{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, ++{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, + {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, - {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, -@@ -864,7 +865,7 @@ +@@ -1026,7 +1023,7 @@ + /* mtc2 is at the bottom of the table. */ /* mthc2 is at the bottom of the table. */ - {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, - {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, + /* mtc3 is at the bottom of the table. */ -{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, +{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5|AL }, {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, -@@ -1018,13 +1019,13 @@ +@@ -1211,13 +1208,13 @@ {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, --{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33 }, --{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33 }, --{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33 }, --{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33 }, --{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33 }, --{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33 }, --{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 }, -+{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|AL }, -+{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|AL }, -+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL }, -+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL }, -+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL }, -+{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL }, -+{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|AL }, - {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 }, - {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 }, - {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, -@@ -1056,24 +1057,17 @@ - {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, - {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, - {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, --{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, --{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, --{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, --{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, --{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, --{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, --{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, --{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, --{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, --{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, --{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, +-{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, +-{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, +-{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, +-{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, +-{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, +-{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, +-{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, ++{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT|AL }, ++{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT|AL }, ++{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT|AL }, ++{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT|AL }, ++{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT|AL }, ++{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT|AL }, ++{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT|AL }, + {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, + {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, + {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +@@ -1261,13 +1258,13 @@ + {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, + {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, + {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, -{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, -+/* sdc1 is at the bottom of the table. */ -+/* sdc2 is at the bottom of the table. */ -+/* sdc3 is at the bottom of the table. */ -+/* s.d (sdc1 is at the bottom of the table. */ +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3|AL }, {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, - {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4 }, + {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 }, -{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, -{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33|AL }, +{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33|AL }, {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, - {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, -@@ -1165,8 +1159,7 @@ - {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, + {"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +@@ -1387,8 +1384,7 @@ + {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ - {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, + {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, +/* swc2 is at the bottom of the table. */ {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, -@@ -1251,7 +1244,8 @@ +@@ -1485,7 +1481,8 @@ + {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, - {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, -{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33|AL }, +{"wsbw", "d,t", 0x7c0000e0, 0xffe007ff, WR_d|RD_t, 0, AL }, {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, - {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, -@@ -1263,6 +1257,319 @@ - {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, - {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, - + {"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +@@ -1564,7 +1561,318 @@ + {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, + {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, + {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +/* Sony Allegrex CPU core. */ +{"bitrev", "d,t", 0x7c000520, 0xffe007ff, WR_d|RD_t, 0, AL }, +{"mfic", "t,G", 0x70000024, 0xffe007ff, LCD|WR_t|RD_C0, 0, AL }, +{"mtic", "t,G", 0x70000026, 0xffe007ff, COD|RD_t|WR_C0, 0, AL }, -+ + +/* Sony Allegrex VFPU instructions. */ +{"bvf", "?c,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL }, +{"bvfl", "?c,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL }, @@ -565,14 +556,14 @@ +{"vflush", "", 0xffff040d, 0xffffffff, RD_C2, 0, AL }, +{"vsync", "", 0xffff0320, 0xffffffff, RD_C2, 0, AL }, +{"vsync", "i", 0xffff0000, 0xffff0000, RD_C2, 0, AL }, -+ /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format instructions so they are here for the latters to take precedence. */ {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, -@@ -1282,6 +1589,36 @@ - {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, - {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +@@ -1609,6 +1917,38 @@ + {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, + {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, ++ +/* Coprocessor 2 load/store operations overlap with the Allegrex VFPU + instructions so they are here for the latters to take precedence. */ +/* COP1 ldc1 and sdc1 and COP3 ldc3 and sdc3 also overlap with the VFPU. */ @@ -603,6 +594,7 @@ +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, + - /* No hazard protection on coprocessor instructions--they shouldn't - change the state of the processor and if they do it's up to the - user to put in nops as necessary. These are at the end so that the ++ + /* Conflicts with the 4650's "mul" instruction. Nobody's using the + 4010 any more, so move this insn out of the way. If the object + format gave us more info, we could do this right. */ diff --git a/devel/psptoolchain-gdb/files/patch-sim-common-sim-signal.c b/devel/psptoolchain-gdb/files/patch-sim-common-sim-signal.c new file mode 100644 index 000000000000..d67bcfdf0951 --- /dev/null +++ b/devel/psptoolchain-gdb/files/patch-sim-common-sim-signal.c @@ -0,0 +1,11 @@ +--- ./sim/common/sim-signal.c.orig 2011-03-15 03:16:17.000000000 +0000 ++++ ./sim/common/sim-signal.c 2012-01-25 22:24:29.000000000 +0000 +@@ -27,7 +27,7 @@ + to not think the process has died (so it can be debugged at the point of + failure). */ + +-#ifdef _WIN32 ++#if defined(_WIN32) && !defined(__CYGWIN__) + #ifndef SIGTRAP + #define SIGTRAP 5 + #endif diff --git a/devel/psptoolchain-gdb/pkg-plist b/devel/psptoolchain-gdb/pkg-plist index 4afdc9c9f75a..355a33b303fc 100644 --- a/devel/psptoolchain-gdb/pkg-plist +++ b/devel/psptoolchain-gdb/pkg-plist @@ -1,6 +1,25 @@ -lib/libpsp-sim.a -bin/psp-run -bin/psp-gdbtui bin/psp-gdb -@dirrmtry psp/lib -@dirrmtry psp +bin/psp-gdbtui +bin/psp-run +lib/libpsp-sim.a +share/gdb/python/gdb/__init__.py +share/gdb/python/gdb/command/__init__.py +share/gdb/python/gdb/command/pretty_printers.py +share/gdb/python/gdb/printing.py +share/gdb/python/gdb/types.py +share/gdb/syscalls/amd64-linux.xml +share/gdb/syscalls/gdb-syscalls.dtd +share/gdb/syscalls/i386-linux.xml +share/gdb/syscalls/mips-n32-linux.xml +share/gdb/syscalls/mips-n64-linux.xml +share/gdb/syscalls/mips-o32-linux.xml +share/gdb/syscalls/ppc-linux.xml +share/gdb/syscalls/ppc64-linux.xml +share/gdb/syscalls/sparc-linux.xml +share/gdb/syscalls/sparc64-linux.xml +@dirrmtry share/info +@dirrm share/gdb/syscalls +@dirrm share/gdb/python/gdb/command +@dirrm share/gdb/python/gdb +@dirrm share/gdb/python +@dirrm share/gdb |