www/qt5-webengine: fix build on head-aarch64

The interface has changed on -current

PR:		243657
Approved by:	ade (on irc), manu (mentor)

4 files changed, 64 insertions, 39 deletions

diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c
index d30e6549fa81..c7de9b43aafd 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c
@@ -1,6 +1,6 @@
---- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-05-23 12:39:34 UTC
+--- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-10-21 10:14:54 UTC
 +++ src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c
-@@ -14,49 +14,35 @@
+@@ -14,49 +14,47 @@
  
  #include <openssl/cpu.h>
  
@@ -17,12 +17,9 @@
 -
  extern uint32_t OPENSSL_armcap_P;
  
-+#include <sys/types.h>
-+#include <machine/armreg.h>
-+
- void OPENSSL_cpuid_setup(void) {
+-void OPENSSL_cpuid_setup(void) {
 -  unsigned long hwcap = getauxval(AT_HWCAP);
-+  uint64_t id_aa64isar0;
++#include <machine/armreg.h>
  
 -  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
 -  // these values.
@@ -31,30 +28,45 @@
 -  static const unsigned long kPMULL = 1 << 4;
 -  static const unsigned long kSHA1 = 1 << 5;
 -  static const unsigned long kSHA256 = 1 << 6;
-+  id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
++#ifndef ID_AA64ISAR0_AES_VAL
++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
++#endif
++#ifndef ID_AA64ISAR0_AES_VAL
++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
++#endif
++#ifndef ID_AA64ISAR0_SHA1_VAL
++#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1
++#endif
++#ifndef ID_AA64ISAR0_SHA2_VAL
++#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2
++#endif
  
 -  if ((hwcap & kNEON) == 0) {
 -    // Matching OpenSSL, if NEON is missing, don't report other features
 -    // either.
 -    return;
 -  }
--
++void OPENSSL_cpuid_setup(void) {
++  uint64_t id_aa64isar0;
+ 
++  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
++
    OPENSSL_armcap_P |= ARMV7_NEON;
  
 -  if (hwcap & kAES) {
-+  if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_BASE) {
++  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
      OPENSSL_armcap_P |= ARMV8_AES;
    }
 -  if (hwcap & kPMULL) {
-+  if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
++  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
      OPENSSL_armcap_P |= ARMV8_PMULL;
    }
 -  if (hwcap & kSHA1) {
-+  if (ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
++  if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
      OPENSSL_armcap_P |= ARMV8_SHA1;
    }
 -  if (hwcap & kSHA256) {
-+  if(ID_AA64ISAR0_SHA2(id_aa64isar0) == ID_AA64ISAR0_SHA2_BASE) {
++  if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
      OPENSSL_armcap_P |= ARMV8_SHA256;
    }
  }
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h
index 0505f8449959..b638df63770a 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h
@@ -1,20 +1,25 @@
---- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2019-05-23 12:39:34 UTC
+--- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2019-10-21 10:14:54 UTC
 +++ src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h
-@@ -16,6 +16,24 @@
+@@ -16,6 +16,29 @@
  
  #if HAVE_ARM64_CRC32C
  
 +#if defined(__FreeBSD__)
 +#include <machine/armreg.h>
-+#include <sys/types.h>
++#ifndef ID_AA64ISAR0_AES_VAL
++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
++#endif
++#ifndef ID_AA64ISAR0_CRC32_VAL
++#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
++#endif
 +namespace crc32c {
 +
 +inline bool CanUseArm64Linux() {
 +  uint64_t id_aa64isar0;
 +
-+  id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
-+  if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
-+     (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
++  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
++  if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
++     (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
 +    return true;
 +  return false;
 +}
@@ -25,7 +30,7 @@
  #if HAVE_STRONG_GETAUXVAL
  #include <sys/auxv.h>
  #elif HAVE_WEAK_GETAUXVAL
-@@ -43,6 +61,7 @@ inline bool CanUseArm64Linux() {
+@@ -43,6 +66,7 @@ inline bool CanUseArm64Linux() {
  
  }  // namespace crc32c
  
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp
index 20ea3996d3af..0846610268fb 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp
@@ -1,18 +1,21 @@
---- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp.orig	2019-05-23 12:39:34 UTC
+--- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp	2019-10-21 10:14:54 UTC
 +++ src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp
-@@ -70,6 +70,20 @@
+@@ -70,6 +70,23 @@
          return features;
      }
  
 +#elif defined(SK_CPU_ARM64) && defined(__FreeBSD__)
 +    #include <machine/armreg.h>
++    #ifndef ID_AA64ISAR0_CRC32_VAL
++    #define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
++    #endif
 +
 +    static uint32_t read_cpu_features() {
 +        uint32_t features = 0;
 +        uint64_t id_aa64isar0;
 +
-+        id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
-+        if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {
++        id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
++        if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {
 +            features |= SkCpu::CRC32;
 +        }
 +        return features;
@@ -21,8 +24,8 @@
  #elif defined(SK_CPU_ARM64) && __has_include(<sys/auxv.h>)
      #include <sys/auxv.h>
  
-@@ -95,7 +109,12 @@
-         const uint32_t kHWCAP_VFPv4 = (1<<16);
+@@ -78,7 +95,12 @@
+                        kHWCAP_ASIMDHP = (1<<10);
  
          uint32_t features = 0;
 +#if defined(__FreeBSD__)
@@ -31,6 +34,6 @@
 +#else
          uint32_t hwcaps = getauxval(AT_HWCAP);
 +#endif
-         if (hwcaps & kHWCAP_NEON ) {
-             features |= SkCpu::NEON;
-             if (hwcaps & kHWCAP_VFPv4) { features |= SkCpu::NEON_FMA|SkCpu::VFP_FP16; }
+         if (hwcaps & kHWCAP_CRC32  ) { features |= SkCpu::CRC32; }
+         if (hwcaps & kHWCAP_ASIMDHP) { features |= SkCpu::ASIMDHP; }
+         return features;
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c
index ed607e85991c..425c8643032e 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c
@@ -1,6 +1,6 @@
---- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig	2019-05-23 12:39:34 UTC
+--- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig	2019-10-21 10:14:54 UTC
 +++ src/3rdparty/chromium/third_party/zlib/arm_features.c
-@@ -8,83 +8,30 @@
+@@ -8,83 +8,36 @@
  
  #include "zutil.h"
  
@@ -29,9 +29,7 @@
  static void init_arm_features(void)
  {
 -    uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0;
-+#if defined (__aarch64__)
-+    uint64_t id_aa64isar0;
- 
+-
 -#if defined(ARMV8_OS_ANDROID)
 -    flag_crc32 = ANDROID_CPU_ARM_FEATURE_CRC32;
 -    flag_pmull = ANDROID_CPU_ARM_FEATURE_PMULL;
@@ -49,16 +47,23 @@
 -        flag_pmull = HWCAP2_PMULL;
 -        capabilities = getauxval(AT_HWCAP2);
 -    #endif
--#endif
--
++#if defined (__aarch64__)
++#ifndef ID_AA64ISAR0_AES_VAL
++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
+ #endif
++#ifndef ID_AA64ISAR0_CRC32_VAL
++#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
++#endif
++    uint64_t id_aa64isar0;
+ 
 -    if (capabilities & flag_crc32)
 -        arm_cpu_enable_crc32 = 1;
 -
 -    if (capabilities & flag_pmull)
-+    id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
-+    if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
++    id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
++    if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
          arm_cpu_enable_pmull = 1;
-+    if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
++    if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
 +        arm_cpu_enable_crc32 = 1;
 +#endif
  }