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-rw-r--r--cad/iverilog/Makefile8
-rw-r--r--cad/iverilog/distinfo5
2 files changed, 8 insertions, 5 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 59d979997eb0..d3ba518d8539 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,10 +7,11 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.8
+PORTVERSION= 0.8.1
CATEGORIES= cad
-MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/
-DISTNAME= verilog-$(PORTVERSION)
+MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ \
+ ftp://ftp.geda.seul.org/pub/geda/dist/
+DISTNAME= verilog-${PORTVERSION}
MAINTAINER= watchman@ludd.ltu.se
COMMENT= A Verilog simulation and synthesis tool
@@ -18,6 +19,7 @@ COMMENT= A Verilog simulation and synthesis tool
USE_BISON= yes
USE_GMAKE= yes
GNU_CONFIGURE= yes
+CONFIGURE_TARGET= --build=${MACHINE_ARCH}-portbld-freebsd${OSREL}
MAN1= iverilog-vpi.1 iverilog.1 vvp.1 iverilog-fpga.1
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index 9aefb9473f34..36360bdec00c 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1,2 +1,3 @@
-MD5 (verilog-0.8.tar.gz) = 12a20a7f63183e767a9d7d077eb0556c
-SIZE (verilog-0.8.tar.gz) = 1371542
+MD5 (verilog-0.8.1.tar.gz) = 61ab44cbf1734acf1b1e6c4c1ed596b6
+SHA256 (verilog-0.8.1.tar.gz) = 9584d54863bb2399b287251ec17ea435b587abdb20784bcf072024bf4965920d
+SIZE (verilog-0.8.1.tar.gz) = 1431354