diff options
| -rw-r--r-- | cad/Makefile | 1 | ||||
| -rw-r--r-- | cad/chipvault/Makefile | 28 | ||||
| -rw-r--r-- | cad/chipvault/distinfo | 1 | ||||
| -rw-r--r-- | cad/chipvault/pkg-comment | 1 | ||||
| -rw-r--r-- | cad/chipvault/pkg-descr | 14 | ||||
| -rw-r--r-- | cad/chipvault/pkg-plist | 1 |
6 files changed, 46 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile index e3ad100d5bd9..2ecb0ebac91c 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -4,6 +4,7 @@ SUBDIR += atlc SUBDIR += cascade SUBDIR += chipmunk + SUBDIR += chipvault SUBDIR += cider SUBDIR += electric SUBDIR += felt diff --git a/cad/chipvault/Makefile b/cad/chipvault/Makefile new file mode 100644 index 000000000000..e8bb7568752b --- /dev/null +++ b/cad/chipvault/Makefile @@ -0,0 +1,28 @@ +# ex:ts=8 +# Ports collection makefile for: chipvault +# Date created: Jan 29, 2003 +# Whom: ijliao +# +# $FreeBSD$ +# + +PORTNAME= chipvault +PORTVERSION= 200211 +CATEGORIES= cad +MASTER_SITES= http://chipvault.sourceforge.net/ +DISTNAME= cv.pl +EXTRACT_SUFX= .gz + +MAINTAINER= ports@FreeBSD.org + +NO_WRKSUBDIR= yes +EXTRACT_CMD= ${GZCAT} +EXTRACT_BEFORE_ARGS= # empty +EXTRACT_AFTER_ARGS= > ${DISTNAME} +NO_BUILD= yes +USE_PERL5_RUN= yes + +do-install: + ${INSTALL_SCRIPT} ${WRKSRC}/cv.pl ${PREFIX}/bin/cv + +.include <bsd.port.mk> diff --git a/cad/chipvault/distinfo b/cad/chipvault/distinfo new file mode 100644 index 000000000000..0339c276d6a1 --- /dev/null +++ b/cad/chipvault/distinfo @@ -0,0 +1 @@ +MD5 (cv.pl.gz) = 1b740c4eb63f8e23b233c429f60b56e7 diff --git a/cad/chipvault/pkg-comment b/cad/chipvault/pkg-comment new file mode 100644 index 000000000000..10d964f45ff1 --- /dev/null +++ b/cad/chipvault/pkg-comment @@ -0,0 +1 @@ +A project organizer for VHDL and Verilog RTL hardware designs diff --git a/cad/chipvault/pkg-descr b/cad/chipvault/pkg-descr new file mode 100644 index 000000000000..2d2406e9cacc --- /dev/null +++ b/cad/chipvault/pkg-descr @@ -0,0 +1,14 @@ +ChipVault is a VHDL and Verilog Chip Design Organization tool which improves +design efficiency by: + - Providing the ability to Navigate and Edit files Hierarchically. + - Automatically generating Schematic Component Port views of VHDL and + Verilog RTL files. + - Automating RTL instantiation and template generation. + - Providing Revision Control (designed for HW, not SW development). + - Supporting External Tool Hooks (bottom-up vcoms,etc). + - Providing an Issue Tracking Log with sorting. + - Providing Netlist sorting and hierarchy viewing. + - Supporting web-sharing of RTL files (both encrypted and clear). + - Fast and Nimble. + +WWW: http://chipvault.sourceforge.net/ diff --git a/cad/chipvault/pkg-plist b/cad/chipvault/pkg-plist new file mode 100644 index 000000000000..7a9e77960981 --- /dev/null +++ b/cad/chipvault/pkg-plist @@ -0,0 +1 @@ +bin/cv |