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-rw-r--r--cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL8
1 files changed, 4 insertions, 4 deletions
diff --git a/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL b/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
index 747ba533da79..083af1c04638 100644
--- a/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
+++ b/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
@@ -1,6 +1,6 @@
---- Preproc/Makefile.PL 2014-03-11 19:59:40.000000000 -0300
-+++ Preproc/Makefile.PL 2014-06-25 11:19:37.000000000 -0300
-@@ -9,13 +9,14 @@
+--- Preproc/Makefile.PL.orig 2016-02-02 23:36:13 UTC
++++ Preproc/Makefile.PL
+@@ -9,13 +9,14 @@ use Config;
sub MY::postamble {
my $out;
@@ -16,7 +16,7 @@
}
# Note OPTIMIZE is passed from upper makefile, so this code needed there too.
my $optimize = $Config{optimize}; $optimize =~ s/(^| )-O2( |$)/\1-O\2/g;
-@@ -46,7 +47,7 @@
+@@ -50,7 +51,7 @@ sub MY::postamble {
$out .= "${cmt}CFLAGS += -DFLEX_DEBUG\n";
$out .= "${cmt}LEXFLAGS += -d\n";
$out .= '