diff options
Diffstat (limited to 'devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08')
| -rw-r--r-- | devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 | 6335 |
1 files changed, 6335 insertions, 0 deletions
diff --git a/devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 b/devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 new file mode 100644 index 000000000000..24b967361775 --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 @@ -0,0 +1,6335 @@ +diff -ruN linux/include/asm-mips/addrspace.h linux-mips/include/asm-mips/addrspace.h +--- linux/include/asm-mips/addrspace.h Thu Jun 26 12:33:39 1997 ++++ linux-mips/include/asm-mips/addrspace.h Mon Sep 11 23:53:12 2000 +@@ -4,6 +4,7 @@ + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle ++ * Copyright (C) 2000 by Maciej W. Rozycki + * + * Defitions for the address spaces of the MIPS CPUs. + */ +@@ -22,20 +23,35 @@ + /* + * Returns the kernel segment base of a given address + */ ++#ifndef __ASSEMBLY__ + #define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) ++#else ++#define KSEGX(a) ((a) & 0xe0000000) ++#endif + + /* + * Returns the physical address of a KSEG0/KSEG1 address + */ ++#ifndef __ASSEMBLY__ + #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) ++#else ++#define PHYSADDR(a) ((a) & 0x1fffffff) ++#endif + + /* + * Map an address to a certain kernel segment + */ ++#ifndef __ASSEMBLY__ + #define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) + #define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) + #define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) + #define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) ++#else ++#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) ++#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) ++#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) ++#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) ++#endif + + /* + * Memory segments (64bit kernel mode addresses) +diff -ruN linux/include/asm-mips/atomic.h linux-mips/include/asm-mips/atomic.h +--- linux/include/asm-mips/atomic.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/atomic.h Fri Nov 10 00:11:39 2000 +@@ -9,20 +9,14 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1996, 1997 by Ralf Baechle +- * +- * $Id: atomic.h,v 1.6 1999/07/26 19:42:42 harald Exp $ ++ * Copyright (C) 1996, 1997, 2000 by Ralf Baechle + */ + #ifndef __ASM_ATOMIC_H + #define __ASM_ATOMIC_H + + #include <linux/config.h> + +-#ifdef CONFIG_SMP + typedef struct { volatile int counter; } atomic_t; +-#else +-typedef struct { int counter; } atomic_t; +-#endif + + #ifdef __KERNEL__ + #define ATOMIC_INIT(i) { (i) } +@@ -38,7 +32,7 @@ + * The MIPS I implementation is only atomic with respect to + * interrupts. R3000 based multiprocessor machines are rare anyway ... + */ +-extern __inline__ void atomic_add(int i, volatile atomic_t * v) ++extern __inline__ void atomic_add(int i, atomic_t * v) + { + int flags; + +@@ -48,7 +42,7 @@ + restore_flags(flags); + } + +-extern __inline__ void atomic_sub(int i, volatile atomic_t * v) ++extern __inline__ void atomic_sub(int i, atomic_t * v) + { + int flags; + +@@ -86,21 +80,6 @@ + return temp; + } + +-extern __inline__ void atomic_clear_mask(unsigned long mask, unsigned long * v) +-{ +- unsigned long temp; +- int flags; +- +- save_flags(flags); +- cli(); +- temp = *v; +- temp &= ~mask; +- *v = temp; +- restore_flags(flags); +- +- return; +-} +- + #else + + /* +@@ -108,41 +87,30 @@ + * implementation is SMP safe ... + */ + +-/* +- * Make sure gcc doesn't try to be clever and move things around +- * on us. We need to use _exactly_ the address the user gave us, +- * not some alias that contains the same information. +- */ +-#define __atomic_fool_gcc(x) (*(volatile struct { int a[100]; } *)x) +- +-extern __inline__ void atomic_add(int i, volatile atomic_t * v) ++extern __inline__ void atomic_add(int i, atomic_t * v) + { + unsigned long temp; + + __asm__ __volatile__( +- "1:\tll\t%0,%1\n\t" +- "addu\t%0,%2\n\t" +- "sc\t%0,%1\n\t" +- "beqz\t%0,1b" +- :"=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ "1:\tll\t%0, %1\t\t\t# atomic_add\n\t" ++ "addu\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter)); + } + +-extern __inline__ void atomic_sub(int i, volatile atomic_t * v) ++extern __inline__ void atomic_sub(int i, atomic_t * v) + { + unsigned long temp; + + __asm__ __volatile__( +- "1:\tll\t%0,%1\n\t" +- "subu\t%0,%2\n\t" +- "sc\t%0,%1\n\t" +- "beqz\t%0,1b" +- :"=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ "1:\tll\t%0, %1\t\t\t# atomic_sub\n\t" ++ "subu\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter)); + } + + /* +@@ -153,18 +121,16 @@ + unsigned long temp, result; + + __asm__ __volatile__( +- ".set\tnoreorder\n" ++ ".set\tnoreorder\t\t\t# atomic_add_return\n" + "1:\tll\t%1,%2\n\t" + "addu\t%0,%1,%3\n\t" + "sc\t%0,%2\n\t" + "beqz\t%0,1b\n\t" + "addu\t%0,%1,%3\n\t" + ".set\treorder" +- :"=&r" (result), +- "=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ : "=&r" (result), "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter) ++ : "memory"); + + return result; + } +@@ -174,18 +140,16 @@ + unsigned long temp, result; + + __asm__ __volatile__( +- ".set\tnoreorder\n" ++ ".set\tnoreorder\t\t\t# atomic_sub_return\n" + "1:\tll\t%1,%2\n\t" + "subu\t%0,%1,%3\n\t" + "sc\t%0,%2\n\t" + "beqz\t%0,1b\n\t" + "subu\t%0,%1,%3\n\t" + ".set\treorder" +- :"=&r" (result), +- "=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ : "=&r" (result), "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter) ++ : "memory"); + + return result; + } +@@ -201,4 +165,4 @@ + #define atomic_dec(v) atomic_sub(1,(v)) + #endif /* defined(__KERNEL__) */ + +-#endif /* __ASM_MIPS_ATOMIC_H */ ++#endif /* __ASM_ATOMIC_H */ +diff -ruN linux/include/asm-mips/bcache.h linux-mips/include/asm-mips/bcache.h +--- linux/include/asm-mips/bcache.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/bcache.h Fri Nov 10 00:11:39 2000 +@@ -1,14 +1,19 @@ +-/* $Id$ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (c) 1997, 1999 by Ralf Baechle ++ * Copyright (c) 1997, 1999, 2000 by Ralf Baechle ++ * Copyright (c) 2000 by Silicon Graphics, Inc. + */ + #ifndef _ASM_BCACHE_H + #define _ASM_BCACHE_H + ++#include <linux/config.h> ++ ++/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, ++ chipset implemented caches. On machines with other CPUs the CPU does the ++ cache thing itself. */ + struct bcache_ops { + void (*bc_enable)(void); + void (*bc_disable)(void); +@@ -19,6 +24,39 @@ + extern void indy_sc_init(void); + extern void sni_pcimt_sc_init(void); + ++#ifdef CONFIG_BOARD_SCACHE ++ + extern struct bcache_ops *bcops; ++ ++extern inline void bc_enable(void) ++{ ++ bcops->bc_enable(); ++} ++ ++extern inline void bc_disable(void) ++{ ++ bcops->bc_disable(); ++} ++ ++extern inline void bc_wback_inv(unsigned long page, unsigned long size) ++{ ++ bcops->bc_wback_inv(page, size); ++} ++ ++extern inline void bc_inv(unsigned long page, unsigned long size) ++{ ++ bcops->bc_inv(page, size); ++} ++ ++#else /* !defined(CONFIG_BOARD_SCACHE) */ ++ ++/* Not R4000 / R4400 / R4600 / R5000. */ ++ ++#define bc_enable() do { } while (0) ++#define bc_disable() do { } while (0) ++#define bc_wback_inv(page, size) do { } while (0) ++#define bc_inv(page, size) do { } while (0) ++ ++#endif /* !defined(CONFIG_BOARD_SCACHE) */ + + #endif /* _ASM_BCACHE_H */ +diff -ruN linux/include/asm-mips/bitops.h linux-mips/include/asm-mips/bitops.h +--- linux/include/asm-mips/bitops.h Wed Jul 5 22:15:26 2000 ++++ linux-mips/include/asm-mips/bitops.h Fri Nov 10 00:11:41 2000 +@@ -1,10 +1,10 @@ +-/* $Id: bitops.h,v 1.7 1999/08/19 22:56:33 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (c) 1994 - 1997, 1999 Ralf Baechle (ralf@gnu.org) ++ * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) ++ * Copyright (c) 2000 Silicon Graphics, Inc. + */ + #ifndef _ASM_BITOPS_H + #define _ASM_BITOPS_H +@@ -19,6 +19,12 @@ + #include <linux/config.h> + + /* ++ * clear_bit() doesn't provide any barrier for the compiler. ++ */ ++#define smp_mb__before_clear_bit() barrier() ++#define smp_mb__after_clear_bit() barrier() ++ ++/* + * Only disable interrupt for kernel mode stuff to keep usermode stuff + * that dares to use kernel include files alive. + */ +@@ -35,25 +41,6 @@ + #define __bi_restore_flags(x) + #endif /* __KERNEL__ */ + +-/* +- * Note that the bit operations are defined on arrays of 32 bit sized +- * elements. With respect to a future 64 bit implementation it is +- * wrong to use long *. Use u32 * or int *. +- */ +-extern __inline__ void set_bit(int nr, void *addr); +-extern __inline__ void clear_bit(int nr, void *addr); +-extern __inline__ void change_bit(int nr, void *addr); +-extern __inline__ int test_and_set_bit(int nr, void *addr); +-extern __inline__ int test_and_clear_bit(int nr, void *addr); +-extern __inline__ int test_and_change_bit(int nr, void *addr); +- +-extern __inline__ int test_bit(int nr, const void *addr); +-#ifndef __MIPSEB__ +-extern __inline__ int find_first_zero_bit (void *addr, unsigned size); +-#endif +-extern __inline__ int find_next_zero_bit (void * addr, int size, int offset); +-extern __inline__ unsigned long ffz(unsigned long word); +- + #if defined(CONFIG_CPU_HAS_LLSC) + + #include <asm/mipsregs.h> +@@ -63,93 +50,162 @@ + * interrupt friendly + */ + +-/* +- * The following functions will only work for the R4000! +- */ ++extern __inline__ void ++set_bit(int nr, volatile void *addr) ++{ ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp; + +-extern __inline__ void set_bit(int nr, void *addr) ++ __asm__ __volatile__( ++ "1:\tll\t%0, %1\t\t# set_bit\n\t" ++ "or\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (*m) ++ : "ir" (1UL << (nr & 0x1f)), "m" (*m)); ++} ++ ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ void __set_bit(int nr, volatile void * addr) + { +- int mask, mw; ++ unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- } while (!store_conditional(addr, mw|mask)); ++ *m |= 1UL << (nr & 31); + } + +-extern __inline__ void clear_bit(int nr, void *addr) ++extern __inline__ void ++clear_bit(int nr, volatile void *addr) + { +- int mask, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp; + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- } +- while (!store_conditional(addr, mw & ~mask)); ++ __asm__ __volatile__( ++ "1:\tll\t%0, %1\t\t# clear_bit\n\t" ++ "and\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b\n\t" ++ : "=&r" (temp), "=m" (*m) ++ : "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); + } + +-extern __inline__ void change_bit(int nr, void *addr) ++extern __inline__ void ++change_bit(int nr, volatile void *addr) + { +- int mask, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp; + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- } while (!store_conditional(addr, mw ^ mask)); ++ __asm__ __volatile__( ++ "1:\tll\t%0, %1\t\t# change_bit\n\t" ++ "xor\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (*m) ++ : "ir" (1UL << (nr & 0x1f)), "m" (*m)); + } + +-extern __inline__ int test_and_set_bit(int nr, void *addr) ++/* ++ * It will also imply a memory barrier, thus it must clobber memory ++ * to make sure to reload anything that was cached into registers ++ * outside _this_ critical section. ++ */ ++extern __inline__ int ++test_and_set_bit(int nr, volatile void *addr) + { +- int mask, retval, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp, res; + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- retval = (mask & mw) != 0; +- } while (!store_conditional(addr, mw|mask)); ++ __asm__ __volatile__( ++ ".set\tnoreorder\t\t# test_and_set_bit\n" ++ "1:\tll\t%0, %1\n\t" ++ "or\t%2, %0, %3\n\t" ++ "sc\t%2, %1\n\t" ++ "beqz\t%2, 1b\n\t" ++ " and\t%2, %0, %3\n\t" ++ ".set\treorder" ++ : "=&r" (temp), "=m" (*m), "=&r" (res) ++ : "r" (1UL << (nr & 0x1f)), "m" (*m) ++ : "memory"); + +- return retval; ++ return res != 0; + } + +-extern __inline__ int test_and_clear_bit(int nr, void *addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) + { +- int mask, retval, mw; ++ int mask, retval; ++ volatile int *a = addr; + +- addr += ((nr >> 3) & ~3); ++ a += nr >> 5; + mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- retval = (mask & mw) != 0; +- } +- while (!store_conditional(addr, mw & ~mask)); ++ retval = (mask & *a) != 0; ++ *a |= mask; + + return retval; + } + +-extern __inline__ int test_and_change_bit(int nr, void *addr) ++extern __inline__ int ++test_and_clear_bit(int nr, volatile void *addr) + { +- int mask, retval, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp, res; ++ ++ __asm__ __volatile__( ++ ".set\tnoreorder\t\t# test_and_clear_bit\n" ++ "1:\tll\t%0, %1\n\t" ++ "or\t%2, %0, %3\n\t" ++ "xor\t%2, %3\n\t" ++ "sc\t%2, %1\n\t" ++ "beqz\t%2, 1b\n\t" ++ " and\t%2, %0, %3\n\t" ++ ".set\treorder" ++ : "=&r" (temp), "=m" (*m), "=&r" (res) ++ : "r" (1UL << (nr & 0x1f)), "m" (*m) ++ : "memory"); + +- addr += ((nr >> 3) & ~3); ++ return res != 0; ++} ++ ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) ++{ ++ int mask, retval; ++ volatile int *a = addr; ++ ++ a += nr >> 5; + mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- retval = (mask & mw) != 0; +- } while (!store_conditional(addr, mw ^ mask)); ++ retval = (mask & *a) != 0; ++ *a &= ~mask; + + return retval; + } + ++extern __inline__ int ++test_and_change_bit(int nr, volatile void *addr) ++{ ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp, res; ++ ++ __asm__ __volatile__( ++ ".set\tnoreorder\t\t# test_and_change_bit\n" ++ "1:\tll\t%0, %1\n\t" ++ "xor\t%2, %0, %3\n\t" ++ "sc\t%2, %1\n\t" ++ "beqz\t%2, 1b\n\t" ++ " and\t%2, %0, %3\n\t" ++ ".set\treorder" ++ : "=&r" (temp), "=m" (*m), "=&r" (res) ++ : "r" (1UL << (nr & 0x1f)), "m" (*m) ++ : "memory"); ++ ++ return res != 0; ++} ++ + #else /* MIPS I */ + +-extern __inline__ void set_bit(int nr, void * addr) ++extern __inline__ void set_bit(int nr, volatile void * addr) + { + int mask; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -159,10 +215,22 @@ + __bi_restore_flags(flags); + } + +-extern __inline__ void clear_bit(int nr, void * addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ void __set_bit(int nr, volatile void * addr) ++{ ++ int mask; ++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ *a |= mask; ++} ++ ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ void clear_bit(int nr, volatile void * addr) + { + int mask; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -172,10 +240,10 @@ + __bi_restore_flags(flags); + } + +-extern __inline__ void change_bit(int nr, void * addr) ++extern __inline__ void change_bit(int nr, volatile void * addr) + { + int mask; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -185,10 +253,10 @@ + __bi_restore_flags(flags); + } + +-extern __inline__ int test_and_set_bit(int nr, void * addr) ++extern __inline__ int test_and_set_bit(int nr, volatile void * addr) + { + int mask, retval; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -201,10 +269,24 @@ + return retval; + } + +-extern __inline__ int test_and_clear_bit(int nr, void * addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) + { + int mask, retval; +- int *a = addr; ++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ retval = (mask & *a) != 0; ++ *a |= mask; ++ ++ return retval; ++} ++ ++extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) ++{ ++ int mask, retval; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -217,10 +299,24 @@ + return retval; + } + +-extern __inline__ int test_and_change_bit(int nr, void * addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) ++{ ++ int mask, retval; ++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ retval = (mask & *a) != 0; ++ *a &= ~mask; ++ ++ return retval; ++} ++ ++extern __inline__ int test_and_change_bit(int nr, volatile void * addr) + { + int mask, retval; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -234,13 +330,13 @@ + } + + #undef __bi_flags +-#undef __bi_cli() +-#undef __bi_save_flags(x) +-#undef __bi_restore_flags(x) ++#undef __bi_cli ++#undef __bi_save_flags ++#undef __bi_restore_flags + + #endif /* MIPS I */ + +-extern __inline__ int test_bit(int nr, const void *addr) ++extern __inline__ int test_bit(int nr, volatile void *addr) + { + return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; + } +@@ -285,13 +381,9 @@ + ".set\tat\n\t" + ".set\treorder\n" + "2:" +- : "=r" (res), +- "=r" (dummy), +- "=r" (addr) +- : "0" ((signed int) 0), +- "1" ((unsigned int) 0xffffffff), +- "2" (addr), +- "r" (size) ++ : "=r" (res), "=r" (dummy), "=r" (addr) ++ : "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff), ++ "2" (addr), "r" (size) + : "$1"); + + return res; +@@ -320,11 +412,8 @@ + ".set\tat\n\t" + ".set\treorder\n" + "1:" +- : "=r" (set), +- "=r" (dummy) +- : "0" (0), +- "1" (1 << bit), +- "r" (*p) ++ : "=r" (set), "=r" (dummy) ++ : "0" (0), "1" (1 << bit), "r" (*p) + : "$1"); + if (set < (32 - bit)) + return set + offset; +diff -ruN linux/include/asm-mips/bootinfo.h linux-mips/include/asm-mips/bootinfo.h +--- linux/include/asm-mips/bootinfo.h Tue Jul 11 11:15:02 2000 ++++ linux-mips/include/asm-mips/bootinfo.h Fri Nov 10 00:11:41 2000 +@@ -1,16 +1,13 @@ +-/* $Id: bootinfo.h,v 1.11 2000/03/06 11:14:32 raiko Exp $ +- * +- * bootinfo.h -- Definition of the Linux/MIPS boot information structure +- * +- * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, +- * Stoned Elipot and Paul M. Antoine. +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. ++ * ++ * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, ++ * Stoned Elipot and Paul M. Antoine. + */ +-#ifndef __ASM_MIPS_BOOTINFO_H +-#define __ASM_MIPS_BOOTINFO_H ++#ifndef _ASM_BOOTINFO_H ++#define _ASM_BOOTINFO_H + + /* + * Values for machgroup +@@ -26,9 +23,10 @@ + #define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ + #define MACH_GROUP_BAGET 9 /* Baget */ + #define MACH_GROUP_ORION 10 /* CoSine Orion */ ++#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards*/ + + #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \ +- "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion" } ++ "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" } + + /* + * Valid machtype values for group unknown (low order halfword of mips_machtype) +@@ -105,8 +103,9 @@ + * Valid machtype for group NEC DDB + */ + #define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ ++#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ + +-#define GROUP_NEC_DDB_NAMES { "Vrc-5074" } ++#define GROUP_NEC_DDB_NAMES { "Vrc-5074", "Vrc-5476"} + + /* + * Valid machtype for group BAGET +@@ -117,6 +116,13 @@ + #define GROUP_BAGET_NAMES { "BT23-201", "BT23-202" } + + /* ++ * Valid machtype for group GALILEO ++ */ ++#define MACH_EV96100 0 /* EV96100 */ ++ ++#define GROUP_GALILEO_NAMES { "EV96100" } ++ ++/* + * Valid cputype values + */ + #define CPU_UNKNOWN 0 +@@ -147,13 +153,15 @@ + #define CPU_R5000A 25 + #define CPU_R4640 26 + #define CPU_NEVADA 27 /* RM5230, RM5260 */ +-#define CPU_LAST 27 ++#define CPU_RM7000 28 ++#define CPU_R5432 29 ++#define CPU_LAST 29 + + #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \ + "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \ + "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \ + "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \ +- "R5000A", "R4640", "Nevada" } ++ "R5000A", "R4640", "Nevada", "RM7000", "R5432" } + + #define CL_SIZE (80) + +@@ -193,4 +201,4 @@ + + #endif /* _LANGUAGE_ASSEMBLY */ + +-#endif /* __ASM_MIPS_BOOTINFO_H */ ++#endif /* _ASM_BOOTINFO_H */ +diff -ruN linux/include/asm-mips/bugs.h linux-mips/include/asm-mips/bugs.h +--- linux/include/asm-mips/bugs.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/bugs.h Mon Sep 11 23:53:13 2000 +@@ -30,6 +30,7 @@ + case CPU_R4700: + case CPU_R5000: + case CPU_NEVADA: ++ case CPU_RM7000: + cpu_wait = r4k_wait; + printk(" available.\n"); + break; +diff -ruN linux/include/asm-mips/cpu.h linux-mips/include/asm-mips/cpu.h +--- linux/include/asm-mips/cpu.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/cpu.h Fri Nov 10 00:11:41 2000 +@@ -25,6 +25,7 @@ + #define PRID_IMP_R4640 0x2200 + #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ + #define PRID_IMP_R5000 0x2300 ++#define PRID_IMP_R5432 0x5400 + #define PRID_IMP_SONIC 0x2400 + #define PRID_IMP_MAGIC 0x2500 + #define PRID_IMP_RM7000 0x2700 +diff -ruN linux/include/asm-mips/dec/interrupts.h linux-mips/include/asm-mips/dec/interrupts.h +--- linux/include/asm-mips/dec/interrupts.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/interrupts.h Mon Sep 11 23:53:17 2000 +@@ -36,7 +36,7 @@ + + #define NR_INTS 11 + +-#ifndef _LANGUAGE_ASSEMBLY ++#ifndef __ASSEMBLY__ + /* + * Data structure to hide the differences between the DECstation Interrupts + * +@@ -50,6 +50,12 @@ + unsigned int iemask; /* enabling interrupts in IRQ Controller */ + } decint_t; + ++extern volatile unsigned int *isr; ++ /* address of the interrupt status register */ ++extern volatile unsigned int *imr; ++ /* address of the interrupt mask register */ ++extern decint_t dec_interrupt[NR_INTS]; ++ + /* + * Interrupt table structure to hide differences between different + * systems such. +@@ -68,7 +74,7 @@ + extern void dec_intr_rtc(void); + + extern void kn02_io_int(void); +-extern void kn02ba_io_int(void); ++extern void kn02xa_io_int(void); + extern void kn03_io_int(void); + + extern void intr_halt(void); +diff -ruN linux/include/asm-mips/dec/ioasic.h linux-mips/include/asm-mips/dec/ioasic.h +--- linux/include/asm-mips/dec/ioasic.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/dec/ioasic.h Mon Sep 11 23:53:17 2000 +@@ -0,0 +1,24 @@ ++/* ++ * linux/asm-mips/dec/ioasic.h ++ * ++ * Copyright (C) 2000 Maciej W. Rozycki ++ * ++ * DEC I/O ASIC access operations. ++ */ ++ ++#ifndef __ASM_DEC_IOASIC_H ++#define __ASM_DEC_IOASIC_H ++ ++extern volatile unsigned int *ioasic_base; ++ ++extern inline void ioasic_write(unsigned int reg, unsigned int v) ++{ ++ ioasic_base[reg / 4] = v; ++} ++ ++extern inline unsigned int ioasic_read(unsigned int reg) ++{ ++ return ioasic_base[reg / 4]; ++} ++ ++#endif /* __ASM_DEC_IOASIC_H */ +diff -ruN linux/include/asm-mips/dec/ioasic_addrs.h linux-mips/include/asm-mips/dec/ioasic_addrs.h +--- linux/include/asm-mips/dec/ioasic_addrs.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/ioasic_addrs.h Mon Sep 11 23:53:17 2000 +@@ -17,25 +17,25 @@ + + #define CHUNK_SIZE 0x00040000 + +-#define SYSTEM_ROM 00*CHUNK_SIZE /* ??? */ +-#define IOCTL 01*CHUNK_SIZE +-#define ESAR 02*CHUNK_SIZE +-#define LANCE 03*CHUNK_SIZE +-#define SCC0 04*CHUNK_SIZE +-#define VDAC_HI 05*CHUNK_SIZE /* maxine only */ +-#define SCC1 06*CHUNK_SIZE +-#define VDAC_LO 07*CHUNK_SIZE /* maxine only */ +-#define TOY 08*CHUNK_SIZE +-#define ISDN 09*CHUNK_SIZE /* maxine only */ +-#define ERRADDR 09*CHUNK_SIZE /* 3maxplus only */ +-#define CHKSYN 10*CHUNK_SIZE /* 3maxplus only */ +-#define ACCESS_BUS 10*CHUNK_SIZE /* maxine only */ +-#define MCR 11*CHUNK_SIZE /* 3maxplus only */ +-#define FLOPPY 11*CHUNK_SIZE /* maxine only */ +-#define SCSI 12*CHUNK_SIZE +-#define FLOPPY_DMA 13*CHUNK_SIZE /* maxine only */ +-#define SCSI_DMA 14*CHUNK_SIZE +-#define RESERVED_4 15*CHUNK_SIZE ++#define SYSTEM_ROM (00*CHUNK_SIZE) /* ??? */ ++#define IOCTL (01*CHUNK_SIZE) ++#define ESAR (02*CHUNK_SIZE) ++#define LANCE (03*CHUNK_SIZE) ++#define SCC0 (04*CHUNK_SIZE) ++#define VDAC_HI (05*CHUNK_SIZE) /* maxine only */ ++#define SCC1 (06*CHUNK_SIZE) ++#define VDAC_LO (07*CHUNK_SIZE) /* maxine only */ ++#define TOY (08*CHUNK_SIZE) ++#define ISDN (09*CHUNK_SIZE) /* maxine only */ ++#define ERRADDR (09*CHUNK_SIZE) /* 3maxplus only */ ++#define CHKSYN (10*CHUNK_SIZE) /* 3maxplus only */ ++#define ACCESS_BUS (10*CHUNK_SIZE) /* maxine only */ ++#define MCR (11*CHUNK_SIZE) /* 3maxplus only */ ++#define FLOPPY (11*CHUNK_SIZE) /* maxine only */ ++#define SCSI (12*CHUNK_SIZE) ++#define FLOPPY_DMA (13*CHUNK_SIZE) /* maxine only */ ++#define SCSI_DMA (14*CHUNK_SIZE) ++#define RESERVED_4 (15*CHUNK_SIZE) + + /* + * Offsets for IOCTL registers (relative to (system_base + IOCTL)) +@@ -56,6 +56,7 @@ + #define SSR 0x100 /* System Support Register */ + #define SIR 0x110 /* System Interrupt Register */ + #define SIMR 0x120 /* System Interrupt Mask Register */ ++#define FCTR 0x1e0 /* Free-Running Counter */ + + /* + * Handle partial word SCSI DMA transfers +diff -ruN linux/include/asm-mips/dec/kn02xa.h linux-mips/include/asm-mips/dec/kn02xa.h +--- linux/include/asm-mips/dec/kn02xa.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/kn02xa.h Fri Nov 10 00:12:14 2000 +@@ -9,6 +9,7 @@ + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. ++ * Copyright (C) 2000 Maciej W. Rozycki + * + * These are addresses which have to be known early in the boot process. + * For other addresses refer to tc.h ioasic_addrs.h and friends. +@@ -19,16 +20,12 @@ + #include <asm/addrspace.h> + + /* +- * Motherboard regs (kseg1 addresses) +- */ +-#define KN02XA_SSR_ADDR KSEG1ADDR(0x1c040100) /* system control & status reg */ +-#define KN02XA_SIR_ADDR KSEG1ADDR(0x1c040110) /* system interrupt reg */ +-#define KN02XA_SIRM_ADDR KSEG1ADDR(0x1c040120) /* system interrupt mask reg */ +- +-/* + * Some port addresses... + * FIXME: these addresses are incomplete and need tidying up! + */ +-#define KN02XA_RTC_BASE (KSEG1ADDR(0x1c000000 + 0x200000)) /* ASIC + SL8 */ ++#define KN02XA_IOASIC_BASE KSEG1ADDR(0x1c040000) /* I/O ASIC */ ++#define KN02XA_RTC_BASE KSEG1ADDR(0x1c200000) /* RTC */ ++ ++#define KN02XA_IOASIC_REG(r) (KN02XA_IOASIC_BASE+(r)) + + #endif /* __ASM_MIPS_DEC_KN02XA_H */ +diff -ruN linux/include/asm-mips/dec/kn03.h linux-mips/include/asm-mips/dec/kn03.h +--- linux/include/asm-mips/dec/kn03.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/kn03.h Mon Sep 11 23:53:17 2000 +@@ -8,6 +8,7 @@ + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. ++ * Copyright (C) 2000 Maciej W. Rozycki + * + * These are addresses which have to be known early in the boot process. + * For other addresses refer to tc.h ioasic_addrs.h and friends. +@@ -18,16 +19,12 @@ + #include <asm/addrspace.h> + + /* +- * Motherboard regs (kseg1 addresses) +- */ +-#define KN03_SSR_ADDR KSEG1ADDR(0x1f840100) /* system control & status reg */ +-#define KN03_SIR_ADDR KSEG1ADDR(0x1f840110) /* system interrupt reg */ +-#define KN03_SIRM_ADDR KSEG1ADDR(0x1f840120) /* system interrupt mask reg */ +- +-/* + * Some port addresses... + * FIXME: these addresses are incomplete and need tidying up! + */ +-#define KN03_RTC_BASE (KSEG1ADDR(0x1f800000 + 0x200000)) /* ASIC + SL8 */ ++#define KN03_IOASIC_BASE KSEG1ADDR(0x1f840000) /* I/O ASIC */ ++#define KN03_RTC_BASE KSEG1ADDR(0x1fa00000) /* RTC */ ++ ++#define KN03_IOASIC_REG(r) (KN03_IOASIC_BASE+(r)) + + #endif /* __ASM_MIPS_DEC_KN03_H */ +diff -ruN linux/include/asm-mips/div64.h linux-mips/include/asm-mips/div64.h +--- linux/include/asm-mips/div64.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/div64.h Mon Sep 11 23:53:13 2000 +@@ -1,4 +1,7 @@ +-/* $Id: div64.h,v 1.1 2000/01/28 23:18:43 ralf Exp $ ++/* ++ * include/asm-mips/div64.h ++ * ++ * Copyright (C) 2000 Maciej W. Rozycki + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive +@@ -7,14 +10,104 @@ + #ifndef _ASM_DIV64_H + #define _ASM_DIV64_H + ++#include <asm/sgidefs.h> ++ + /* +- * Hey, we're already 64-bit, no +- * need to play games.. ++ * No traps on overflows for any of these... + */ +-#define do_div(n,base) ({ \ +- int __res; \ +- __res = ((unsigned long) n) % (unsigned) base; \ +- n = ((unsigned long) n) / (unsigned) base; \ +- __res; }) ++ ++#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) ++ ++#define do_div64_32(res, high, low, base) ({ \ ++ unsigned long __quot, __mod; \ ++ unsigned long __cf, __tmp, __i; \ ++ \ ++ __asm__(".set push\n\t" \ ++ ".set noat\n\t" \ ++ ".set noreorder\n\t" \ ++ "b 1f\n\t" \ ++ " li %4,0x21\n" \ ++ "0:\n\t" \ ++ "sll $1,%0,0x1\n\t" \ ++ "srl %3,%0,0x1f\n\t" \ ++ "or %0,$1,$2\n\t" \ ++ "sll %1,%1,0x1\n\t" \ ++ "sll %2,%2,0x1\n" \ ++ "1:\n\t" \ ++ "bnez %3,2f\n\t" \ ++ "sltu $2,%0,%z5\n\t" \ ++ "bnez $2,3f\n\t" \ ++ "2:\n\t" \ ++ " addiu %4,%4,-1\n\t" \ ++ "subu %0,%0,%z5\n\t" \ ++ "addiu %2,%2,1\n" \ ++ "3:\n\t" \ ++ "bnez %4,0b\n\t" \ ++ " srl $2,%1,0x1f\n\t" \ ++ ".set pop" \ ++ : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ ++ "=&r" (__i) \ ++ : "Jr" (base), "0" (high), "1" (low), "2" (0), "3" (0) \ ++ /* Aarrgh! Ran out of gcc's limit on constraints... */ \ ++ : "$1", "$2"); \ ++ \ ++ (res) = __quot; \ ++ __mod; }) ++ ++#define do_div(n, base) ({ \ ++ unsigned long long __quot; \ ++ unsigned long __upper, __low, __high, __mod; \ ++ \ ++ __quot = (n); \ ++ __high = __quot >> 32; \ ++ __low = __quot; \ ++ __upper = __high; \ ++ \ ++ if (__high) \ ++ __asm__("divu $0,%z2,%z3" \ ++ : "=h" (__upper), "=l" (__high) \ ++ : "Jr" (__high), "Jr" (base)); \ ++ \ ++ __mod = do_div64_32(__low, __upper, __low, base); \ ++ \ ++ __quot = __high; \ ++ __quot = __quot << 32 | __low; \ ++ (n) = __quot; \ ++ __mod; }) ++ ++#else ++ ++#define do_div64_32(res, high, low, base) ({ \ ++ unsigned long __quot, __mod, __r0; \ ++ \ ++ __asm__("dsll32 %2,%z3,0\n\t" \ ++ "or %2,%2,%z4\n\t" \ ++ "ddivu $0,%2,%z5" \ ++ : "=h" (__mod), "=l" (__quot), "=&r" (__r0) \ ++ : "Jr" (high), "Jr" (low), "Jr" (base)); \ ++ \ ++ (res) = __quot; \ ++ __mod; }) ++ ++#define do_div(n, base) ({ \ ++ unsigned long long __quot; \ ++ unsigned long __mod, __r0; \ ++ \ ++ __quot = (n); \ ++ \ ++ __asm__("dsll32 %2,%M3,0\n\t" \ ++ "or %2,%2,%L3\n\t" \ ++ "ddivu $0,%2,%z4\n\t" \ ++ "mflo %L1\n\t" \ ++ "dsra32 %M1,%L1,0\n\t" \ ++ "dsll32 %L1,%L1,0\n\t" \ ++ "dsra32 %L1,%L1,0" \ ++ : "=h" (__mod), "=r" (__quot), "=&r" (__r0) \ ++ : "r" (n), "Jr" (base)); \ ++ \ ++ (n) = __quot; \ ++ __mod; }) ++ ++#endif + + #endif /* _ASM_DIV64_H */ +diff -ruN linux/include/asm-mips/fcntl.h linux-mips/include/asm-mips/fcntl.h +--- linux/include/asm-mips/fcntl.h Thu Nov 23 15:51:49 2000 ++++ linux-mips/include/asm-mips/fcntl.h Fri Nov 10 00:11:44 2000 +@@ -1,13 +1,12 @@ +-/* $Id: fcntl.h,v 1.4 1998/09/19 19:19:36 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle + */ +-#ifndef __ASM_MIPS_FCNTL_H +-#define __ASM_MIPS_FCNTL_H ++#ifndef __ASM_FCNTL_H ++#define __ASM_FCNTL_H + + /* open/fcntl - O_SYNC is only implemented on blocks devices and on files + located on an ext2 file system */ +@@ -44,6 +43,10 @@ + #define F_SETSIG 10 /* for sockets. */ + #define F_GETSIG 11 /* for sockets. */ + ++#define F_GETLK64 33 /* using 'struct flock64' */ ++#define F_SETLK64 34 ++#define F_SETLKW64 35 ++ + /* for F_[GET|SET]FL */ + #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ + +@@ -76,10 +79,19 @@ + short l_whence; + __kernel_off_t l_start; + __kernel_off_t l_len; +- long l_sysid; /* XXXXXXXXXXXXXXXXXXXXXXXXX */ ++ long l_sysid; /* ABI junk, unused on Linux */ + __kernel_pid_t l_pid; +- long pad[4]; /* ZZZZZZZZZZZZZZZZZZZZZZZZZZ */ ++ long pad[4]; /* ABI junk, unused on Linux */ + } flock_t; + ++typedef struct flock64 { ++ short l_type; ++ short l_whence; ++ loff_t l_start; ++ loff_t l_len; ++ pid_t l_pid; ++} flock64_t; ++ + #define F_LINUX_SPECIFIC_BASE 1024 +-#endif /* __ASM_MIPS_FCNTL_H */ ++ ++#endif /* __ASM_FCNTL_H */ +diff -ruN linux/include/asm-mips/galileo-boards/ev96100.h linux-mips/include/asm-mips/galileo-boards/ev96100.h +--- linux/include/asm-mips/galileo-boards/ev96100.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/ev96100.h Fri Nov 10 00:12:16 2000 +@@ -0,0 +1,55 @@ ++/* ++ * ++ */ ++#ifndef _MIPS_EV96100_H ++#define _MIPS_EV96100_H ++ ++#include <asm/addrspace.h> ++ ++/* ++ * GT64120 config space base address ++ */ ++#define GT64120_BASE (KSEG1ADDR(0x14000000)) ++#define MIPS_GT_BASE GT64120_BASE ++ ++/* ++ * PCI Bus allocation ++ */ ++#define GT_PCI_MEM_BASE 0x12000000 ++#define GT_PCI_MEM_SIZE 0x02000000 ++#define GT_PCI_IO_BASE 0x10000000 ++#define GT_PCI_IO_SIZE 0x02000000 ++#define GT_ISA_IO_BASE PCI_IO_BASE ++ ++/* ++ * Duart I/O ports. ++ */ ++#define EV96100_COM1_BASE_ADDR (0x1d000000 + 0x20) ++#define EV96100_COM2_BASE_ADDR (0x1d000000 + 0x00) ++ ++ ++/* ++ * EV96100 interrupt controller register base. ++ */ ++#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) ++ ++/* ++ * EV96100 UART register base. ++ */ ++#define EV96100_UART0_REGS_BASE (KSEG1ADDR(EV96100_COM1_BASE_ADDR)) ++#define EV96100_UART1_REGS_BASE (KSEG1ADDR(EV96100_COM2_BASE_ADDR)) ++#define EV96100_BASE_BAUD ( 3686400 / 16 ) ++ ++ ++/* ++ * Because of an error/peculiarity in the Galileo chip, we need to swap the ++ * bytes when running bigendian. ++ */ ++ ++#define GT_WRITE(ofs, data) \ ++ *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) ++#define GT_READ(ofs, data) \ ++ data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) ++ ++ ++#endif /* !(_MIPS_EV96100_H) */ +diff -ruN linux/include/asm-mips/galileo-boards/ev96100int.h linux-mips/include/asm-mips/galileo-boards/ev96100int.h +--- linux/include/asm-mips/galileo-boards/ev96100int.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/ev96100int.h Fri Nov 10 00:12:16 2000 +@@ -0,0 +1,12 @@ ++/* ++ * ++ */ ++#ifndef _MIPS_EV96100INT_H ++#define _MIPS_EV96100INT_H ++ ++#define EV96100INT_UART_0 6 /* IP 6 */ ++#define EV96100INT_TIMER 7 /* IP 7 */ ++ ++extern void ev96100int_init(void); ++ ++#endif /* !(_MIPS_EV96100_H) */ +diff -ruN linux/include/asm-mips/galileo-boards/gt64120.h linux-mips/include/asm-mips/galileo-boards/gt64120.h +--- linux/include/asm-mips/galileo-boards/gt64120.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/gt64120.h Fri Nov 10 00:12:17 2000 +@@ -0,0 +1,320 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register definitions for Galileo 64120 system controller. ++ * ++ */ ++#ifndef GT64120_H ++#define GT64120_H ++ ++#define MSK(n) ((1 << (n)) - 1) ++ ++/************************************************************************ ++ * Register offset addresses ++ ************************************************************************/ ++ ++#define GT_CPU_OFS 0x000 ++ ++#define GT_INTRCAUSE_OFS 0xc18 ++#define GT_PCI0_CFGADDR_OFS 0xcf8 ++#define GT_PCI0_CFGDATA_OFS 0xcfc ++#define GT_SDRAM_BM_OFS 0x478 ++#define GT_SDRAM_ADDRDECODE_OFS 0x47c ++#define GT_SDRAM_B0_OFS 0x44c ++#define GT_SDRAM_B2_OFS 0x454 ++#define GT_SDRAM_CFG_OFS 0x448 ++#define GT_SDRAM_OPMODE_OFS 0x474 ++ ++#define GT_ISD_OFS 0x068 ++ ++#define GT_SCS10LD_OFS 0x008 ++#define GT_SCS10HD_OFS 0x010 ++#define GT_SCS32LD_OFS 0x018 ++#define GT_SCS32HD_OFS 0x020 ++#define GT_CS20LD_OFS 0x028 ++#define GT_CS20HD_OFS 0x030 ++#define GT_CS3BOOTLD_OFS 0x038 ++#define GT_CS3BOOTHD_OFS 0x040 ++#define GT_PCI0IOLD_OFS 0x048 ++#define GT_PCI0IOHD_OFS 0x050 ++#define GT_PCI0M0LD_OFS 0x058 ++#define GT_PCI0M0HD_OFS 0x060 ++#define GT_PCI0M1LD_OFS 0x080 ++#define GT_PCI0M1HD_OFS 0x088 ++#define GT_PCI1IOLD_OFS 0x090 ++#define GT_PCI1IOHD_OFS 0x098 ++#define GT_PCI1M0LD_OFS 0x0a0 ++#define GT_PCI1M0HD_OFS 0x0a8 ++#define GT_PCI1M1LD_OFS 0x0b0 ++#define GT_PCI1M1HD_OFS 0x0b8 ++ ++#define GT_SCS0LD_OFS 0x400 ++#define GT_SCS0HD_OFS 0x404 ++#define GT_SCS1LD_OFS 0x408 ++#define GT_SCS1HD_OFS 0x40c ++#define GT_SCS2LD_OFS 0x410 ++#define GT_SCS2HD_OFS 0x414 ++#define GT_SCS3LD_OFS 0x418 ++#define GT_SCS3HD_OFS 0x41c ++#define GT_CS0LD_OFS 0x420 ++#define GT_CS0HD_OFS 0x424 ++#define GT_CS1LD_OFS 0x428 ++#define GT_CS1HD_OFS 0x42c ++#define GT_CS2LD_OFS 0x430 ++#define GT_CS2HD_OFS 0x434 ++#define GT_CS3LD_OFS 0x438 ++#define GT_CS3HD_OFS 0x43c ++#define GT_BOOTLD_OFS 0x440 ++#define GT_BOOTHD_OFS 0x444 ++ ++#define GT_PCI0_BS_SCS10_OFS 0Xc08 ++#define GT_PCI0_BS_SCS32_OFS 0xc0c ++#define GT_PCI0_BARE_OFS 0Xc3c ++ ++#define GT_PCI0_TOR_OFS 0xc04 ++ ++#define GT_PCI0_IACK_OFS 0xc34 ++ ++ ++/************************************************************************ ++ * Register encodings ++ ************************************************************************/ ++ ++#define GT_CPU_WR_SHF 16 ++#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) ++#define GT_CPU_WR_BIT GT_CPU_WR_MSK ++#define GT_CPU_WR_DXDXDXDX 0 ++#define GT_CPU_WR_DDDD 1 ++ ++ ++#define GT_CFGADDR_CFGEN_SHF 31 ++#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) ++#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK ++ ++#define GT_CFGADDR_BUSNUM_SHF 16 ++#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) ++ ++#define GT_CFGADDR_DEVNUM_SHF 11 ++#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) ++ ++#define GT_CFGADDR_FUNCNUM_SHF 8 ++#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) ++ ++#define GT_CFGADDR_REGNUM_SHF 2 ++#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) ++ ++ ++#define GT_SDRAM_BM_ORDER_SHF 2 ++#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) ++#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK ++#define GT_SDRAM_BM_ORDER_SUB 1 ++#define GT_SDRAM_BM_ORDER_LIN 0 ++ ++#define GT_SDRAM_BM_RSVD_ALL1 0xFFB ++ ++ ++#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) ++#define GT_SDRAM_ADDRDECODE_ADDR_0 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_1 1 ++#define GT_SDRAM_ADDRDECODE_ADDR_2 2 ++#define GT_SDRAM_ADDRDECODE_ADDR_3 3 ++#define GT_SDRAM_ADDRDECODE_ADDR_4 4 ++#define GT_SDRAM_ADDRDECODE_ADDR_5 5 ++#define GT_SDRAM_ADDRDECODE_ADDR_6 6 ++#define GT_SDRAM_ADDRDECODE_ADDR_7 7 ++ ++ ++#define GT_SDRAM_B0_CASLAT_SHF 0 ++#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) ++#define GT_SDRAM_B0_CASLAT_2 1 ++#define GT_SDRAM_B0_CASLAT_3 2 ++ ++#define GT_SDRAM_B0_FTDIS_SHF 2 ++#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) ++#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK ++ ++#define GT_SDRAM_B0_SRASPRCHG_SHF 3 ++#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) ++#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK ++#define GT_SDRAM_B0_SRASPRCHG_2 0 ++#define GT_SDRAM_B0_SRASPRCHG_3 1 ++ ++#define GT_SDRAM_B0_B0COMPAB_SHF 4 ++#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) ++#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK ++ ++#define GT_SDRAM_B0_64BITINT_SHF 5 ++#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) ++#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK ++#define GT_SDRAM_B0_64BITINT_2 0 ++#define GT_SDRAM_B0_64BITINT_4 1 ++ ++#define GT_SDRAM_B0_BW_SHF 6 ++#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) ++#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK ++#define GT_SDRAM_B0_BW_32 0 ++#define GT_SDRAM_B0_BW_64 1 ++ ++#define GT_SDRAM_B0_BLODD_SHF 7 ++#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) ++#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK ++ ++#define GT_SDRAM_B0_PAR_SHF 8 ++#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) ++#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK ++ ++#define GT_SDRAM_B0_BYPASS_SHF 9 ++#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) ++#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK ++ ++#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 ++#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) ++#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK ++#define GT_SDRAM_B0_SRAS2SCAS_2 0 ++#define GT_SDRAM_B0_SRAS2SCAS_3 1 ++ ++#define GT_SDRAM_B0_SIZE_SHF 11 ++#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) ++#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK ++#define GT_SDRAM_B0_SIZE_16M 0 ++#define GT_SDRAM_B0_SIZE_64M 1 ++ ++#define GT_SDRAM_B0_EXTPAR_SHF 12 ++#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) ++#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK ++ ++#define GT_SDRAM_B0_BLEN_SHF 13 ++#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) ++#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK ++#define GT_SDRAM_B0_BLEN_8 0 ++#define GT_SDRAM_B0_BLEN_4 1 ++ ++ ++#define GT_SDRAM_CFG_REFINT_SHF 0 ++#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) ++ ++#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 ++#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) ++#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK ++ ++#define GT_SDRAM_CFG_RMW_SHF 15 ++#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) ++#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK ++ ++#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 ++#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) ++#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK ++ ++#define GT_SDRAM_CFG_DUPCNTL_SHF 19 ++#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) ++#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK ++ ++#define GT_SDRAM_CFG_DUPBA_SHF 20 ++#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) ++#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT0_SHF 21 ++#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) ++#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT1_SHF 22 ++#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) ++#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK ++ ++#define GT_SDRAM_OPMODE_OP_SHF 0 ++#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) ++#define GT_SDRAM_OPMODE_OP_NORMAL 0 ++#define GT_SDRAM_OPMODE_OP_NOP 1 ++#define GT_SDRAM_OPMODE_OP_PRCHG 2 ++#define GT_SDRAM_OPMODE_OP_MODE 3 ++#define GT_SDRAM_OPMODE_OP_CBR 4 ++ ++ ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 ++#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) ++#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 ++#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) ++#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK ++ ++#define GT_PCI0_BARE_INTIODIS_SHF 3 ++#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) ++#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK ++ ++#define GT_PCI0_BARE_INTMEMDIS_SHF 4 ++#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) ++#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK ++ ++#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 ++#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_CS20DIS_SHF 6 ++#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) ++#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK ++ ++#define GT_PCI0_BARE_SCS32DIS_SHF 7 ++#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) ++#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SCS10DIS_SHF 8 ++#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) ++#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK ++ ++ ++#define GT_INTRCAUSE_MASABORT0_SHF 18 ++#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) ++#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK ++ ++#define GT_INTRCAUSE_TARABORT0_SHF 19 ++#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) ++#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK ++ ++ ++#define GT_PCI0_CFGADDR_REGNUM_SHF 2 ++#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) ++#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 ++#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) ++#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 ++#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) ++#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 ++#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 ++#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK ++ ++ ++/************************************************************************ ++ * Misc ++ ************************************************************************/ ++ ++#define GT_DEF_BASE 0x14000000 ++#define GT_DEF_PCI0_MEM0_BASE 0x12000000 ++#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ ++#define GT_LATTIM_MIN 6 /* Minimum lat */ ++ ++#endif /* #ifndef GT64120_H */ +diff -ruN linux/include/asm-mips/galileo-boards/gt96100.h linux-mips/include/asm-mips/galileo-boards/gt96100.h +--- linux/include/asm-mips/galileo-boards/gt96100.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/gt96100.h Fri Nov 10 00:12:18 2000 +@@ -0,0 +1,432 @@ ++/* ++ * Copyright 2000 MontaVista Software Inc. ++ * Author: MontaVista Software, Inc. ++ * stevel@mvista.com or support@mvista.com ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register offsets of the MIPS GT96100 Advanced Communication Controller. ++ * ++ */ ++#ifndef _GT96100_H ++#define _GT96100_H ++ ++/* ++ * Galileo GT96100 internal register base. ++ */ ++#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000)) ++ ++#define GT96100_WRITE(ofs, data) \ ++ *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data) ++#define GT96100_READ(ofs) \ ++ le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs)) ++ ++#define GT96100_ETH_IO_SIZE 0x4000 ++ ++/************************************************************************ ++ * Register offset addresses follow ++ ************************************************************************/ ++ ++/* CPU Interface Control Registers */ ++#define GT96100_CPU_INTERF_CONFIG 0x000000 ++ ++/* Ethernet Ports */ ++#define GT96100_ETH_PHY_ADDR_REG 0x080800 ++#define GT96100_ETH_SMI_REG 0x080810 ++/* ++ These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to ++ get offsets to port 1 registers. ++*/ ++#define GT96100_ETH_PORT_CONFIG 0x084800 ++#define GT96100_ETH_PORT_CONFIG_EXT 0x084808 ++#define GT96100_ETH_PORT_COMM 0x084810 ++#define GT96100_ETH_PORT_STATUS 0x084818 ++#define GT96100_ETH_SER_PARAM 0x084820 ++#define GT96100_ETH_HASH_TBL_PTR 0x084828 ++#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830 ++#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838 ++#define GT96100_ETH_SDMA_CONFIG 0x084840 ++#define GT96100_ETH_SDMA_COMM 0x084848 ++#define GT96100_ETH_INT_CAUSE 0x084850 ++#define GT96100_ETH_INT_MASK 0x084858 ++#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880 ++#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884 ++#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888 ++#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C ++#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0 ++#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4 ++#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8 ++#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC ++#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0 ++#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4 ++#define GT96100_ETH_MIB_COUNT_BASE 0x085800 ++ ++/* SDMAs */ ++#define GT96100_SDMA_GROUP_CONFIG 0x101AF0 ++/* SDMA Group 0 */ ++#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900 ++#define GT96100_SDMA_G0_CHAN0_COMM 0x000908 ++#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900 ++#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910 ++#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900 ++#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910 ++#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914 ++#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900 ++#define GT96100_SDMA_G0_CHAN1_COMM 0x010908 ++#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900 ++#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910 ++#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900 ++#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910 ++#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914 ++#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900 ++#define GT96100_SDMA_G0_CHAN2_COMM 0x020908 ++#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900 ++#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910 ++#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900 ++#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910 ++#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914 ++#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900 ++#define GT96100_SDMA_G0_CHAN3_COMM 0x030908 ++#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900 ++#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910 ++#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900 ++#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910 ++#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914 ++#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900 ++#define GT96100_SDMA_G0_CHAN4_COMM 0x040908 ++#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900 ++#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910 ++#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900 ++#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910 ++#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914 ++#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900 ++#define GT96100_SDMA_G0_CHAN5_COMM 0x050908 ++#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900 ++#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910 ++#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900 ++#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910 ++#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914 ++#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900 ++#define GT96100_SDMA_G0_CHAN6_COMM 0x060908 ++#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900 ++#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910 ++#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900 ++#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910 ++#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914 ++#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900 ++#define GT96100_SDMA_G0_CHAN7_COMM 0x070908 ++#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900 ++#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910 ++#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900 ++#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910 ++#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914 ++/* SDMA Group 1 */ ++#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900 ++#define GT96100_SDMA_G1_CHAN0_COMM 0x100908 ++#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900 ++#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910 ++#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900 ++#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910 ++#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914 ++#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900 ++#define GT96100_SDMA_G1_CHAN1_COMM 0x110908 ++#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900 ++#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910 ++#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900 ++#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910 ++#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914 ++#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900 ++#define GT96100_SDMA_G1_CHAN2_COMM 0x120908 ++#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900 ++#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910 ++#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900 ++#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910 ++#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914 ++#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900 ++#define GT96100_SDMA_G1_CHAN3_COMM 0x130908 ++#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900 ++#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910 ++#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900 ++#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910 ++#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914 ++#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900 ++#define GT96100_SDMA_G1_CHAN4_COMM 0x140908 ++#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900 ++#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910 ++#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900 ++#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910 ++#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914 ++#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900 ++#define GT96100_SDMA_G1_CHAN5_COMM 0x150908 ++#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900 ++#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910 ++#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900 ++#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910 ++#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914 ++#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900 ++#define GT96100_SDMA_G1_CHAN6_COMM 0x160908 ++#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900 ++#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910 ++#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900 ++#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910 ++#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914 ++#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900 ++#define GT96100_SDMA_G1_CHAN7_COMM 0x170908 ++#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900 ++#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910 ++#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900 ++#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910 ++#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914 ++/* MPSCs */ ++#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00 ++#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04 ++#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08 ++#define GT96100_MPSC_CHAN0_REG1 0x000A0C ++#define GT96100_MPSC_CHAN0_REG2 0x000A10 ++#define GT96100_MPSC_CHAN0_REG3 0x000A14 ++#define GT96100_MPSC_CHAN0_REG4 0x000A18 ++#define GT96100_MPSC_CHAN0_REG5 0x000A1C ++#define GT96100_MPSC_CHAN0_REG6 0x000A20 ++#define GT96100_MPSC_CHAN0_REG7 0x000A24 ++#define GT96100_MPSC_CHAN0_REG8 0x000A28 ++#define GT96100_MPSC_CHAN0_REG9 0x000A2C ++#define GT96100_MPSC_CHAN0_REG10 0x000A30 ++#define GT96100_MPSC_CHAN0_REG11 0x000A34 ++#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00 ++#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04 ++#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08 ++#define GT96100_MPSC_CHAN1_REG1 0x008A0C ++#define GT96100_MPSC_CHAN1_REG2 0x008A10 ++#define GT96100_MPSC_CHAN1_REG3 0x008A14 ++#define GT96100_MPSC_CHAN1_REG4 0x008A18 ++#define GT96100_MPSC_CHAN1_REG5 0x008A1C ++#define GT96100_MPSC_CHAN1_REG6 0x008A20 ++#define GT96100_MPSC_CHAN1_REG7 0x008A24 ++#define GT96100_MPSC_CHAN1_REG8 0x008A28 ++#define GT96100_MPSC_CHAN1_REG9 0x008A2C ++#define GT96100_MPSC_CHAN1_REG10 0x008A30 ++#define GT96100_MPSC_CHAN1_REG11 0x008A34 ++#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00 ++#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04 ++#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08 ++#define GT96100_MPSC_CHAN2_REG1 0x010A0C ++#define GT96100_MPSC_CHAN2_REG2 0x010A10 ++#define GT96100_MPSC_CHAN2_REG3 0x010A14 ++#define GT96100_MPSC_CHAN2_REG4 0x010A18 ++#define GT96100_MPSC_CHAN2_REG5 0x010A1C ++#define GT96100_MPSC_CHAN2_REG6 0x010A20 ++#define GT96100_MPSC_CHAN2_REG7 0x010A24 ++#define GT96100_MPSC_CHAN2_REG8 0x010A28 ++#define GT96100_MPSC_CHAN2_REG9 0x010A2C ++#define GT96100_MPSC_CHAN2_REG10 0x010A30 ++#define GT96100_MPSC_CHAN2_REG11 0x010A34 ++#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00 ++#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04 ++#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08 ++#define GT96100_MPSC_CHAN3_REG1 0x018A0C ++#define GT96100_MPSC_CHAN3_REG2 0x018A10 ++#define GT96100_MPSC_CHAN3_REG3 0x018A14 ++#define GT96100_MPSC_CHAN3_REG4 0x018A18 ++#define GT96100_MPSC_CHAN3_REG5 0x018A1C ++#define GT96100_MPSC_CHAN3_REG6 0x018A20 ++#define GT96100_MPSC_CHAN3_REG7 0x018A24 ++#define GT96100_MPSC_CHAN3_REG8 0x018A28 ++#define GT96100_MPSC_CHAN3_REG9 0x018A2C ++#define GT96100_MPSC_CHAN3_REG10 0x018A30 ++#define GT96100_MPSC_CHAN3_REG11 0x018A34 ++#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00 ++#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04 ++#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08 ++#define GT96100_MPSC_CHAN4_REG1 0x020A0C ++#define GT96100_MPSC_CHAN4_REG2 0x020A10 ++#define GT96100_MPSC_CHAN4_REG3 0x020A14 ++#define GT96100_MPSC_CHAN4_REG4 0x020A18 ++#define GT96100_MPSC_CHAN4_REG5 0x020A1C ++#define GT96100_MPSC_CHAN4_REG6 0x020A20 ++#define GT96100_MPSC_CHAN4_REG7 0x020A24 ++#define GT96100_MPSC_CHAN4_REG8 0x020A28 ++#define GT96100_MPSC_CHAN4_REG9 0x020A2C ++#define GT96100_MPSC_CHAN4_REG10 0x020A30 ++#define GT96100_MPSC_CHAN4_REG11 0x020A34 ++#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00 ++#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04 ++#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08 ++#define GT96100_MPSC_CHAN5_REG1 0x028A0C ++#define GT96100_MPSC_CHAN5_REG2 0x028A10 ++#define GT96100_MPSC_CHAN5_REG3 0x028A14 ++#define GT96100_MPSC_CHAN5_REG4 0x028A18 ++#define GT96100_MPSC_CHAN5_REG5 0x028A1C ++#define GT96100_MPSC_CHAN5_REG6 0x028A20 ++#define GT96100_MPSC_CHAN5_REG7 0x028A24 ++#define GT96100_MPSC_CHAN5_REG8 0x028A28 ++#define GT96100_MPSC_CHAN5_REG9 0x028A2C ++#define GT96100_MPSC_CHAN5_REG10 0x028A30 ++#define GT96100_MPSC_CHAN5_REG11 0x028A34 ++#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00 ++#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04 ++#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08 ++#define GT96100_MPSC_CHAN6_REG1 0x030A0C ++#define GT96100_MPSC_CHAN6_REG2 0x030A10 ++#define GT96100_MPSC_CHAN6_REG3 0x030A14 ++#define GT96100_MPSC_CHAN6_REG4 0x030A18 ++#define GT96100_MPSC_CHAN6_REG5 0x030A1C ++#define GT96100_MPSC_CHAN6_REG6 0x030A20 ++#define GT96100_MPSC_CHAN6_REG7 0x030A24 ++#define GT96100_MPSC_CHAN6_REG8 0x030A28 ++#define GT96100_MPSC_CHAN6_REG9 0x030A2C ++#define GT96100_MPSC_CHAN6_REG10 0x030A30 ++#define GT96100_MPSC_CHAN6_REG11 0x030A34 ++#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00 ++#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04 ++#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08 ++#define GT96100_MPSC_CHAN7_REG1 0x038A0C ++#define GT96100_MPSC_CHAN7_REG2 0x038A10 ++#define GT96100_MPSC_CHAN7_REG3 0x038A14 ++#define GT96100_MPSC_CHAN7_REG4 0x038A18 ++#define GT96100_MPSC_CHAN7_REG5 0x038A1C ++#define GT96100_MPSC_CHAN7_REG6 0x038A20 ++#define GT96100_MPSC_CHAN7_REG7 0x038A24 ++#define GT96100_MPSC_CHAN7_REG8 0x038A28 ++#define GT96100_MPSC_CHAN7_REG9 0x038A2C ++#define GT96100_MPSC_CHAN7_REG10 0x038A30 ++#define GT96100_MPSC_CHAN7_REG11 0x038A34 ++/* FlexTDMs */ ++/* TDPR0 - Transmit Dual Port RAM. block size 0xff */ ++#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00 ++#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00 ++#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00 ++#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00 ++/* RDPR0 - Receive Dual Port RAM. block size 0xff */ ++#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00 ++#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00 ++#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00 ++#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00 ++#define GT96100_FXTDM0_TX_READ_PTR 0x008B00 ++#define GT96100_FXTDM0_RX_READ_PTR 0x008B04 ++#define GT96100_FXTDM0_CONFIG 0x008B08 ++#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C ++#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10 ++#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14 ++#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18 ++#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00 ++#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00 ++#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00 ++#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00 ++#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00 ++#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00 ++#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00 ++#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00 ++#define GT96100_FXTDM1_TX_READ_PTR 0x018B00 ++#define GT96100_FXTDM1_RX_READ_PTR 0x018B04 ++#define GT96100_FXTDM1_CONFIG 0x018B08 ++#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C ++#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10 ++#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14 ++#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18 ++#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00 ++#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00 ++#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00 ++#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00 ++#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00 ++#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00 ++#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00 ++#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00 ++#define GT96100_FLTDM2_TX_READ_PTR 0x028B00 ++#define GT96100_FLTDM2_RX_READ_PTR 0x028B04 ++#define GT96100_FLTDM2_CONFIG 0x028B08 ++#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C ++#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10 ++#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14 ++#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18 ++#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00 ++#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00 ++#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00 ++#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00 ++#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00 ++#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00 ++#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00 ++#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00 ++#define GT96100_FXTDM3_TX_READ_PTR 0x038B00 ++#define GT96100_FXTDM3_RX_READ_PTR 0x038B04 ++#define GT96100_FXTDM3_CONFIG 0x038B08 ++#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C ++#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10 ++#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14 ++#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18 ++/* Baud Rate Generators */ ++#define GT96100_BRG0_CONFIG 0x102A00 ++#define GT96100_BRG0_BAUD_TUNE 0x102A04 ++#define GT96100_BRG1_CONFIG 0x102A08 ++#define GT96100_BRG1_BAUD_TUNE 0x102A0C ++#define GT96100_BRG2_CONFIG 0x102A10 ++#define GT96100_BRG2_BAUD_TUNE 0x102A14 ++#define GT96100_BRG3_CONFIG 0x102A18 ++#define GT96100_BRG3_BAUD_TUNE 0x102A1C ++#define GT96100_BRG4_CONFIG 0x102A20 ++#define GT96100_BRG4_BAUD_TUNE 0x102A24 ++#define GT96100_BRG5_CONFIG 0x102A28 ++#define GT96100_BRG5_BAUD_TUNE 0x102A2C ++#define GT96100_BRG6_CONFIG 0x102A30 ++#define GT96100_BRG6_BAUD_TUNE 0x102A34 ++#define GT96100_BRG7_CONFIG 0x102A38 ++#define GT96100_BRG7_BAUD_TUNE 0x102A3C ++/* Routing Registers */ ++#define GT96100_ROUTE_MAIN 0x101A00 ++#define GT96100_ROUTE_RX_CLOCK 0x101A10 ++#define GT96100_ROUTE_TX_CLOCK 0x101A20 ++/* General Purpose Ports */ ++#define GT96100_GPP_CONFIG0 0x100A00 ++#define GT96100_GPP_CONFIG1 0x100A04 ++#define GT96100_GPP_CONFIG2 0x100A08 ++#define GT96100_GPP_CONFIG3 0x100A0C ++#define GT96100_GPP_IO0 0x100A20 ++#define GT96100_GPP_IO1 0x100A24 ++#define GT96100_GPP_IO2 0x100A28 ++#define GT96100_GPP_IO3 0x100A2C ++#define GT96100_GPP_DATA0 0x100A40 ++#define GT96100_GPP_DATA1 0x100A44 ++#define GT96100_GPP_DATA2 0x100A48 ++#define GT96100_GPP_DATA3 0x100A4C ++#define GT96100_GPP_LEVEL0 0x100A60 ++#define GT96100_GPP_LEVEL1 0x100A64 ++#define GT96100_GPP_LEVEL2 0x100A68 ++#define GT96100_GPP_LEVEL3 0x100A6C ++/* Watchdog */ ++#define GT96100_WD_CONFIG 0x101A80 ++#define GT96100_WD_VALUE 0x101A84 ++/* Communication Unit Arbiter */ ++#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0 ++/* PCI Arbiters */ ++#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0 ++#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4 ++/* CIU Arbiter */ ++#define GT96100_CIU_ARBITER_CONFIG 0x101AC0 ++/* Interrupt Controller */ ++#define GT96100_MAIN_CAUSE 0x000C18 ++#define GT96100_INT0_MAIN_MASK 0x000C1C ++#define GT96100_INT1_MAIN_MASK 0x000C24 ++#define GT96100_HIGH_CAUSE 0x000C98 ++#define GT96100_INT0_HIGH_MASK 0x000C9C ++#define GT96100_INT1_HIGH_MASK 0x000CA4 ++#define GT96100_INT0_SELECT 0x000C70 ++#define GT96100_INT1_SELECT 0x000C74 ++#define GT96100_SERIAL_CAUSE 0x103A00 ++#define GT96100_SERINT0_MASK 0x103A80 ++#define GT96100_SERINT1_MASK 0x103A88 ++ ++#endif /* _GT96100_H */ +diff -ruN linux/include/asm-mips/io.h linux-mips/include/asm-mips/io.h +--- linux/include/asm-mips/io.h Mon Feb 28 07:18:20 2000 ++++ linux-mips/include/asm-mips/io.h Fri Nov 10 00:11:47 2000 +@@ -317,6 +317,57 @@ + __OUTS(h,w,2) + __OUTS(w,l,4) + ++ ++#ifdef CONFIG_MIPS_EV96100 ++ ++#include <asm/byteorder.h> ++ ++#define inb(port) in_8((u8 *)((port)+mips_io_port_base)) ++#define outb(val, port) out_8((u8 *)((port)+mips_io_port_base), (val)) ++#define inw(port) in_16((u16 *)((port)+mips_io_port_base)) ++#define outw(val, port) out_16((u16 *)((port)+mips_io_port_base), (val)) ++#define inl(port) in_32((u32 *)((port)+mips_io_port_base)) ++#define outl(val, port) out_32((u32 *)((port)+mips_io_port_base), (val)) ++ ++#define inb_p(port) inb((port)) ++#define outb_p(val, port) outb((val), (port)) ++#define inw_p(port) inw((port)) ++#define outw_p(val, port) outw((val), (port)) ++#define inl_p(port) inl((port)) ++#define outl_p(val, port) outl((val), (port)) ++ ++extern inline unsigned char in_8(const unsigned char *addr) ++{ ++ return *KSEG1ADDR(addr); ++} ++ ++extern inline void out_8(unsigned char *addr, unsigned int val) ++{ ++ *KSEG1ADDR(addr) = (unsigned char)val; ++} ++ ++extern inline unsigned short in_16(const unsigned short *addr) ++{ ++ return (le16_to_cpu(*KSEG1ADDR(addr))); ++} ++ ++extern inline void out_16(unsigned short *addr, unsigned int val) ++{ ++ *KSEG1ADDR(addr) = cpu_to_le16((unsigned short)val); ++} ++ ++extern inline unsigned int in_32(const unsigned int *addr) ++{ ++ return (le32_to_cpu(*KSEG1ADDR(addr))); ++} ++ ++extern inline void out_32(unsigned int *addr, unsigned int val) ++{ ++ *KSEG1ADDR(addr) = cpu_to_le32((unsigned int)val); ++} ++ ++#else ++ + /* + * Note that due to the way __builtin_constant_p() works, you + * - can't use it inside an inline function (it will never be true) +@@ -412,6 +463,7 @@ + ((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inslc((port),(addr),(count)) : \ + __insl((port),(addr),(count))) ++#endif + + #define IO_SPACE_LIMIT 0xffff + +diff -ruN linux/include/asm-mips/irq.h linux-mips/include/asm-mips/irq.h +--- linux/include/asm-mips/irq.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/irq.h Fri Nov 10 00:11:47 2000 +@@ -1,20 +1,28 @@ +-/* $Id: irq.h,v 1.6 2000/01/26 00:07:45 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle +- * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle ++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle + */ + #ifndef _ASM_IRQ_H + #define _ASM_IRQ_H + ++#include <linux/config.h> ++ + #define NR_IRQS 64 + + #define TIMER_IRQ 0 + +-extern int (*irq_cannonicalize)(int irq); ++#ifdef CONFIG_I8259 ++static inline int irq_cannonicalize(int irq) ++{ ++ return ((irq == 2) ? 9 : irq); ++} ++#else ++#define irq_cannonicalize(irq) (irq) /* Sane hardware, sane code ... */ ++#endif + + struct irqaction; + extern int i8259_setup_irq(int irq, struct irqaction * new); +diff -ruN linux/include/asm-mips/mc146818rtc.h linux-mips/include/asm-mips/mc146818rtc.h +--- linux/include/asm-mips/mc146818rtc.h Fri Aug 4 18:31:19 2000 ++++ linux-mips/include/asm-mips/mc146818rtc.h Fri Nov 10 00:11:51 2000 +@@ -49,4 +49,6 @@ + #define RTC_IRQ 8 + #endif + ++#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ ++ + #endif /* _ASM_MC146818RTC_H */ +diff -ruN linux/include/asm-mips/mips-boards/atlas.h linux-mips/include/asm-mips/mips-boards/atlas.h +--- linux/include/asm-mips/mips-boards/atlas.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/atlas.h Fri Nov 10 00:12:18 2000 +@@ -0,0 +1,55 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines of the Atlas board specific address-MAP, registers, etc. ++ * ++ */ ++#ifndef _MIPS_ATLAS_H ++#define _MIPS_ATLAS_H ++ ++#include <asm/addrspace.h> ++ ++/* ++ * Atlas RTC-device indirect register access. ++ */ ++#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800)) ++#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808)) ++ ++ ++/* ++ * Atlas interrupt controller register base. ++ */ ++#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) ++ ++/* ++ * Atlas UART register base. ++ */ ++#define ATLAS_UART_REGS_BASE (KSEG1ADDR(0x1f000900)) ++#define ATLAS_BASE_BAUD ( 3686400 / 16 ) ++ ++/* ++ * Atlas PSU standby register. ++ */ ++#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600)) ++#define ATLAS_GOSTBY 0x4d ++ ++ ++#endif /* !(_MIPS_ATLAS_H) */ +diff -ruN linux/include/asm-mips/mips-boards/atlasint.h linux-mips/include/asm-mips/mips-boards/atlasint.h +--- linux/include/asm-mips/mips-boards/atlasint.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/atlasint.h Fri Nov 10 00:12:18 2000 +@@ -0,0 +1,51 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines for the Atlas interrupt controller. ++ * ++ */ ++#ifndef _MIPS_ATLASINT_H ++#define _MIPS_ATLASINT_H ++ ++/* Number of IRQ supported on hw interrupt 0. */ ++#define ATLASINT_UART 0 ++#define ATLASINT_END 32 ++ ++/* ++ * Atlas registers are memory mapped on 64-bit aligned boundaries and ++ * only word access are allowed. ++ */ ++struct atlas_ictrl_regs { ++ volatile unsigned long intraw; ++ long dummy1; ++ volatile unsigned long intseten; ++ long dummy2; ++ volatile unsigned long intrsten; ++ long dummy3; ++ volatile unsigned long intenable; ++ long dummy4; ++ volatile unsigned long intstatus; ++ long dummy5; ++}; ++ ++extern void atlasint_init(void); ++ ++#endif /* !(_MIPS_ATLASINT_H) */ +diff -ruN linux/include/asm-mips/mips-boards/generic.h linux-mips/include/asm-mips/mips-boards/generic.h +--- linux/include/asm-mips/mips-boards/generic.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/generic.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,65 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines of the MIPS boards specific address-MAP, registers, etc. ++ * ++ */ ++#ifndef _MIPS_GENERIC_H ++#define _MIPS_GENERIC_H ++ ++#include <asm/addrspace.h> ++#include <asm/byteorder.h> ++ ++/* ++ * Display register base. ++ */ ++#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410)) ++#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418)) ++ ++ ++/* ++ * Yamon Prom print address. ++ */ ++#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504)) ++ ++ ++/* ++ * Reset register. ++ */ ++#define SOFTRES_REG (KSEG1ADDR(0x1f000500)) ++#define GORESET 0x42 ++ ++ ++/* ++ * Galileo GT64120 system controller register base. ++ */ ++#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000)) ++ ++/* ++ * Because of an error/peculiarity in the Galileo chip, we need to swap the ++ * bytes when running bigendian. ++ */ ++#define GT_WRITE(ofs, data) \ ++ *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) ++#define GT_READ(ofs, data) \ ++ data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) ++ ++#endif /* !(_MIPS_GENERIC_H) */ +diff -ruN linux/include/asm-mips/mips-boards/gt64120.h linux-mips/include/asm-mips/mips-boards/gt64120.h +--- linux/include/asm-mips/mips-boards/gt64120.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/gt64120.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,320 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register definitions for Galileo 64120 system controller. ++ * ++ */ ++#ifndef GT64120_H ++#define GT64120_H ++ ++#define MSK(n) ((1 << (n)) - 1) ++ ++/************************************************************************ ++ * Register offset addresses ++ ************************************************************************/ ++ ++#define GT_CPU_OFS 0x000 ++ ++#define GT_INTRCAUSE_OFS 0xc18 ++#define GT_PCI0_CFGADDR_OFS 0xcf8 ++#define GT_PCI0_CFGDATA_OFS 0xcfc ++#define GT_SDRAM_BM_OFS 0x478 ++#define GT_SDRAM_ADDRDECODE_OFS 0x47c ++#define GT_SDRAM_B0_OFS 0x44c ++#define GT_SDRAM_B2_OFS 0x454 ++#define GT_SDRAM_CFG_OFS 0x448 ++#define GT_SDRAM_OPMODE_OFS 0x474 ++ ++#define GT_ISD_OFS 0x068 ++ ++#define GT_SCS10LD_OFS 0x008 ++#define GT_SCS10HD_OFS 0x010 ++#define GT_SCS32LD_OFS 0x018 ++#define GT_SCS32HD_OFS 0x020 ++#define GT_CS20LD_OFS 0x028 ++#define GT_CS20HD_OFS 0x030 ++#define GT_CS3BOOTLD_OFS 0x038 ++#define GT_CS3BOOTHD_OFS 0x040 ++#define GT_PCI0IOLD_OFS 0x048 ++#define GT_PCI0IOHD_OFS 0x050 ++#define GT_PCI0M0LD_OFS 0x058 ++#define GT_PCI0M0HD_OFS 0x060 ++#define GT_PCI0M1LD_OFS 0x080 ++#define GT_PCI0M1HD_OFS 0x088 ++#define GT_PCI1IOLD_OFS 0x090 ++#define GT_PCI1IOHD_OFS 0x098 ++#define GT_PCI1M0LD_OFS 0x0a0 ++#define GT_PCI1M0HD_OFS 0x0a8 ++#define GT_PCI1M1LD_OFS 0x0b0 ++#define GT_PCI1M1HD_OFS 0x0b8 ++ ++#define GT_SCS0LD_OFS 0x400 ++#define GT_SCS0HD_OFS 0x404 ++#define GT_SCS1LD_OFS 0x408 ++#define GT_SCS1HD_OFS 0x40c ++#define GT_SCS2LD_OFS 0x410 ++#define GT_SCS2HD_OFS 0x414 ++#define GT_SCS3LD_OFS 0x418 ++#define GT_SCS3HD_OFS 0x41c ++#define GT_CS0LD_OFS 0x420 ++#define GT_CS0HD_OFS 0x424 ++#define GT_CS1LD_OFS 0x428 ++#define GT_CS1HD_OFS 0x42c ++#define GT_CS2LD_OFS 0x430 ++#define GT_CS2HD_OFS 0x434 ++#define GT_CS3LD_OFS 0x438 ++#define GT_CS3HD_OFS 0x43c ++#define GT_BOOTLD_OFS 0x440 ++#define GT_BOOTHD_OFS 0x444 ++ ++#define GT_PCI0_BS_SCS10_OFS 0Xc08 ++#define GT_PCI0_BS_SCS32_OFS 0xc0c ++#define GT_PCI0_BARE_OFS 0Xc3c ++ ++#define GT_PCI0_TOR_OFS 0xc04 ++ ++#define GT_PCI0_IACK_OFS 0xc34 ++ ++ ++/************************************************************************ ++ * Register encodings ++ ************************************************************************/ ++ ++#define GT_CPU_WR_SHF 16 ++#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) ++#define GT_CPU_WR_BIT GT_CPU_WR_MSK ++#define GT_CPU_WR_DXDXDXDX 0 ++#define GT_CPU_WR_DDDD 1 ++ ++ ++#define GT_CFGADDR_CFGEN_SHF 31 ++#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) ++#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK ++ ++#define GT_CFGADDR_BUSNUM_SHF 16 ++#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) ++ ++#define GT_CFGADDR_DEVNUM_SHF 11 ++#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) ++ ++#define GT_CFGADDR_FUNCNUM_SHF 8 ++#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) ++ ++#define GT_CFGADDR_REGNUM_SHF 2 ++#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) ++ ++ ++#define GT_SDRAM_BM_ORDER_SHF 2 ++#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) ++#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK ++#define GT_SDRAM_BM_ORDER_SUB 1 ++#define GT_SDRAM_BM_ORDER_LIN 0 ++ ++#define GT_SDRAM_BM_RSVD_ALL1 0xFFB ++ ++ ++#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) ++#define GT_SDRAM_ADDRDECODE_ADDR_0 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_1 1 ++#define GT_SDRAM_ADDRDECODE_ADDR_2 2 ++#define GT_SDRAM_ADDRDECODE_ADDR_3 3 ++#define GT_SDRAM_ADDRDECODE_ADDR_4 4 ++#define GT_SDRAM_ADDRDECODE_ADDR_5 5 ++#define GT_SDRAM_ADDRDECODE_ADDR_6 6 ++#define GT_SDRAM_ADDRDECODE_ADDR_7 7 ++ ++ ++#define GT_SDRAM_B0_CASLAT_SHF 0 ++#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) ++#define GT_SDRAM_B0_CASLAT_2 1 ++#define GT_SDRAM_B0_CASLAT_3 2 ++ ++#define GT_SDRAM_B0_FTDIS_SHF 2 ++#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) ++#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK ++ ++#define GT_SDRAM_B0_SRASPRCHG_SHF 3 ++#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) ++#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK ++#define GT_SDRAM_B0_SRASPRCHG_2 0 ++#define GT_SDRAM_B0_SRASPRCHG_3 1 ++ ++#define GT_SDRAM_B0_B0COMPAB_SHF 4 ++#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) ++#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK ++ ++#define GT_SDRAM_B0_64BITINT_SHF 5 ++#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) ++#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK ++#define GT_SDRAM_B0_64BITINT_2 0 ++#define GT_SDRAM_B0_64BITINT_4 1 ++ ++#define GT_SDRAM_B0_BW_SHF 6 ++#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) ++#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK ++#define GT_SDRAM_B0_BW_32 0 ++#define GT_SDRAM_B0_BW_64 1 ++ ++#define GT_SDRAM_B0_BLODD_SHF 7 ++#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) ++#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK ++ ++#define GT_SDRAM_B0_PAR_SHF 8 ++#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) ++#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK ++ ++#define GT_SDRAM_B0_BYPASS_SHF 9 ++#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) ++#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK ++ ++#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 ++#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) ++#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK ++#define GT_SDRAM_B0_SRAS2SCAS_2 0 ++#define GT_SDRAM_B0_SRAS2SCAS_3 1 ++ ++#define GT_SDRAM_B0_SIZE_SHF 11 ++#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) ++#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK ++#define GT_SDRAM_B0_SIZE_16M 0 ++#define GT_SDRAM_B0_SIZE_64M 1 ++ ++#define GT_SDRAM_B0_EXTPAR_SHF 12 ++#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) ++#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK ++ ++#define GT_SDRAM_B0_BLEN_SHF 13 ++#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) ++#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK ++#define GT_SDRAM_B0_BLEN_8 0 ++#define GT_SDRAM_B0_BLEN_4 1 ++ ++ ++#define GT_SDRAM_CFG_REFINT_SHF 0 ++#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) ++ ++#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 ++#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) ++#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK ++ ++#define GT_SDRAM_CFG_RMW_SHF 15 ++#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) ++#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK ++ ++#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 ++#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) ++#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK ++ ++#define GT_SDRAM_CFG_DUPCNTL_SHF 19 ++#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) ++#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK ++ ++#define GT_SDRAM_CFG_DUPBA_SHF 20 ++#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) ++#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT0_SHF 21 ++#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) ++#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT1_SHF 22 ++#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) ++#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK ++ ++#define GT_SDRAM_OPMODE_OP_SHF 0 ++#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) ++#define GT_SDRAM_OPMODE_OP_NORMAL 0 ++#define GT_SDRAM_OPMODE_OP_NOP 1 ++#define GT_SDRAM_OPMODE_OP_PRCHG 2 ++#define GT_SDRAM_OPMODE_OP_MODE 3 ++#define GT_SDRAM_OPMODE_OP_CBR 4 ++ ++ ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 ++#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) ++#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 ++#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) ++#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK ++ ++#define GT_PCI0_BARE_INTIODIS_SHF 3 ++#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) ++#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK ++ ++#define GT_PCI0_BARE_INTMEMDIS_SHF 4 ++#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) ++#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK ++ ++#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 ++#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_CS20DIS_SHF 6 ++#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) ++#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK ++ ++#define GT_PCI0_BARE_SCS32DIS_SHF 7 ++#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) ++#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SCS10DIS_SHF 8 ++#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) ++#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK ++ ++ ++#define GT_INTRCAUSE_MASABORT0_SHF 18 ++#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) ++#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK ++ ++#define GT_INTRCAUSE_TARABORT0_SHF 19 ++#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) ++#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK ++ ++ ++#define GT_PCI0_CFGADDR_REGNUM_SHF 2 ++#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) ++#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 ++#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) ++#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 ++#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) ++#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 ++#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 ++#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK ++ ++ ++/************************************************************************ ++ * Misc ++ ************************************************************************/ ++ ++#define GT_DEF_BASE 0x14000000 ++#define GT_DEF_PCI0_MEM0_BASE 0x12000000 ++#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ ++#define GT_LATTIM_MIN 6 /* Minimum lat */ ++ ++#endif /* #ifndef GT64120_H */ +diff -ruN linux/include/asm-mips/mips-boards/malta.h linux-mips/include/asm-mips/mips-boards/malta.h +--- linux/include/asm-mips/mips-boards/malta.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/malta.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,59 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines of the Malta board specific address-MAP, registers, etc. ++ * ++ */ ++#ifndef _MIPS_MALTA_H ++#define _MIPS_MALTA_H ++ ++#include <asm/addrspace.h> ++#include <asm/io.h> ++ ++/* ++ * Malta I/O ports base address. ++*/ ++#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000)) ++ ++/* ++ * Malta RTC-device indirect register access. ++ */ ++#define MALTA_RTC_ADR_REG 0x70 ++#define MALTA_RTC_DAT_REG 0x71 ++ ++/* ++ * Malta SMSC FDC37M817 Super I/O Controller register. ++ */ ++#define SMSC_CONFIG_REG 0x3f0 ++#define SMSC_DATA_REG 0x3f1 ++ ++#define SMSC_CONFIG_DEVNUM 0x7 ++#define SMSC_CONFIG_ACTIVATE 0x30 ++#define SMSC_CONFIG_ENTER 0x55 ++#define SMSC_CONFIG_EXIT 0xaa ++ ++#define SMSC_CONFIG_DEVNUM_FLOPPY 0 ++ ++#define SMSC_CONFIG_ACTIVATE_ENABLE 1 ++ ++#define SMSC_WRITE(x,a) outb(x,a) ++ ++#endif /* !(_MIPS_MALTA_H) */ +diff -ruN linux/include/asm-mips/mips-boards/maltaint.h linux-mips/include/asm-mips/mips-boards/maltaint.h +--- linux/include/asm-mips/mips-boards/maltaint.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/maltaint.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,33 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines for the Malta interrupt controller. ++ * ++ */ ++#ifndef _MIPS_MALTAINT_H ++#define _MIPS_MALTAINT_H ++ ++/* Number of IRQ supported on hw interrupt 0. */ ++#define MALTAINT_END 16 ++ ++extern void maltaint_init(void); ++ ++#endif /* !(_MIPS_MALTAINT_H) */ +diff -ruN linux/include/asm-mips/mips-boards/piix4.h linux-mips/include/asm-mips/mips-boards/piix4.h +--- linux/include/asm-mips/mips-boards/piix4.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/piix4.h Fri Nov 10 00:12:20 2000 +@@ -0,0 +1,86 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register definitions for Intel PIIX4 South Bridge Device. ++ * ++ */ ++ ++#ifndef PIIX4_H ++#define PIIX4_H ++ ++/************************************************************************ ++ * IO register offsets ++ ************************************************************************/ ++#define PIIX4_ICTLR1_ICW1 0x20 ++#define PIIX4_ICTLR1_ICW2 0x21 ++#define PIIX4_ICTLR1_ICW3 0x21 ++#define PIIX4_ICTLR1_ICW4 0x21 ++#define PIIX4_ICTLR2_ICW1 0xa0 ++#define PIIX4_ICTLR2_ICW2 0xa1 ++#define PIIX4_ICTLR2_ICW3 0xa1 ++#define PIIX4_ICTLR2_ICW4 0xa1 ++#define PIIX4_ICTLR1_OCW1 0x21 ++#define PIIX4_ICTLR1_OCW2 0x20 ++#define PIIX4_ICTLR1_OCW3 0x20 ++#define PIIX4_ICTLR1_OCW4 0x20 ++#define PIIX4_ICTLR2_OCW1 0xa1 ++#define PIIX4_ICTLR2_OCW2 0xa0 ++#define PIIX4_ICTLR2_OCW3 0xa0 ++#define PIIX4_ICTLR2_OCW4 0xa0 ++ ++ ++/************************************************************************ ++ * Register encodings. ++ ************************************************************************/ ++#define PIIX4_OCW2_NSEOI (0x1 << 5) ++#define PIIX4_OCW2_SEOI (0x3 << 5) ++#define PIIX4_OCW2_RNSEOI (0x5 << 5) ++#define PIIX4_OCW2_RAEOIS (0x4 << 5) ++#define PIIX4_OCW2_RAEOIC (0x0 << 5) ++#define PIIX4_OCW2_RSEOI (0x7 << 5) ++#define PIIX4_OCW2_SP (0x6 << 5) ++#define PIIX4_OCW2_NOP (0x2 << 5) ++ ++#define PIIX4_OCW2_SEL (0x0 << 3) ++ ++#define PIIX4_OCW2_ILS_0 0 ++#define PIIX4_OCW2_ILS_1 1 ++#define PIIX4_OCW2_ILS_2 2 ++#define PIIX4_OCW2_ILS_3 3 ++#define PIIX4_OCW2_ILS_4 4 ++#define PIIX4_OCW2_ILS_5 5 ++#define PIIX4_OCW2_ILS_6 6 ++#define PIIX4_OCW2_ILS_7 7 ++#define PIIX4_OCW2_ILS_8 0 ++#define PIIX4_OCW2_ILS_9 1 ++#define PIIX4_OCW2_ILS_10 2 ++#define PIIX4_OCW2_ILS_11 3 ++#define PIIX4_OCW2_ILS_12 4 ++#define PIIX4_OCW2_ILS_13 5 ++#define PIIX4_OCW2_ILS_14 6 ++#define PIIX4_OCW2_ILS_15 7 ++ ++#define PIIX4_OCW3_SEL (0x1 << 3) ++ ++#define PIIX4_OCW3_IRR 0x2 ++#define PIIX4_OCW3_ISR 0x3 ++ ++#endif /* !(PIIX4_H) */ +diff -ruN linux/include/asm-mips/mips-boards/prom.h linux-mips/include/asm-mips/mips-boards/prom.h +--- linux/include/asm-mips/mips-boards/prom.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/prom.h Fri Nov 10 00:12:20 2000 +@@ -0,0 +1,49 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * MIPS boards bootprom interface for the Linux kernel. ++ * ++ */ ++ ++#ifndef _MIPS_PROM_H ++#define _MIPS_PROM_H ++ ++extern char *prom_getcmdline(void); ++extern char *prom_getenv(char *name); ++extern void setup_prom_printf(void); ++extern void prom_printf(char *fmt, ...); ++extern void prom_init_cmdline(void); ++extern void prom_meminit(void); ++extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); ++extern void prom_free_prom_memory (void); ++extern void mips_display_message(const char *str); ++extern void mips_display_word(unsigned int num); ++extern int get_ethernet_addr(char *ethernet_addr); ++ ++/* Memory descriptor management. */ ++#define PROM_MAX_PMEMBLOCKS 32 ++struct prom_pmemblock { ++ unsigned long base; /* Within KSEG0. */ ++ unsigned int size; /* In bytes. */ ++ unsigned int type; /* free or prom memory */ ++}; ++ ++#endif /* !(_MIPS_PROM_H) */ +diff -ruN linux/include/asm-mips/mipsregs.h linux-mips/include/asm-mips/mipsregs.h +--- linux/include/asm-mips/mipsregs.h Sun Jul 9 22:18:15 2000 ++++ linux-mips/include/asm-mips/mipsregs.h Fri Nov 10 00:11:53 2000 +@@ -1,10 +1,10 @@ +-/* $Id: mipsregs.h,v 1.6 1999/07/26 19:42:43 harald Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle ++ * Copyright (C) 1994, 1995, 1996, 1997, 2000 by Ralf Baechle ++ * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + */ + #ifndef __ASM_MIPS_MIPSREGS_H +@@ -184,42 +184,6 @@ + __BUILD_SET_CP0(config,CP0_CONFIG) + + #endif /* defined (_LANGUAGE_ASSEMBLY) */ +- +-/* +- * Inline code for use of the ll and sc instructions +- * +- * FIXME: This instruction is only available on MIPS ISA >=2. +- * Since these operations are only being used for atomic operations +- * the easiest workaround for the R[23]00 is to disable interrupts. +- * This fails for R3000 SMP machines which use that many different +- * technologies as replacement that it is difficult to create even +- * just a hook for for all machines to hook into. The only good +- * thing is that there is currently no R3000 SMP machine on the +- * Linux/MIPS target list ... +- */ +-#define load_linked(addr) \ +-({ \ +- unsigned int __res; \ +- \ +- __asm__ __volatile__( \ +- "ll\t%0,(%1)" \ +- : "=r" (__res) \ +- : "r" ((unsigned long) (addr))); \ +- \ +- __res; \ +-}) +- +-#define store_conditional(addr,value) \ +-({ \ +- int __res; \ +- \ +- __asm__ __volatile__( \ +- "sc\t%0,(%2)" \ +- : "=r" (__res) \ +- : "0" (value), "r" (addr)); \ +- \ +- __res; \ +-}) + + /* + * Bitfields in the R4xx0 cp0 status register +diff -ruN linux/include/asm-mips/pci.h linux-mips/include/asm-mips/pci.h +--- linux/include/asm-mips/pci.h Thu Jun 22 07:17:16 2000 ++++ linux-mips/include/asm-mips/pci.h Fri Nov 10 00:11:55 2000 +@@ -40,7 +40,7 @@ + #include <linux/string.h> + #include <asm/io.h> + +-#ifdef CONFIG_DDB5074 ++#if (defined(CONFIG_DDB5074) || defined(CONFIG_DDB5476)) + #undef PCIBIOS_MIN_IO + #undef PCIBIOS_MIN_MEM + #define PCIBIOS_MIN_IO 0x0100000 +diff -ruN linux/include/asm-mips/pgtable.h linux-mips/include/asm-mips/pgtable.h +--- linux/include/asm-mips/pgtable.h Mon Aug 7 21:02:27 2000 ++++ linux-mips/include/asm-mips/pgtable.h Fri Nov 10 00:11:57 2000 +@@ -3,7 +3,7 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1994 - 1999 by Ralf Baechle at alii ++ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle at alii + * Copyright (C) 1999 Silicon Graphics, Inc. + */ + #ifndef _ASM_PGTABLE_H +@@ -25,6 +25,7 @@ + * - flush_cache_page(mm, vmaddr) flushes a single page + * - flush_cache_range(mm, start, end) flushes a range of pages + * - flush_page_to_ram(page) write back kernel page to ram ++ * - flush_icache_range(start, end) flush a range of instructions + */ + extern void (*_flush_cache_all)(void); + extern void (*_flush_cache_mm)(struct mm_struct *mm); +@@ -33,6 +34,9 @@ + extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); + extern void (*_flush_cache_sigtramp)(unsigned long addr); + extern void (*_flush_page_to_ram)(struct page * page); ++extern void (*_flush_icache_range)(unsigned long start, unsigned long end); ++extern void (*_flush_icache_page)(struct vm_area_struct *vma, ++ struct page *page, unsigned long addr); + + #define flush_dcache_page(page) do { } while (0) + +@@ -43,14 +47,8 @@ + #define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) + #define flush_page_to_ram(page) _flush_page_to_ram(page) + +-#define flush_icache_range(start, end) flush_cache_all() +- +-#define flush_icache_page(vma, page) \ +-do { \ +- unsigned long addr; \ +- addr = (unsigned long) page_address(page); \ +- _flush_cache_page(vma, addr); \ +-} while (0) ++#define flush_icache_range(start, end) _flush_icache_range(start,end) ++#define flush_icache_page(vma, page, addr) _flush_icache_page(vma, page, addr) + + + /* +@@ -303,7 +301,7 @@ + extern inline void pgd_clear(pgd_t *pgdp) { } + + /* +- * Permanent address of a page. On MIPS64 we never have highmem, so this ++ * Permanent address of a page. On MIPS we never have highmem, so this + * is simple. + */ + #define page_address(page) ((page)->virtual) +@@ -390,7 +388,7 @@ + + extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) + { +- return __pte(((physpage & PAGE_MASK) - PAGE_OFFSET) | pgprot_val(pgprot)); ++ return __pte(physpage | pgprot_val(pgprot)); + } + + extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +@@ -640,6 +638,19 @@ + "mtc0 %0, $6\n\t" + ".set pop" + : : "r" (val)); ++} ++ ++extern inline unsigned long get_info(void) ++{ ++ unsigned long val; ++ ++ __asm__( ++ ".set push\n\t" ++ ".set reorder\n\t" ++ "mfc0 %0, $7\n\t" ++ ".set pop" ++ : "=r" (val)); ++ return val; + } + + /* CP0_TAGLO and CP0_TAGHI registers */ +diff -ruN linux/include/asm-mips/resource.h linux-mips/include/asm-mips/resource.h +--- linux/include/asm-mips/resource.h Thu Nov 23 15:51:49 2000 ++++ linux-mips/include/asm-mips/resource.h Fri Nov 10 00:11:59 2000 +@@ -26,13 +26,13 @@ + + #define RLIM_NLIMITS 11 /* Number of limit flavors. */ + ++#ifdef __KERNEL__ ++ + /* + * SuS says limits have to be unsigned. + * Which makes a ton more sense anyway. + */ + #define RLIM_INFINITY 0x7fffffffUL +- +-#ifdef __KERNEL__ + + #define INIT_RLIMITS \ + { \ +diff -ruN linux/include/asm-mips/riscos-syscall.h linux-mips/include/asm-mips/riscos-syscall.h +--- linux/include/asm-mips/riscos-syscall.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/riscos-syscall.h Fri Nov 10 00:12:02 2000 +@@ -0,0 +1,979 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle ++ */ ++#ifndef _ASM_RISCOS_SYSCALL_H ++#define _ASM_RISCOS_SYSCALL_H ++ ++/* ++ * The syscalls 0 - 3999 are reserved for a down to the root syscall ++ * compatibility with RISC/os and IRIX. We'll see how to deal with the ++ * various "real" BSD variants like Ultrix, NetBSD ... ++ */ ++ ++/* ++ * SVR4 syscalls are in the range from 1 to 999 ++ */ ++#define __NR_SVR4 0 ++#define __NR_SVR4_syscall (__NR_SVR4 + 0) ++#define __NR_SVR4_exit (__NR_SVR4 + 1) ++#define __NR_SVR4_fork (__NR_SVR4 + 2) ++#define __NR_SVR4_read (__NR_SVR4 + 3) ++#define __NR_SVR4_write (__NR_SVR4 + 4) ++#define __NR_SVR4_open (__NR_SVR4 + 5) ++#define __NR_SVR4_close (__NR_SVR4 + 6) ++#define __NR_SVR4_wait (__NR_SVR4 + 7) ++#define __NR_SVR4_creat (__NR_SVR4 + 8) ++#define __NR_SVR4_link (__NR_SVR4 + 9) ++#define __NR_SVR4_unlink (__NR_SVR4 + 10) ++#define __NR_SVR4_exec (__NR_SVR4 + 11) ++#define __NR_SVR4_chdir (__NR_SVR4 + 12) ++#define __NR_SVR4_gtime (__NR_SVR4 + 13) ++#define __NR_SVR4_mknod (__NR_SVR4 + 14) ++#define __NR_SVR4_chmod (__NR_SVR4 + 15) ++#define __NR_SVR4_chown (__NR_SVR4 + 16) ++#define __NR_SVR4_sbreak (__NR_SVR4 + 17) ++#define __NR_SVR4_stat (__NR_SVR4 + 18) ++#define __NR_SVR4_lseek (__NR_SVR4 + 19) ++#define __NR_SVR4_getpid (__NR_SVR4 + 20) ++#define __NR_SVR4_mount (__NR_SVR4 + 21) ++#define __NR_SVR4_umount (__NR_SVR4 + 22) ++#define __NR_SVR4_setuid (__NR_SVR4 + 23) ++#define __NR_SVR4_getuid (__NR_SVR4 + 24) ++#define __NR_SVR4_stime (__NR_SVR4 + 25) ++#define __NR_SVR4_ptrace (__NR_SVR4 + 26) ++#define __NR_SVR4_alarm (__NR_SVR4 + 27) ++#define __NR_SVR4_fstat (__NR_SVR4 + 28) ++#define __NR_SVR4_pause (__NR_SVR4 + 29) ++#define __NR_SVR4_utime (__NR_SVR4 + 30) ++#define __NR_SVR4_stty (__NR_SVR4 + 31) ++#define __NR_SVR4_gtty (__NR_SVR4 + 32) ++#define __NR_SVR4_access (__NR_SVR4 + 33) ++#define __NR_SVR4_nice (__NR_SVR4 + 34) ++#define __NR_SVR4_statfs (__NR_SVR4 + 35) ++#define __NR_SVR4_sync (__NR_SVR4 + 36) ++#define __NR_SVR4_kill (__NR_SVR4 + 37) ++#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) ++#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) ++#define __NR_SVR4_cxenix (__NR_SVR4 + 40) ++#define __NR_SVR4_dup (__NR_SVR4 + 41) ++#define __NR_SVR4_pipe (__NR_SVR4 + 42) ++#define __NR_SVR4_times (__NR_SVR4 + 43) ++#define __NR_SVR4_profil (__NR_SVR4 + 44) ++#define __NR_SVR4_plock (__NR_SVR4 + 45) ++#define __NR_SVR4_setgid (__NR_SVR4 + 46) ++#define __NR_SVR4_getgid (__NR_SVR4 + 47) ++#define __NR_SVR4_sig (__NR_SVR4 + 48) ++#define __NR_SVR4_msgsys (__NR_SVR4 + 49) ++#define __NR_SVR4_sysmips (__NR_SVR4 + 50) ++#define __NR_SVR4_sysacct (__NR_SVR4 + 51) ++#define __NR_SVR4_shmsys (__NR_SVR4 + 52) ++#define __NR_SVR4_semsys (__NR_SVR4 + 53) ++#define __NR_SVR4_ioctl (__NR_SVR4 + 54) ++#define __NR_SVR4_uadmin (__NR_SVR4 + 55) ++#define __NR_SVR4_exch (__NR_SVR4 + 56) ++#define __NR_SVR4_utssys (__NR_SVR4 + 57) ++#define __NR_SVR4_fsync (__NR_SVR4 + 58) ++#define __NR_SVR4_exece (__NR_SVR4 + 59) ++#define __NR_SVR4_umask (__NR_SVR4 + 60) ++#define __NR_SVR4_chroot (__NR_SVR4 + 61) ++#define __NR_SVR4_fcntl (__NR_SVR4 + 62) ++#define __NR_SVR4_ulimit (__NR_SVR4 + 63) ++#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) ++#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) ++#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) ++#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) ++#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) ++#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) ++#define __NR_SVR4_advfs (__NR_SVR4 + 70) ++#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) ++#define __NR_SVR4_unused1 (__NR_SVR4 + 72) ++#define __NR_SVR4_unused2 (__NR_SVR4 + 73) ++#define __NR_SVR4_rfstart (__NR_SVR4 + 74) ++#define __NR_SVR4_unused3 (__NR_SVR4 + 75) ++#define __NR_SVR4_rdebug (__NR_SVR4 + 76) ++#define __NR_SVR4_rfstop (__NR_SVR4 + 77) ++#define __NR_SVR4_rfsys (__NR_SVR4 + 78) ++#define __NR_SVR4_rmdir (__NR_SVR4 + 79) ++#define __NR_SVR4_mkdir (__NR_SVR4 + 80) ++#define __NR_SVR4_getdents (__NR_SVR4 + 81) ++#define __NR_SVR4_libattach (__NR_SVR4 + 82) ++#define __NR_SVR4_libdetach (__NR_SVR4 + 83) ++#define __NR_SVR4_sysfs (__NR_SVR4 + 84) ++#define __NR_SVR4_getmsg (__NR_SVR4 + 85) ++#define __NR_SVR4_putmsg (__NR_SVR4 + 86) ++#define __NR_SVR4_poll (__NR_SVR4 + 87) ++#define __NR_SVR4_lstat (__NR_SVR4 + 88) ++#define __NR_SVR4_symlink (__NR_SVR4 + 89) ++#define __NR_SVR4_readlink (__NR_SVR4 + 90) ++#define __NR_SVR4_setgroups (__NR_SVR4 + 91) ++#define __NR_SVR4_getgroups (__NR_SVR4 + 92) ++#define __NR_SVR4_fchmod (__NR_SVR4 + 93) ++#define __NR_SVR4_fchown (__NR_SVR4 + 94) ++#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) ++#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) ++#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) ++#define __NR_SVR4_sigaction (__NR_SVR4 + 98) ++#define __NR_SVR4_sigpending (__NR_SVR4 + 99) ++#define __NR_SVR4_setcontext (__NR_SVR4 + 100) ++#define __NR_SVR4_evsys (__NR_SVR4 + 101) ++#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) ++#define __NR_SVR4_statvfs (__NR_SVR4 + 103) ++#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) ++#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) ++#define __NR_SVR4_nfssys (__NR_SVR4 + 106) ++#define __NR_SVR4_waitid (__NR_SVR4 + 107) ++#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) ++#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) ++#define __NR_SVR4_acancel (__NR_SVR4 + 110) ++#define __NR_SVR4_async (__NR_SVR4 + 111) ++#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) ++#define __NR_SVR4_pathconf (__NR_SVR4 + 113) ++#define __NR_SVR4_mincore (__NR_SVR4 + 114) ++#define __NR_SVR4_mmap (__NR_SVR4 + 115) ++#define __NR_SVR4_mprotect (__NR_SVR4 + 116) ++#define __NR_SVR4_munmap (__NR_SVR4 + 117) ++#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) ++#define __NR_SVR4_vfork (__NR_SVR4 + 119) ++#define __NR_SVR4_fchdir (__NR_SVR4 + 120) ++#define __NR_SVR4_readv (__NR_SVR4 + 121) ++#define __NR_SVR4_writev (__NR_SVR4 + 122) ++#define __NR_SVR4_xstat (__NR_SVR4 + 123) ++#define __NR_SVR4_lxstat (__NR_SVR4 + 124) ++#define __NR_SVR4_fxstat (__NR_SVR4 + 125) ++#define __NR_SVR4_xmknod (__NR_SVR4 + 126) ++#define __NR_SVR4_clocal (__NR_SVR4 + 127) ++#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) ++#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) ++#define __NR_SVR4_lchown (__NR_SVR4 + 130) ++#define __NR_SVR4_memcntl (__NR_SVR4 + 131) ++#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) ++#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) ++#define __NR_SVR4_rename (__NR_SVR4 + 134) ++#define __NR_SVR4_nuname (__NR_SVR4 + 135) ++#define __NR_SVR4_setegid (__NR_SVR4 + 136) ++#define __NR_SVR4_sysconf (__NR_SVR4 + 137) ++#define __NR_SVR4_adjtime (__NR_SVR4 + 138) ++#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) ++#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) ++#define __NR_SVR4_seteuid (__NR_SVR4 + 141) ++#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) ++#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) ++#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) ++#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) ++#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) ++#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) ++#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) ++#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) ++#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) ++#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) ++#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) ++#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) ++#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) ++#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) ++#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) ++#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) ++#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) ++#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) ++#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) ++#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) ++#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) ++#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) ++#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) ++#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) ++#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) ++#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) ++#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) ++#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) ++#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) ++#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) ++#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) ++#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) ++#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) ++#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) ++#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) ++#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) ++#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) ++#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) ++#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) ++#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) ++#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) ++#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) ++#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) ++#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) ++#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) ++#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) ++#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) ++#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) ++#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) ++#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) ++#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) ++#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) ++#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) ++#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) ++#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) ++#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) ++#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) ++#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) ++#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) ++#define __NR_SVR4_aread (__NR_SVR4 + 201) ++#define __NR_SVR4_awrite (__NR_SVR4 + 202) ++#define __NR_SVR4_listio (__NR_SVR4 + 203) ++#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) ++#define __NR_SVR4_astatus (__NR_SVR4 + 205) ++#define __NR_SVR4_await (__NR_SVR4 + 206) ++#define __NR_SVR4_areadv (__NR_SVR4 + 207) ++#define __NR_SVR4_awritev (__NR_SVR4 + 208) ++#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) ++#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) ++#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) ++#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) ++#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) ++#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) ++#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) ++#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) ++#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) ++#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) ++#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) ++#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) ++#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) ++#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) ++#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) ++#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) ++#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) ++#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) ++#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) ++#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) ++#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) ++#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) ++#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) ++#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) ++#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) ++#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) ++#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) ++#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) ++#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) ++#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) ++#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) ++#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) ++ ++/* ++ * SYS V syscalls are in the range from 1000 to 1999 ++ */ ++#define __NR_SYSV 1000 ++#define __NR_SYSV_syscall (__NR_SYSV + 0) ++#define __NR_SYSV_exit (__NR_SYSV + 1) ++#define __NR_SYSV_fork (__NR_SYSV + 2) ++#define __NR_SYSV_read (__NR_SYSV + 3) ++#define __NR_SYSV_write (__NR_SYSV + 4) ++#define __NR_SYSV_open (__NR_SYSV + 5) ++#define __NR_SYSV_close (__NR_SYSV + 6) ++#define __NR_SYSV_wait (__NR_SYSV + 7) ++#define __NR_SYSV_creat (__NR_SYSV + 8) ++#define __NR_SYSV_link (__NR_SYSV + 9) ++#define __NR_SYSV_unlink (__NR_SYSV + 10) ++#define __NR_SYSV_execv (__NR_SYSV + 11) ++#define __NR_SYSV_chdir (__NR_SYSV + 12) ++#define __NR_SYSV_time (__NR_SYSV + 13) ++#define __NR_SYSV_mknod (__NR_SYSV + 14) ++#define __NR_SYSV_chmod (__NR_SYSV + 15) ++#define __NR_SYSV_chown (__NR_SYSV + 16) ++#define __NR_SYSV_brk (__NR_SYSV + 17) ++#define __NR_SYSV_stat (__NR_SYSV + 18) ++#define __NR_SYSV_lseek (__NR_SYSV + 19) ++#define __NR_SYSV_getpid (__NR_SYSV + 20) ++#define __NR_SYSV_mount (__NR_SYSV + 21) ++#define __NR_SYSV_umount (__NR_SYSV + 22) ++#define __NR_SYSV_setuid (__NR_SYSV + 23) ++#define __NR_SYSV_getuid (__NR_SYSV + 24) ++#define __NR_SYSV_stime (__NR_SYSV + 25) ++#define __NR_SYSV_ptrace (__NR_SYSV + 26) ++#define __NR_SYSV_alarm (__NR_SYSV + 27) ++#define __NR_SYSV_fstat (__NR_SYSV + 28) ++#define __NR_SYSV_pause (__NR_SYSV + 29) ++#define __NR_SYSV_utime (__NR_SYSV + 30) ++#define __NR_SYSV_stty (__NR_SYSV + 31) ++#define __NR_SYSV_gtty (__NR_SYSV + 32) ++#define __NR_SYSV_access (__NR_SYSV + 33) ++#define __NR_SYSV_nice (__NR_SYSV + 34) ++#define __NR_SYSV_statfs (__NR_SYSV + 35) ++#define __NR_SYSV_sync (__NR_SYSV + 36) ++#define __NR_SYSV_kill (__NR_SYSV + 37) ++#define __NR_SYSV_fstatfs (__NR_SYSV + 38) ++#define __NR_SYSV_setpgrp (__NR_SYSV + 39) ++#define __NR_SYSV_syssgi (__NR_SYSV + 40) ++#define __NR_SYSV_dup (__NR_SYSV + 41) ++#define __NR_SYSV_pipe (__NR_SYSV + 42) ++#define __NR_SYSV_times (__NR_SYSV + 43) ++#define __NR_SYSV_profil (__NR_SYSV + 44) ++#define __NR_SYSV_plock (__NR_SYSV + 45) ++#define __NR_SYSV_setgid (__NR_SYSV + 46) ++#define __NR_SYSV_getgid (__NR_SYSV + 47) ++#define __NR_SYSV_sig (__NR_SYSV + 48) ++#define __NR_SYSV_msgsys (__NR_SYSV + 49) ++#define __NR_SYSV_sysmips (__NR_SYSV + 50) ++#define __NR_SYSV_acct (__NR_SYSV + 51) ++#define __NR_SYSV_shmsys (__NR_SYSV + 52) ++#define __NR_SYSV_semsys (__NR_SYSV + 53) ++#define __NR_SYSV_ioctl (__NR_SYSV + 54) ++#define __NR_SYSV_uadmin (__NR_SYSV + 55) ++#define __NR_SYSV_sysmp (__NR_SYSV + 56) ++#define __NR_SYSV_utssys (__NR_SYSV + 57) ++#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) ++#define __NR_SYSV_execve (__NR_SYSV + 59) ++#define __NR_SYSV_umask (__NR_SYSV + 60) ++#define __NR_SYSV_chroot (__NR_SYSV + 61) ++#define __NR_SYSV_fcntl (__NR_SYSV + 62) ++#define __NR_SYSV_ulimit (__NR_SYSV + 63) ++#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) ++#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) ++#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) ++#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) ++#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) ++#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) ++#define __NR_SYSV_advfs (__NR_SYSV + 70) ++#define __NR_SYSV_unadvfs (__NR_SYSV + 71) ++#define __NR_SYSV_rmount (__NR_SYSV + 72) ++#define __NR_SYSV_rumount (__NR_SYSV + 73) ++#define __NR_SYSV_rfstart (__NR_SYSV + 74) ++#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) ++#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) ++#define __NR_SYSV_nanosleep (__NR_SYSV + 77) ++#define __NR_SYSV_lseek64 (__NR_SYSV + 78) ++#define __NR_SYSV_rmdir (__NR_SYSV + 79) ++#define __NR_SYSV_mkdir (__NR_SYSV + 80) ++#define __NR_SYSV_getdents (__NR_SYSV + 81) ++#define __NR_SYSV_sginap (__NR_SYSV + 82) ++#define __NR_SYSV_sgikopt (__NR_SYSV + 83) ++#define __NR_SYSV_sysfs (__NR_SYSV + 84) ++#define __NR_SYSV_getmsg (__NR_SYSV + 85) ++#define __NR_SYSV_putmsg (__NR_SYSV + 86) ++#define __NR_SYSV_poll (__NR_SYSV + 87) ++#define __NR_SYSV_sigreturn (__NR_SYSV + 88) ++#define __NR_SYSV_accept (__NR_SYSV + 89) ++#define __NR_SYSV_bind (__NR_SYSV + 90) ++#define __NR_SYSV_connect (__NR_SYSV + 91) ++#define __NR_SYSV_gethostid (__NR_SYSV + 92) ++#define __NR_SYSV_getpeername (__NR_SYSV + 93) ++#define __NR_SYSV_getsockname (__NR_SYSV + 94) ++#define __NR_SYSV_getsockopt (__NR_SYSV + 95) ++#define __NR_SYSV_listen (__NR_SYSV + 96) ++#define __NR_SYSV_recv (__NR_SYSV + 97) ++#define __NR_SYSV_recvfrom (__NR_SYSV + 98) ++#define __NR_SYSV_recvmsg (__NR_SYSV + 99) ++#define __NR_SYSV_select (__NR_SYSV + 100) ++#define __NR_SYSV_send (__NR_SYSV + 101) ++#define __NR_SYSV_sendmsg (__NR_SYSV + 102) ++#define __NR_SYSV_sendto (__NR_SYSV + 103) ++#define __NR_SYSV_sethostid (__NR_SYSV + 104) ++#define __NR_SYSV_setsockopt (__NR_SYSV + 105) ++#define __NR_SYSV_shutdown (__NR_SYSV + 106) ++#define __NR_SYSV_socket (__NR_SYSV + 107) ++#define __NR_SYSV_gethostname (__NR_SYSV + 108) ++#define __NR_SYSV_sethostname (__NR_SYSV + 109) ++#define __NR_SYSV_getdomainname (__NR_SYSV + 110) ++#define __NR_SYSV_setdomainname (__NR_SYSV + 111) ++#define __NR_SYSV_truncate (__NR_SYSV + 112) ++#define __NR_SYSV_ftruncate (__NR_SYSV + 113) ++#define __NR_SYSV_rename (__NR_SYSV + 114) ++#define __NR_SYSV_symlink (__NR_SYSV + 115) ++#define __NR_SYSV_readlink (__NR_SYSV + 116) ++#define __NR_SYSV_lstat (__NR_SYSV + 117) ++#define __NR_SYSV_nfsmount (__NR_SYSV + 118) ++#define __NR_SYSV_nfssvc (__NR_SYSV + 119) ++#define __NR_SYSV_getfh (__NR_SYSV + 120) ++#define __NR_SYSV_async_daemon (__NR_SYSV + 121) ++#define __NR_SYSV_exportfs (__NR_SYSV + 122) ++#define __NR_SYSV_setregid (__NR_SYSV + 123) ++#define __NR_SYSV_setreuid (__NR_SYSV + 124) ++#define __NR_SYSV_getitimer (__NR_SYSV + 125) ++#define __NR_SYSV_setitimer (__NR_SYSV + 126) ++#define __NR_SYSV_adjtime (__NR_SYSV + 127) ++#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) ++#define __NR_SYSV_sproc (__NR_SYSV + 129) ++#define __NR_SYSV_prctl (__NR_SYSV + 130) ++#define __NR_SYSV_procblk (__NR_SYSV + 131) ++#define __NR_SYSV_sprocsp (__NR_SYSV + 132) ++#define __NR_SYSV_sgigsc (__NR_SYSV + 133) ++#define __NR_SYSV_mmap (__NR_SYSV + 134) ++#define __NR_SYSV_munmap (__NR_SYSV + 135) ++#define __NR_SYSV_mprotect (__NR_SYSV + 136) ++#define __NR_SYSV_msync (__NR_SYSV + 137) ++#define __NR_SYSV_madvise (__NR_SYSV + 138) ++#define __NR_SYSV_pagelock (__NR_SYSV + 139) ++#define __NR_SYSV_getpagesize (__NR_SYSV + 140) ++#define __NR_SYSV_quotactl (__NR_SYSV + 141) ++#define __NR_SYSV_libdetach (__NR_SYSV + 142) ++#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) ++#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) ++#define __NR_SYSV_vhangup (__NR_SYSV + 145) ++#define __NR_SYSV_fsync (__NR_SYSV + 146) ++#define __NR_SYSV_fchdir (__NR_SYSV + 147) ++#define __NR_SYSV_getrlimit (__NR_SYSV + 148) ++#define __NR_SYSV_setrlimit (__NR_SYSV + 149) ++#define __NR_SYSV_cacheflush (__NR_SYSV + 150) ++#define __NR_SYSV_cachectl (__NR_SYSV + 151) ++#define __NR_SYSV_fchown (__NR_SYSV + 152) ++#define __NR_SYSV_fchmod (__NR_SYSV + 153) ++#define __NR_SYSV_wait3 (__NR_SYSV + 154) ++#define __NR_SYSV_socketpair (__NR_SYSV + 155) ++#define __NR_SYSV_sysinfo (__NR_SYSV + 156) ++#define __NR_SYSV_nuname (__NR_SYSV + 157) ++#define __NR_SYSV_xstat (__NR_SYSV + 158) ++#define __NR_SYSV_lxstat (__NR_SYSV + 159) ++#define __NR_SYSV_fxstat (__NR_SYSV + 160) ++#define __NR_SYSV_xmknod (__NR_SYSV + 161) ++#define __NR_SYSV_ksigaction (__NR_SYSV + 162) ++#define __NR_SYSV_sigpending (__NR_SYSV + 163) ++#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) ++#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) ++#define __NR_SYSV_sigpoll (__NR_SYSV + 166) ++#define __NR_SYSV_swapctl (__NR_SYSV + 167) ++#define __NR_SYSV_getcontext (__NR_SYSV + 168) ++#define __NR_SYSV_setcontext (__NR_SYSV + 169) ++#define __NR_SYSV_waitsys (__NR_SYSV + 170) ++#define __NR_SYSV_sigstack (__NR_SYSV + 171) ++#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) ++#define __NR_SYSV_sigsendset (__NR_SYSV + 173) ++#define __NR_SYSV_statvfs (__NR_SYSV + 174) ++#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) ++#define __NR_SYSV_getpmsg (__NR_SYSV + 176) ++#define __NR_SYSV_putpmsg (__NR_SYSV + 177) ++#define __NR_SYSV_lchown (__NR_SYSV + 178) ++#define __NR_SYSV_priocntl (__NR_SYSV + 179) ++#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) ++#define __NR_SYSV_readv (__NR_SYSV + 181) ++#define __NR_SYSV_writev (__NR_SYSV + 182) ++#define __NR_SYSV_truncate64 (__NR_SYSV + 183) ++#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) ++#define __NR_SYSV_mmap64 (__NR_SYSV + 185) ++#define __NR_SYSV_dmi (__NR_SYSV + 186) ++#define __NR_SYSV_pread (__NR_SYSV + 187) ++#define __NR_SYSV_pwrite (__NR_SYSV + 188) ++ ++/* ++ * BSD 4.3 syscalls are in the range from 2000 to 2999 ++ */ ++#define __NR_BSD43 2000 ++#define __NR_BSD43_syscall (__NR_BSD43 + 0) ++#define __NR_BSD43_exit (__NR_BSD43 + 1) ++#define __NR_BSD43_fork (__NR_BSD43 + 2) ++#define __NR_BSD43_read (__NR_BSD43 + 3) ++#define __NR_BSD43_write (__NR_BSD43 + 4) ++#define __NR_BSD43_open (__NR_BSD43 + 5) ++#define __NR_BSD43_close (__NR_BSD43 + 6) ++#define __NR_BSD43_wait (__NR_BSD43 + 7) ++#define __NR_BSD43_creat (__NR_BSD43 + 8) ++#define __NR_BSD43_link (__NR_BSD43 + 9) ++#define __NR_BSD43_unlink (__NR_BSD43 + 10) ++#define __NR_BSD43_exec (__NR_BSD43 + 11) ++#define __NR_BSD43_chdir (__NR_BSD43 + 12) ++#define __NR_BSD43_time (__NR_BSD43 + 13) ++#define __NR_BSD43_mknod (__NR_BSD43 + 14) ++#define __NR_BSD43_chmod (__NR_BSD43 + 15) ++#define __NR_BSD43_chown (__NR_BSD43 + 16) ++#define __NR_BSD43_sbreak (__NR_BSD43 + 17) ++#define __NR_BSD43_oldstat (__NR_BSD43 + 18) ++#define __NR_BSD43_lseek (__NR_BSD43 + 19) ++#define __NR_BSD43_getpid (__NR_BSD43 + 20) ++#define __NR_BSD43_oldmount (__NR_BSD43 + 21) ++#define __NR_BSD43_umount (__NR_BSD43 + 22) ++#define __NR_BSD43_setuid (__NR_BSD43 + 23) ++#define __NR_BSD43_getuid (__NR_BSD43 + 24) ++#define __NR_BSD43_stime (__NR_BSD43 + 25) ++#define __NR_BSD43_ptrace (__NR_BSD43 + 26) ++#define __NR_BSD43_alarm (__NR_BSD43 + 27) ++#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) ++#define __NR_BSD43_pause (__NR_BSD43 + 29) ++#define __NR_BSD43_utime (__NR_BSD43 + 30) ++#define __NR_BSD43_stty (__NR_BSD43 + 31) ++#define __NR_BSD43_gtty (__NR_BSD43 + 32) ++#define __NR_BSD43_access (__NR_BSD43 + 33) ++#define __NR_BSD43_nice (__NR_BSD43 + 34) ++#define __NR_BSD43_ftime (__NR_BSD43 + 35) ++#define __NR_BSD43_sync (__NR_BSD43 + 36) ++#define __NR_BSD43_kill (__NR_BSD43 + 37) ++#define __NR_BSD43_stat (__NR_BSD43 + 38) ++#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) ++#define __NR_BSD43_lstat (__NR_BSD43 + 40) ++#define __NR_BSD43_dup (__NR_BSD43 + 41) ++#define __NR_BSD43_pipe (__NR_BSD43 + 42) ++#define __NR_BSD43_times (__NR_BSD43 + 43) ++#define __NR_BSD43_profil (__NR_BSD43 + 44) ++#define __NR_BSD43_msgsys (__NR_BSD43 + 45) ++#define __NR_BSD43_setgid (__NR_BSD43 + 46) ++#define __NR_BSD43_getgid (__NR_BSD43 + 47) ++#define __NR_BSD43_ssig (__NR_BSD43 + 48) ++#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) ++#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) ++#define __NR_BSD43_sysacct (__NR_BSD43 + 51) ++#define __NR_BSD43_phys (__NR_BSD43 + 52) ++#define __NR_BSD43_lock (__NR_BSD43 + 53) ++#define __NR_BSD43_ioctl (__NR_BSD43 + 54) ++#define __NR_BSD43_reboot (__NR_BSD43 + 55) ++#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) ++#define __NR_BSD43_symlink (__NR_BSD43 + 57) ++#define __NR_BSD43_readlink (__NR_BSD43 + 58) ++#define __NR_BSD43_execve (__NR_BSD43 + 59) ++#define __NR_BSD43_umask (__NR_BSD43 + 60) ++#define __NR_BSD43_chroot (__NR_BSD43 + 61) ++#define __NR_BSD43_fstat (__NR_BSD43 + 62) ++#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) ++#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) ++#define __NR_BSD43_mremap (__NR_BSD43 + 65) ++#define __NR_BSD43_vfork (__NR_BSD43 + 66) ++#define __NR_BSD43_vread (__NR_BSD43 + 67) ++#define __NR_BSD43_vwrite (__NR_BSD43 + 68) ++#define __NR_BSD43_sbrk (__NR_BSD43 + 69) ++#define __NR_BSD43_sstk (__NR_BSD43 + 70) ++#define __NR_BSD43_mmap (__NR_BSD43 + 71) ++#define __NR_BSD43_vadvise (__NR_BSD43 + 72) ++#define __NR_BSD43_munmap (__NR_BSD43 + 73) ++#define __NR_BSD43_mprotect (__NR_BSD43 + 74) ++#define __NR_BSD43_madvise (__NR_BSD43 + 75) ++#define __NR_BSD43_vhangup (__NR_BSD43 + 76) ++#define __NR_BSD43_vlimit (__NR_BSD43 + 77) ++#define __NR_BSD43_mincore (__NR_BSD43 + 78) ++#define __NR_BSD43_getgroups (__NR_BSD43 + 79) ++#define __NR_BSD43_setgroups (__NR_BSD43 + 80) ++#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) ++#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) ++#define __NR_BSD43_setitimer (__NR_BSD43 + 83) ++#define __NR_BSD43_wait3 (__NR_BSD43 + 84) ++#define __NR_BSD43_swapon (__NR_BSD43 + 85) ++#define __NR_BSD43_getitimer (__NR_BSD43 + 86) ++#define __NR_BSD43_gethostname (__NR_BSD43 + 87) ++#define __NR_BSD43_sethostname (__NR_BSD43 + 88) ++#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) ++#define __NR_BSD43_dup2 (__NR_BSD43 + 90) ++#define __NR_BSD43_getdopt (__NR_BSD43 + 91) ++#define __NR_BSD43_fcntl (__NR_BSD43 + 92) ++#define __NR_BSD43_select (__NR_BSD43 + 93) ++#define __NR_BSD43_setdopt (__NR_BSD43 + 94) ++#define __NR_BSD43_fsync (__NR_BSD43 + 95) ++#define __NR_BSD43_setpriority (__NR_BSD43 + 96) ++#define __NR_BSD43_socket (__NR_BSD43 + 97) ++#define __NR_BSD43_connect (__NR_BSD43 + 98) ++#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) ++#define __NR_BSD43_getpriority (__NR_BSD43 + 100) ++#define __NR_BSD43_send (__NR_BSD43 + 101) ++#define __NR_BSD43_recv (__NR_BSD43 + 102) ++#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) ++#define __NR_BSD43_bind (__NR_BSD43 + 104) ++#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) ++#define __NR_BSD43_listen (__NR_BSD43 + 106) ++#define __NR_BSD43_vtimes (__NR_BSD43 + 107) ++#define __NR_BSD43_sigvec (__NR_BSD43 + 108) ++#define __NR_BSD43_sigblock (__NR_BSD43 + 109) ++#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) ++#define __NR_BSD43_sigpause (__NR_BSD43 + 111) ++#define __NR_BSD43_sigstack (__NR_BSD43 + 112) ++#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) ++#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) ++#define __NR_BSD43_vtrace (__NR_BSD43 + 115) ++#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) ++#define __NR_BSD43_getrusage (__NR_BSD43 + 117) ++#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) ++#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) ++#define __NR_BSD43_readv (__NR_BSD43 + 120) ++#define __NR_BSD43_writev (__NR_BSD43 + 121) ++#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) ++#define __NR_BSD43_fchown (__NR_BSD43 + 123) ++#define __NR_BSD43_fchmod (__NR_BSD43 + 124) ++#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) ++#define __NR_BSD43_setreuid (__NR_BSD43 + 126) ++#define __NR_BSD43_setregid (__NR_BSD43 + 127) ++#define __NR_BSD43_rename (__NR_BSD43 + 128) ++#define __NR_BSD43_truncate (__NR_BSD43 + 129) ++#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) ++#define __NR_BSD43_flock (__NR_BSD43 + 131) ++#define __NR_BSD43_semsys (__NR_BSD43 + 132) ++#define __NR_BSD43_sendto (__NR_BSD43 + 133) ++#define __NR_BSD43_shutdown (__NR_BSD43 + 134) ++#define __NR_BSD43_socketpair (__NR_BSD43 + 135) ++#define __NR_BSD43_mkdir (__NR_BSD43 + 136) ++#define __NR_BSD43_rmdir (__NR_BSD43 + 137) ++#define __NR_BSD43_utimes (__NR_BSD43 + 138) ++#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) ++#define __NR_BSD43_adjtime (__NR_BSD43 + 140) ++#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) ++#define __NR_BSD43_gethostid (__NR_BSD43 + 142) ++#define __NR_BSD43_sethostid (__NR_BSD43 + 143) ++#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) ++#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) ++#define __NR_BSD43_killpg (__NR_BSD43 + 146) ++#define __NR_BSD43_shmsys (__NR_BSD43 + 147) ++#define __NR_BSD43_quota (__NR_BSD43 + 148) ++#define __NR_BSD43_qquota (__NR_BSD43 + 149) ++#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) ++#define __NR_BSD43_sysmips (__NR_BSD43 + 151) ++#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) ++#define __NR_BSD43_cachectl (__NR_BSD43 + 153) ++#define __NR_BSD43_debug (__NR_BSD43 + 154) ++#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) ++#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) ++#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) ++#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) ++#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) ++#define __NR_BSD43_statfs (__NR_BSD43 + 160) ++#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) ++#define __NR_BSD43_unmount (__NR_BSD43 + 162) ++#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) ++#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) ++#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) ++#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) ++#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) ++#define __NR_BSD43_quotactl (__NR_BSD43 + 168) ++#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) ++#define __NR_BSD43_smount (__NR_BSD43 + 170) ++#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) ++#define __NR_BSD43_exportfs (__NR_BSD43 + 172) ++#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) ++#define __NR_BSD43_libattach (__NR_BSD43 + 174) ++#define __NR_BSD43_libdetach (__NR_BSD43 + 175) ++#define __NR_BSD43_accept (__NR_BSD43 + 176) ++#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) ++#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) ++#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) ++#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) ++#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) ++#define __NR_BSD43_getpeername (__NR_BSD43 + 182) ++#define __NR_BSD43_getsockname (__NR_BSD43 + 183) ++#define __NR_BSD43_aread (__NR_BSD43 + 184) ++#define __NR_BSD43_awrite (__NR_BSD43 + 185) ++#define __NR_BSD43_listio (__NR_BSD43 + 186) ++#define __NR_BSD43_acancel (__NR_BSD43 + 187) ++#define __NR_BSD43_astatus (__NR_BSD43 + 188) ++#define __NR_BSD43_await (__NR_BSD43 + 189) ++#define __NR_BSD43_areadv (__NR_BSD43 + 190) ++#define __NR_BSD43_awritev (__NR_BSD43 + 191) ++ ++/* ++ * POSIX syscalls are in the range from 3000 to 3999 ++ */ ++#define __NR_POSIX 3000 ++#define __NR_POSIX_syscall (__NR_POSIX + 0) ++#define __NR_POSIX_exit (__NR_POSIX + 1) ++#define __NR_POSIX_fork (__NR_POSIX + 2) ++#define __NR_POSIX_read (__NR_POSIX + 3) ++#define __NR_POSIX_write (__NR_POSIX + 4) ++#define __NR_POSIX_open (__NR_POSIX + 5) ++#define __NR_POSIX_close (__NR_POSIX + 6) ++#define __NR_POSIX_wait (__NR_POSIX + 7) ++#define __NR_POSIX_creat (__NR_POSIX + 8) ++#define __NR_POSIX_link (__NR_POSIX + 9) ++#define __NR_POSIX_unlink (__NR_POSIX + 10) ++#define __NR_POSIX_exec (__NR_POSIX + 11) ++#define __NR_POSIX_chdir (__NR_POSIX + 12) ++#define __NR_POSIX_gtime (__NR_POSIX + 13) ++#define __NR_POSIX_mknod (__NR_POSIX + 14) ++#define __NR_POSIX_chmod (__NR_POSIX + 15) ++#define __NR_POSIX_chown (__NR_POSIX + 16) ++#define __NR_POSIX_sbreak (__NR_POSIX + 17) ++#define __NR_POSIX_stat (__NR_POSIX + 18) ++#define __NR_POSIX_lseek (__NR_POSIX + 19) ++#define __NR_POSIX_getpid (__NR_POSIX + 20) ++#define __NR_POSIX_mount (__NR_POSIX + 21) ++#define __NR_POSIX_umount (__NR_POSIX + 22) ++#define __NR_POSIX_setuid (__NR_POSIX + 23) ++#define __NR_POSIX_getuid (__NR_POSIX + 24) ++#define __NR_POSIX_stime (__NR_POSIX + 25) ++#define __NR_POSIX_ptrace (__NR_POSIX + 26) ++#define __NR_POSIX_alarm (__NR_POSIX + 27) ++#define __NR_POSIX_fstat (__NR_POSIX + 28) ++#define __NR_POSIX_pause (__NR_POSIX + 29) ++#define __NR_POSIX_utime (__NR_POSIX + 30) ++#define __NR_POSIX_stty (__NR_POSIX + 31) ++#define __NR_POSIX_gtty (__NR_POSIX + 32) ++#define __NR_POSIX_access (__NR_POSIX + 33) ++#define __NR_POSIX_nice (__NR_POSIX + 34) ++#define __NR_POSIX_statfs (__NR_POSIX + 35) ++#define __NR_POSIX_sync (__NR_POSIX + 36) ++#define __NR_POSIX_kill (__NR_POSIX + 37) ++#define __NR_POSIX_fstatfs (__NR_POSIX + 38) ++#define __NR_POSIX_getpgrp (__NR_POSIX + 39) ++#define __NR_POSIX_syssgi (__NR_POSIX + 40) ++#define __NR_POSIX_dup (__NR_POSIX + 41) ++#define __NR_POSIX_pipe (__NR_POSIX + 42) ++#define __NR_POSIX_times (__NR_POSIX + 43) ++#define __NR_POSIX_profil (__NR_POSIX + 44) ++#define __NR_POSIX_lock (__NR_POSIX + 45) ++#define __NR_POSIX_setgid (__NR_POSIX + 46) ++#define __NR_POSIX_getgid (__NR_POSIX + 47) ++#define __NR_POSIX_sig (__NR_POSIX + 48) ++#define __NR_POSIX_msgsys (__NR_POSIX + 49) ++#define __NR_POSIX_sysmips (__NR_POSIX + 50) ++#define __NR_POSIX_sysacct (__NR_POSIX + 51) ++#define __NR_POSIX_shmsys (__NR_POSIX + 52) ++#define __NR_POSIX_semsys (__NR_POSIX + 53) ++#define __NR_POSIX_ioctl (__NR_POSIX + 54) ++#define __NR_POSIX_uadmin (__NR_POSIX + 55) ++#define __NR_POSIX_exch (__NR_POSIX + 56) ++#define __NR_POSIX_utssys (__NR_POSIX + 57) ++#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) ++#define __NR_POSIX_exece (__NR_POSIX + 59) ++#define __NR_POSIX_umask (__NR_POSIX + 60) ++#define __NR_POSIX_chroot (__NR_POSIX + 61) ++#define __NR_POSIX_fcntl (__NR_POSIX + 62) ++#define __NR_POSIX_ulimit (__NR_POSIX + 63) ++#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) ++#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) ++#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) ++#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) ++#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) ++#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) ++#define __NR_POSIX_advfs (__NR_POSIX + 70) ++#define __NR_POSIX_unadvfs (__NR_POSIX + 71) ++#define __NR_POSIX_rmount (__NR_POSIX + 72) ++#define __NR_POSIX_rumount (__NR_POSIX + 73) ++#define __NR_POSIX_rfstart (__NR_POSIX + 74) ++#define __NR_POSIX_reserved1 (__NR_POSIX + 75) ++#define __NR_POSIX_rdebug (__NR_POSIX + 76) ++#define __NR_POSIX_rfstop (__NR_POSIX + 77) ++#define __NR_POSIX_rfsys (__NR_POSIX + 78) ++#define __NR_POSIX_rmdir (__NR_POSIX + 79) ++#define __NR_POSIX_mkdir (__NR_POSIX + 80) ++#define __NR_POSIX_getdents (__NR_POSIX + 81) ++#define __NR_POSIX_sginap (__NR_POSIX + 82) ++#define __NR_POSIX_sgikopt (__NR_POSIX + 83) ++#define __NR_POSIX_sysfs (__NR_POSIX + 84) ++#define __NR_POSIX_getmsg (__NR_POSIX + 85) ++#define __NR_POSIX_putmsg (__NR_POSIX + 86) ++#define __NR_POSIX_poll (__NR_POSIX + 87) ++#define __NR_POSIX_sigreturn (__NR_POSIX + 88) ++#define __NR_POSIX_accept (__NR_POSIX + 89) ++#define __NR_POSIX_bind (__NR_POSIX + 90) ++#define __NR_POSIX_connect (__NR_POSIX + 91) ++#define __NR_POSIX_gethostid (__NR_POSIX + 92) ++#define __NR_POSIX_getpeername (__NR_POSIX + 93) ++#define __NR_POSIX_getsockname (__NR_POSIX + 94) ++#define __NR_POSIX_getsockopt (__NR_POSIX + 95) ++#define __NR_POSIX_listen (__NR_POSIX + 96) ++#define __NR_POSIX_recv (__NR_POSIX + 97) ++#define __NR_POSIX_recvfrom (__NR_POSIX + 98) ++#define __NR_POSIX_recvmsg (__NR_POSIX + 99) ++#define __NR_POSIX_select (__NR_POSIX + 100) ++#define __NR_POSIX_send (__NR_POSIX + 101) ++#define __NR_POSIX_sendmsg (__NR_POSIX + 102) ++#define __NR_POSIX_sendto (__NR_POSIX + 103) ++#define __NR_POSIX_sethostid (__NR_POSIX + 104) ++#define __NR_POSIX_setsockopt (__NR_POSIX + 105) ++#define __NR_POSIX_shutdown (__NR_POSIX + 106) ++#define __NR_POSIX_socket (__NR_POSIX + 107) ++#define __NR_POSIX_gethostname (__NR_POSIX + 108) ++#define __NR_POSIX_sethostname (__NR_POSIX + 109) ++#define __NR_POSIX_getdomainname (__NR_POSIX + 110) ++#define __NR_POSIX_setdomainname (__NR_POSIX + 111) ++#define __NR_POSIX_truncate (__NR_POSIX + 112) ++#define __NR_POSIX_ftruncate (__NR_POSIX + 113) ++#define __NR_POSIX_rename (__NR_POSIX + 114) ++#define __NR_POSIX_symlink (__NR_POSIX + 115) ++#define __NR_POSIX_readlink (__NR_POSIX + 116) ++#define __NR_POSIX_lstat (__NR_POSIX + 117) ++#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) ++#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) ++#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) ++#define __NR_POSIX_async_daemon (__NR_POSIX + 121) ++#define __NR_POSIX_exportfs (__NR_POSIX + 122) ++#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) ++#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) ++#define __NR_POSIX_getitimer (__NR_POSIX + 125) ++#define __NR_POSIX_setitimer (__NR_POSIX + 126) ++#define __NR_POSIX_adjtime (__NR_POSIX + 127) ++#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) ++#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) ++#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) ++#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) ++#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) ++#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) ++#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) ++#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) ++#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) ++#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) ++#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) ++#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) ++#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) ++#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) ++#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) ++#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) ++#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) ++#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) ++#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) ++#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) ++#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) ++#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) ++#define __NR_POSIX_cacheflush (__NR_POSIX + 150) ++#define __NR_POSIX_cachectl (__NR_POSIX + 151) ++#define __NR_POSIX_fchown (__NR_POSIX + 152) ++#define __NR_POSIX_fchmod (__NR_POSIX + 153) ++#define __NR_POSIX_wait3 (__NR_POSIX + 154) ++#define __NR_POSIX_mmap (__NR_POSIX + 155) ++#define __NR_POSIX_munmap (__NR_POSIX + 156) ++#define __NR_POSIX_madvise (__NR_POSIX + 157) ++#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) ++#define __NR_POSIX_setreuid (__NR_POSIX + 159) ++#define __NR_POSIX_setregid (__NR_POSIX + 160) ++#define __NR_POSIX_setpgid (__NR_POSIX + 161) ++#define __NR_POSIX_getgroups (__NR_POSIX + 162) ++#define __NR_POSIX_setgroups (__NR_POSIX + 163) ++#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) ++#define __NR_POSIX_getrusage (__NR_POSIX + 165) ++#define __NR_POSIX_getrlimit (__NR_POSIX + 166) ++#define __NR_POSIX_setrlimit (__NR_POSIX + 167) ++#define __NR_POSIX_waitpid (__NR_POSIX + 168) ++#define __NR_POSIX_dup2 (__NR_POSIX + 169) ++#define __NR_POSIX_reserved2 (__NR_POSIX + 170) ++#define __NR_POSIX_reserved3 (__NR_POSIX + 171) ++#define __NR_POSIX_reserved4 (__NR_POSIX + 172) ++#define __NR_POSIX_reserved5 (__NR_POSIX + 173) ++#define __NR_POSIX_reserved6 (__NR_POSIX + 174) ++#define __NR_POSIX_reserved7 (__NR_POSIX + 175) ++#define __NR_POSIX_reserved8 (__NR_POSIX + 176) ++#define __NR_POSIX_reserved9 (__NR_POSIX + 177) ++#define __NR_POSIX_reserved10 (__NR_POSIX + 178) ++#define __NR_POSIX_reserved11 (__NR_POSIX + 179) ++#define __NR_POSIX_reserved12 (__NR_POSIX + 180) ++#define __NR_POSIX_reserved13 (__NR_POSIX + 181) ++#define __NR_POSIX_reserved14 (__NR_POSIX + 182) ++#define __NR_POSIX_reserved15 (__NR_POSIX + 183) ++#define __NR_POSIX_reserved16 (__NR_POSIX + 184) ++#define __NR_POSIX_reserved17 (__NR_POSIX + 185) ++#define __NR_POSIX_reserved18 (__NR_POSIX + 186) ++#define __NR_POSIX_reserved19 (__NR_POSIX + 187) ++#define __NR_POSIX_reserved20 (__NR_POSIX + 188) ++#define __NR_POSIX_reserved21 (__NR_POSIX + 189) ++#define __NR_POSIX_reserved22 (__NR_POSIX + 190) ++#define __NR_POSIX_reserved23 (__NR_POSIX + 191) ++#define __NR_POSIX_reserved24 (__NR_POSIX + 192) ++#define __NR_POSIX_reserved25 (__NR_POSIX + 193) ++#define __NR_POSIX_reserved26 (__NR_POSIX + 194) ++#define __NR_POSIX_reserved27 (__NR_POSIX + 195) ++#define __NR_POSIX_reserved28 (__NR_POSIX + 196) ++#define __NR_POSIX_reserved29 (__NR_POSIX + 197) ++#define __NR_POSIX_reserved30 (__NR_POSIX + 198) ++#define __NR_POSIX_reserved31 (__NR_POSIX + 199) ++#define __NR_POSIX_reserved32 (__NR_POSIX + 200) ++#define __NR_POSIX_reserved33 (__NR_POSIX + 201) ++#define __NR_POSIX_reserved34 (__NR_POSIX + 202) ++#define __NR_POSIX_reserved35 (__NR_POSIX + 203) ++#define __NR_POSIX_reserved36 (__NR_POSIX + 204) ++#define __NR_POSIX_reserved37 (__NR_POSIX + 205) ++#define __NR_POSIX_reserved38 (__NR_POSIX + 206) ++#define __NR_POSIX_reserved39 (__NR_POSIX + 207) ++#define __NR_POSIX_reserved40 (__NR_POSIX + 208) ++#define __NR_POSIX_reserved41 (__NR_POSIX + 209) ++#define __NR_POSIX_reserved42 (__NR_POSIX + 210) ++#define __NR_POSIX_reserved43 (__NR_POSIX + 211) ++#define __NR_POSIX_reserved44 (__NR_POSIX + 212) ++#define __NR_POSIX_reserved45 (__NR_POSIX + 213) ++#define __NR_POSIX_reserved46 (__NR_POSIX + 214) ++#define __NR_POSIX_reserved47 (__NR_POSIX + 215) ++#define __NR_POSIX_reserved48 (__NR_POSIX + 216) ++#define __NR_POSIX_reserved49 (__NR_POSIX + 217) ++#define __NR_POSIX_reserved50 (__NR_POSIX + 218) ++#define __NR_POSIX_reserved51 (__NR_POSIX + 219) ++#define __NR_POSIX_reserved52 (__NR_POSIX + 220) ++#define __NR_POSIX_reserved53 (__NR_POSIX + 221) ++#define __NR_POSIX_reserved54 (__NR_POSIX + 222) ++#define __NR_POSIX_reserved55 (__NR_POSIX + 223) ++#define __NR_POSIX_reserved56 (__NR_POSIX + 224) ++#define __NR_POSIX_reserved57 (__NR_POSIX + 225) ++#define __NR_POSIX_reserved58 (__NR_POSIX + 226) ++#define __NR_POSIX_reserved59 (__NR_POSIX + 227) ++#define __NR_POSIX_reserved60 (__NR_POSIX + 228) ++#define __NR_POSIX_reserved61 (__NR_POSIX + 229) ++#define __NR_POSIX_reserved62 (__NR_POSIX + 230) ++#define __NR_POSIX_reserved63 (__NR_POSIX + 231) ++#define __NR_POSIX_reserved64 (__NR_POSIX + 232) ++#define __NR_POSIX_reserved65 (__NR_POSIX + 233) ++#define __NR_POSIX_reserved66 (__NR_POSIX + 234) ++#define __NR_POSIX_reserved67 (__NR_POSIX + 235) ++#define __NR_POSIX_reserved68 (__NR_POSIX + 236) ++#define __NR_POSIX_reserved69 (__NR_POSIX + 237) ++#define __NR_POSIX_reserved70 (__NR_POSIX + 238) ++#define __NR_POSIX_reserved71 (__NR_POSIX + 239) ++#define __NR_POSIX_reserved72 (__NR_POSIX + 240) ++#define __NR_POSIX_reserved73 (__NR_POSIX + 241) ++#define __NR_POSIX_reserved74 (__NR_POSIX + 242) ++#define __NR_POSIX_reserved75 (__NR_POSIX + 243) ++#define __NR_POSIX_reserved76 (__NR_POSIX + 244) ++#define __NR_POSIX_reserved77 (__NR_POSIX + 245) ++#define __NR_POSIX_reserved78 (__NR_POSIX + 246) ++#define __NR_POSIX_reserved79 (__NR_POSIX + 247) ++#define __NR_POSIX_reserved80 (__NR_POSIX + 248) ++#define __NR_POSIX_reserved81 (__NR_POSIX + 249) ++#define __NR_POSIX_reserved82 (__NR_POSIX + 250) ++#define __NR_POSIX_reserved83 (__NR_POSIX + 251) ++#define __NR_POSIX_reserved84 (__NR_POSIX + 252) ++#define __NR_POSIX_reserved85 (__NR_POSIX + 253) ++#define __NR_POSIX_reserved86 (__NR_POSIX + 254) ++#define __NR_POSIX_reserved87 (__NR_POSIX + 255) ++#define __NR_POSIX_reserved88 (__NR_POSIX + 256) ++#define __NR_POSIX_reserved89 (__NR_POSIX + 257) ++#define __NR_POSIX_reserved90 (__NR_POSIX + 258) ++#define __NR_POSIX_reserved91 (__NR_POSIX + 259) ++#define __NR_POSIX_netboot (__NR_POSIX + 260) ++#define __NR_POSIX_netunboot (__NR_POSIX + 261) ++#define __NR_POSIX_rdump (__NR_POSIX + 262) ++#define __NR_POSIX_setsid (__NR_POSIX + 263) ++#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) ++#define __NR_POSIX_sigpending (__NR_POSIX + 265) ++#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) ++#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) ++#define __NR_POSIX_sigaction (__NR_POSIX + 268) ++#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) ++#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) ++#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) ++#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) ++#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) ++#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) ++#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) ++#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) ++#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) ++#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) ++#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) ++#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) ++#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) ++#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) ++#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) ++#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) ++#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) ++#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) ++#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) ++#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) ++#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) ++#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) ++#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) ++#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) ++#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) ++#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) ++#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) ++#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) ++#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) ++#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) ++#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) ++#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) ++#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) ++#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) ++#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) ++#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) ++#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) ++#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) ++#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) ++#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) ++#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) ++#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) ++#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) ++#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) ++#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) ++#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) ++#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) ++#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) ++#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) ++#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) ++#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) ++ ++#endif /* _ASM_RISCOS_SYSCALL_H */ +diff -ruN linux/include/asm-mips/semaphore-helper.h linux-mips/include/asm-mips/semaphore-helper.h +--- linux/include/asm-mips/semaphore-helper.h Sun Jul 9 22:18:15 2000 ++++ linux-mips/include/asm-mips/semaphore-helper.h Fri Nov 10 00:12:03 2000 +@@ -1,5 +1,4 @@ +-/* $Id: semaphore-helper.h,v 1.6 1999/10/20 21:10:58 ralf Exp $ +- * ++/* + * SMP- and interrupt-safe semaphores helper functions. + * + * (C) Copyright 1996 Linus Torvalds +@@ -75,6 +74,7 @@ + ret = 0; + } + restore_flags(flags); ++ + return ret; + } + +@@ -92,7 +92,7 @@ + "sc\t%0, %2\n\t" + "beqz\t%0, 1b\n\t" + "2:" +- : "=r"(ret), "=r"(tmp), "=m"(__atomic_fool_gcc(&sem->waking)) ++ : "=r" (ret), "=r" (tmp), "=m" (sem->waking) + : "0"(0)); + + return ret; +diff -ruN linux/include/asm-mips/semaphore.h linux-mips/include/asm-mips/semaphore.h +--- linux/include/asm-mips/semaphore.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/semaphore.h Fri Nov 10 00:12:03 2000 +@@ -59,7 +59,7 @@ + #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) + #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) + +-extern inline void sema_init (struct semaphore *sem, int val) ++static inline void sema_init (struct semaphore *sem, int val) + { + atomic_set(&sem->count, val); + atomic_set(&sem->waking, 0); +@@ -84,7 +84,7 @@ + asmlinkage int __down_trylock(struct semaphore * sem); + asmlinkage void __up(struct semaphore * sem); + +-extern inline void down(struct semaphore * sem) ++static inline void down(struct semaphore * sem) + { + #if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +@@ -93,7 +93,7 @@ + __down(sem); + } + +-extern inline int down_interruptible(struct semaphore * sem) ++static inline int down_interruptible(struct semaphore * sem) + { + int ret = 0; + +@@ -107,7 +107,7 @@ + + #if !defined(CONFIG_CPU_HAS_LLSC) + +-extern inline int down_trylock(struct semaphore * sem) ++static inline int down_trylock(struct semaphore * sem) + { + int ret = 0; + if (atomic_dec_return(&sem->count) < 0) +@@ -139,7 +139,7 @@ + * } + * } + */ +-extern inline int down_trylock(struct semaphore * sem) ++static inline int down_trylock(struct semaphore * sem) + { + long ret, tmp, tmp2, sub; + +@@ -180,7 +180,7 @@ + * Note! This is subtle. We jump to wake people up only if + * the semaphore was negative (== somebody was waiting on it). + */ +-extern inline void up(struct semaphore * sem) ++static inline void up(struct semaphore * sem) + { + #if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +@@ -247,7 +247,7 @@ + #define DECLARE_RWSEM_WRITE_LOCKED(name) \ + __DECLARE_RWSEM_GENERIC(name, 0) + +-extern inline void init_rwsem(struct rw_semaphore *sem) ++static inline void init_rwsem(struct rw_semaphore *sem) + { + atomic_set(&sem->count, RW_LOCK_BIAS); + sem->granted = 0; +@@ -265,7 +265,7 @@ + extern void __down_write(struct rw_semaphore *sem, int count); + extern void __rwsem_wake(struct rw_semaphore *sem, unsigned long readers); + +-extern inline void down_read(struct rw_semaphore *sem) ++static inline void down_read(struct rw_semaphore *sem) + { + int count; + +@@ -288,7 +288,7 @@ + #endif + } + +-extern inline void down_write(struct rw_semaphore *sem) ++static inline void down_write(struct rw_semaphore *sem) + { + int count; + +@@ -317,7 +317,7 @@ + there was a writer waiting, and we've bumped the count to 0: we must + wake the writer up. */ + +-extern inline void up_read(struct rw_semaphore *sem) ++static inline void up_read(struct rw_semaphore *sem) + { + #if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +@@ -336,7 +336,7 @@ + /* + * Releasing the writer is easy -- just release it and wake up any sleepers. + */ +-extern inline void up_write(struct rw_semaphore *sem) ++static inline void up_write(struct rw_semaphore *sem) + { + int count; + +diff -ruN linux/include/asm-mips/serial.h linux-mips/include/asm-mips/serial.h +--- linux/include/asm-mips/serial.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/serial.h Fri Nov 10 00:12:04 2000 +@@ -76,6 +76,18 @@ + #define JAZZ_SERIAL_PORT_DEFNS + #endif + ++#ifdef CONFIG_MIPS_EV96100 ++#include <asm/galileo-boards/ev96100.h> ++#include <asm/galileo-boards/ev96100int.h> ++#define EV96100_SERIAL_PORT_DEFNS \ ++ { baud_base: EV96100_BASE_BAUD, port: EV96100_UART0_REGS_BASE, \ ++ irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \ ++ iomem_base: EV96100_UART0_REGS_BASE }, ++#else ++#define EV96100_SERIAL_PORT_DEFNS ++#endif ++ ++ + #define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ +@@ -152,7 +164,8 @@ + #endif + + #define SERIAL_PORT_DFNS \ ++ EV96100_SERIAL_PORT_DEFNS \ + JAZZ_SERIAL_PORT_DEFNS \ + STD_SERIAL_PORT_DEFNS \ + EXTRA_SERIAL_PORT_DEFNS \ +- HUB6_SERIAL_PORT_DFNS ++ HUB6_SERIAL_PORT_DFNS +diff -ruN linux/include/asm-mips/sni.h linux-mips/include/asm-mips/sni.h +--- linux/include/asm-mips/sni.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/sni.h Fri Nov 10 00:12:08 2000 +@@ -30,6 +30,14 @@ + #define PCIMT_ERRADDR 0xbfff0040 + #define PCIMT_SYNDROME 0xbfff0048 + #define PCIMT_ITPEND 0xbfff0050 ++#define IT_INT2 0x01 ++#define IT_INTD 0x02 ++#define IT_INTC 0x04 ++#define IT_INTB 0x08 ++#define IT_INTA 0x10 ++#define IT_EISA 0x20 ++#define IT_SCSI 0x40 ++#define IT_ETH 0x80 + #define PCIMT_IRQSEL 0xbfff0058 + #define PCIMT_TESTMEM 0xbfff0060 + #define PCIMT_ECCREG 0xbfff0068 +@@ -73,16 +81,18 @@ + * to the other interrupts generated by ASIC PCI. + */ + #define PCIMT_KEYBOARD_IRQ 1 +-#define PCIMT_IRQ_ETHERNET 16 +-#define PCIMT_IRQ_TEMPERATURE 17 +-#define PCIMT_IRQ_EISA_NMI 18 +-#define PCIMT_IRQ_POWER_OFF 19 +-#define PCIMT_IRQ_BUTTON 20 +-#define PCIMT_IRQ_INTA 21 +-#define PCIMT_IRQ_INTB 22 +-#define PCIMT_IRQ_INTC 23 +-#define PCIMT_IRQ_INTD 24 +-#define PCIMT_IRQ_SCSI 25 ++#define PCIMT_IRQ_INT2 16 /* What is that? */ ++#define PCIMT_IRQ_INTD 17 ++#define PCIMT_IRQ_INTC 18 ++#define PCIMT_IRQ_INTB 19 ++#define PCIMT_IRQ_INTA 20 ++#define PCIMT_IRQ_EISA 21 ++#define PCIMT_IRQ_SCSI 22 ++#define PCIMT_IRQ_ETHERNET 23 ++#define PCIMT_IRQ_TEMPERATURE 24 ++#define PCIMT_IRQ_EISA_NMI 25 ++#define PCIMT_IRQ_POWER_OFF 26 ++#define PCIMT_IRQ_BUTTON 27 + + /* + * Base address for the mapped 16mb EISA bus segment. +diff -ruN linux/include/asm-mips/spinlock.h linux-mips/include/asm-mips/spinlock.h +--- linux/include/asm-mips/spinlock.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/spinlock.h Fri Nov 10 00:12:08 2000 +@@ -1,5 +1,4 @@ +-/* $Id: spinlock.h,v 1.8 2000/01/23 21:15:52 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. +@@ -29,9 +28,6 @@ + * We make no fairness assumptions. They have a cost. + */ + +-typedef struct { unsigned long a[100]; } __dummy_lock_t; +-#define __dummy_lock(lock) (*(__dummy_lock_t *)(lock)) +- + static inline void spin_lock(spinlock_t *lock) + { + unsigned int tmp; +@@ -45,8 +41,8 @@ + "beqz\t%1, 1b\n\t" + " sync\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(lock)), "=&r" (tmp) +- : "o" (__dummy_lock(lock)) ++ : "=o" (lock->lock), "=&r" (tmp) ++ : "o" (lock->lock) + : "memory"); + } + +@@ -57,8 +53,8 @@ + "sync\n\t" + "sw\t$0, %0\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(lock)) +- : "o" (__dummy_lock(lock)) ++ : "=o" (lock->lock) ++ : "o" (lock->lock) + : "memory"); + } + +@@ -92,8 +88,8 @@ + "beqz\t%1, 1b\n\t" + " sync\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)), "=&r" (tmp) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock), "=&r" (tmp) ++ : "o" (rw->lock) + : "memory"); + } + +@@ -111,8 +107,8 @@ + "sc\t%1, %0\n\t" + "beqz\t%1, 1b\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)), "=&r" (tmp) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock), "=&r" (tmp) ++ : "o" (rw->lock) + : "memory"); + } + +@@ -129,8 +125,8 @@ + "beqz\t%1, 1b\n\t" + " sync\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)), "=&r" (tmp) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock), "=&r" (tmp) ++ : "o" (rw->lock) + : "memory"); + } + +@@ -141,8 +137,8 @@ + "sync\n\t" + "sw\t$0, %0\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock) ++ : "o" (rw->lock) + : "memory"); + } + +diff -ruN linux/include/asm-mips/stackframe.h linux-mips/include/asm-mips/stackframe.h +--- linux/include/asm-mips/stackframe.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/stackframe.h Fri Nov 10 00:12:08 2000 +@@ -47,19 +47,28 @@ + #define __str2(x) #x + #define __str(x) __str2(x) + +-#define save_static(frame) \ +- __asm__ __volatile__( \ +- "sw\t$16,"__str(PT_R16)"(%0)\n\t" \ +- "sw\t$17,"__str(PT_R17)"(%0)\n\t" \ +- "sw\t$18,"__str(PT_R18)"(%0)\n\t" \ +- "sw\t$19,"__str(PT_R19)"(%0)\n\t" \ +- "sw\t$20,"__str(PT_R20)"(%0)\n\t" \ +- "sw\t$21,"__str(PT_R21)"(%0)\n\t" \ +- "sw\t$22,"__str(PT_R22)"(%0)\n\t" \ +- "sw\t$23,"__str(PT_R23)"(%0)\n\t" \ +- "sw\t$30,"__str(PT_R30)"(%0)\n\t" \ +- : /* No outputs */ \ +- : "r" (frame)) ++#define save_static_function(symbol) \ ++__asm__ ( \ ++ ".globl\t" #symbol "\n\t" \ ++ ".align\t2\n\t" \ ++ ".type\t" #symbol ", @function\n\t" \ ++ ".ent\t" #symbol ", 0\n" \ ++ #symbol":\n\t" \ ++ ".frame\t$29, 0, $31\n\t" \ ++ "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ ++ "sw\t$17,"__str(PT_R17)"($29)\n\t" \ ++ "sw\t$18,"__str(PT_R18)"($29)\n\t" \ ++ "sw\t$19,"__str(PT_R19)"($29)\n\t" \ ++ "sw\t$20,"__str(PT_R20)"($29)\n\t" \ ++ "sw\t$21,"__str(PT_R21)"($29)\n\t" \ ++ "sw\t$22,"__str(PT_R22)"($29)\n\t" \ ++ "sw\t$23,"__str(PT_R23)"($29)\n\t" \ ++ "sw\t$30,"__str(PT_R30)"($29)\n\t" \ ++ ".end\t" #symbol "\n\t" \ ++ ".size\t" #symbol",. - " #symbol) ++ ++/* Used in declaration of save_static functions. */ ++#define static_unused static __attribute__((unused)) + + #define SAVE_SOME \ + .set push; \ +diff -ruN linux/include/asm-mips/stat.h linux-mips/include/asm-mips/stat.h +--- linux/include/asm-mips/stat.h Sun Jul 9 22:18:15 2000 ++++ linux-mips/include/asm-mips/stat.h Mon Sep 11 23:53:16 2000 +@@ -17,8 +17,7 @@ + unsigned int st_ctime, st_res3; + unsigned int st_blksize; + int st_blocks; +- unsigned int st_flags; +- unsigned int st_gen; ++ unsigned int st_unused0[2]; + }; + + struct stat { +@@ -45,11 +44,7 @@ + long reserved2; + long st_blksize; + long st_blocks; +- char st_fstype[16]; /* Filesystem type name */ +- long st_pad4[8]; +- /* Linux specific fields */ +- unsigned int st_flags; +- unsigned int st_gen; ++ long st_pad4[14]; + }; + + /* +@@ -61,25 +56,36 @@ + struct stat64 { + unsigned long st_dev; + unsigned long st_pad0[3]; /* Reserved for st_dev expansion */ +- ino_t st_ino; ++ ++ unsigned long long st_ino; ++ + mode_t st_mode; + nlink_t st_nlink; ++ + uid_t st_uid; + gid_t st_gid; ++ + unsigned long st_rdev; + unsigned long st_pad1[3]; /* Reserved for st_rdev expansion */ ++ + long long st_size; ++ + /* + * Actually this should be timestruc_t st_atime, st_mtime and st_ctime + * but we don't have it under Linux. + */ + time_t st_atime; + unsigned long reserved0; /* Reserved for st_atime expansion */ ++ + time_t st_mtime; +- unsigned long reserved1; /* Reserved for st_atime expansion */ ++ unsigned long reserved1; /* Reserved for st_mtime expansion */ ++ + time_t st_ctime; +- unsigned long reserved2; /* Reserved for st_atime expansion */ ++ unsigned long reserved2; /* Reserved for st_ctime expansion */ ++ + unsigned long st_blksize; ++ unsigned long st_pad2; ++ + long long st_blocks; + }; + +diff -ruN linux/include/asm-mips/system.h linux-mips/include/asm-mips/system.h +--- linux/include/asm-mips/system.h Thu Aug 3 15:38:11 2000 ++++ linux-mips/include/asm-mips/system.h Fri Nov 10 00:12:09 2000 +@@ -1,5 +1,4 @@ +-/* $Id: system.h,v 1.20 1999/12/06 23:13:21 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. +@@ -61,56 +60,54 @@ + : "$1", "memory"); + } + +-#define __save_flags(x) \ +-__asm__ __volatile__( \ +- ".set\tpush\n\t" \ +- ".set\treorder\n\t" \ +- "mfc0\t%0,$12\n\t" \ +- ".set\tpop\n\t" \ +- : "=r" (x) \ +- : /* no inputs */ \ +- : "memory") +- +-#define __save_and_cli(x) \ +-__asm__ __volatile__( \ +- ".set\tpush\n\t" \ +- ".set\treorder\n\t" \ +- ".set\tnoat\n\t" \ +- "mfc0\t%0,$12\n\t" \ +- "ori\t$1,%0,1\n\t" \ +- "xori\t$1,1\n\t" \ +- ".set\tnoreorder\n\t" \ +- "mtc0\t$1,$12\n\t" \ +- "nop\n\t" \ +- "nop\n\t" \ +- "nop\n\t" \ +- ".set\tpop\n\t" \ +- : "=r" (x) \ +- : /* no inputs */ \ ++#define __save_flags(x) \ ++__asm__ __volatile__( \ ++ ".set\tpush\n\t" \ ++ ".set\treorder\n\t" \ ++ "mfc0\t%0,$12\n\t" \ ++ ".set\tpop\n\t" \ ++ : "=r" (x)) ++ ++#define __save_and_cli(x) \ ++__asm__ __volatile__( \ ++ ".set\tpush\n\t" \ ++ ".set\treorder\n\t" \ ++ ".set\tnoat\n\t" \ ++ "mfc0\t%0,$12\n\t" \ ++ "ori\t$1,%0,1\n\t" \ ++ "xori\t$1,1\n\t" \ ++ ".set\tnoreorder\n\t" \ ++ "mtc0\t$1,$12\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ ".set\tpop\n\t" \ ++ : "=r" (x) \ ++ : /* no inputs */ \ + : "$1", "memory") + +-extern void __inline__ +-__restore_flags(int flags) +-{ +- __asm__ __volatile__( +- ".set\tpush\n\t" +- ".set\treorder\n\t" +- "mfc0\t$8,$12\n\t" +- "li\t$9,0xff00\n\t" +- "and\t$8,$9\n\t" +- "nor\t$9,$0,$9\n\t" +- "and\t%0,$9\n\t" +- "or\t%0,$8\n\t" +- ".set\tnoreorder\n\t" +- "mtc0\t%0,$12\n\t" +- "nop\n\t" +- "nop\n\t" +- "nop\n\t" +- ".set\tpop\n\t" +- : +- : "r" (flags) +- : "$8", "$9", "memory"); +-} ++#define __restore_flags(flags) \ ++do { \ ++ unsigned long __tmp1; \ ++ \ ++ __asm__ __volatile__( \ ++ ".set\tnoreorder\t\t\t# __restore_flags\n\t" \ ++ ".set\tnoat\n\t" \ ++ "mfc0\t$1, $12\n\t" \ ++ "andi\t%0, 1\n\t" \ ++ "ori\t$1, 1\n\t" \ ++ "xori\t$1, 1\n\t" \ ++ "or\t%0, $1\n\t" \ ++ "mtc0\t%0, $12\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ ".set\tat\n\t" \ ++ ".set\treorder" \ ++ : "=r" (__tmp1) \ ++ : "0" (flags) \ ++ : "$1", "memory"); \ ++} while(0) + + /* + * Non-SMP versions ... +@@ -131,11 +128,14 @@ + * These are probably defined overly paranoid ... + */ + #ifdef CONFIG_CPU_HAS_WB ++ + #include <asm/wbflush.h> + #define rmb() + #define wmb() wbflush() + #define mb() wbflush() +-#else ++ ++#else /* CONFIG_CPU_HAS_WB */ ++ + #define mb() \ + __asm__ __volatile__( \ + "# prevent instructions being moved around\n\t" \ +@@ -148,6 +148,17 @@ + : "memory") + #define rmb() mb() + #define wmb() mb() ++ ++#endif /* CONFIG_CPU_HAS_WB */ ++ ++#ifdef CONFIG_SMP ++#define smp_mb() mb() ++#define smp_rmb() rmb() ++#define smp_wmb() wmb() ++#else ++#define smp_mb() barrier() ++#define smp_rmb() barrier() ++#define smp_wmb() barrier() + #endif + + #define set_mb(var, value) \ +@@ -180,17 +191,17 @@ + unsigned long dummy; + + __asm__ __volatile__( +- ".set\tnoreorder\n\t" ++ ".set\tnoreorder\t\t\t# xchg_u32\n\t" + ".set\tnoat\n\t" +- "ll\t%0,(%1)\n" +- "1:\tmove\t$1,%2\n\t" +- "sc\t$1,(%1)\n\t" +- "beqzl\t$1,1b\n\t" +- "ll\t%0,(%1)\n\t" ++ "ll\t%0, %3\n" ++ "1:\tmove\t$1, %2\n\t" ++ "sc\t$1, %1\n\t" ++ "beqzl\t$1, 1b\n\t" ++ " ll\t%0, %3\n\t" + ".set\tat\n\t" + ".set\treorder" +- : "=r" (val), "=r" (m), "=r" (dummy) +- : "1" (m), "2" (val) ++ : "=r" (val), "=o" (*m), "=r" (dummy) ++ : "o" (*m), "2" (val) + : "memory"); + + return val; +@@ -207,54 +218,16 @@ + #endif /* Processor-dependent optimization */ + } + +-/* +- * Only used for 64 bit kernel. +- */ +-extern __inline__ unsigned long xchg_u64(volatile long * m, unsigned long val) +-{ +- unsigned long dummy; +- +- __asm__ __volatile__( +- ".set\tnoreorder\n\t" +- ".set\tnoat\n\t" +- "lld\t%0,(%1)\n" +- "1:\tmove\t$1,%2\n\t" +- "scd\t$1,(%1)\n\t" +- "beqzl\t$1,1b\n\t" +- "lld\t%0,(%1)\n\t" +- ".set\tat\n\t" +- ".set\treorder" +- : "=r" (val), "=r" (m), "=r" (dummy) +- : "1" (m), "2" (val) +- : "memory"); +- +- return val; +-} +- + #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + #define tas(ptr) (xchg((ptr),1)) + +-/* +- * This function doesn't exist, so you'll get a linker error +- * if something tries to do an invalid xchg(). +- * +- * This only works if the compiler isn't horribly bad at optimizing. +- * gcc-2.5.8 reportedly can't handle this, but I define that one to +- * be dead anyway. +- */ +-extern void __xchg_called_with_bad_pointer(void); +- +-static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size) ++static __inline__ unsigned long ++__xchg(unsigned long x, volatile void * ptr, int size) + { + switch (size) { + case 4: + return xchg_u32(ptr, x); +-#if defined(__mips64) +- case 8: +- return xchg_u64(ptr, x); +-#endif + } +- __xchg_called_with_bad_pointer(); + return x; + } + +diff -ruN linux/include/asm-mips/unaligned.h linux-mips/include/asm-mips/unaligned.h +--- linux/include/asm-mips/unaligned.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/unaligned.h Fri Nov 10 00:12:11 2000 +@@ -1,10 +1,10 @@ +-/* $Id$ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1996, 1999 by Ralf Baechle ++ * Copyright (C) 1996, 1999, 2000 by Ralf Baechle ++ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ + #ifndef _ASM_UNALIGNED_H + #define _ASM_UNALIGNED_H +@@ -13,133 +13,129 @@ + extern void __put_unaligned_bad_length(void); + + /* +- * Load quad unaligned. ++ * Load double unaligned. ++ * ++ * This could have been implemented in plain C like IA64 but egcs 1.0.3a ++ * inflates this to 23 instructions ... + */ +-extern __inline__ unsigned long ldq_u(const unsigned long long * __addr) ++extern inline unsigned long long __ldq_u(const unsigned long long * __addr) + { + unsigned long long __res; + +- __asm__("uld\t%0,(%1)" +- :"=&r" (__res) +- :"r" (__addr)); ++ __asm__("ulw\t%0, %1\n\t" ++ "ulw\t%D0, 4+%1" ++ : "=&r" (__res) ++ : "m" (*__addr)); + + return __res; + } + + /* +- * Load long unaligned. ++ * Load word unaligned. + */ +-extern __inline__ unsigned long ldl_u(const unsigned int * __addr) ++extern inline unsigned long __ldl_u(const unsigned int * __addr) + { + unsigned long __res; + +- __asm__("ulw\t%0,(%1)" +- :"=&r" (__res) +- :"r" (__addr)); ++ __asm__("ulw\t%0,%1" ++ : "=&r" (__res) ++ : "m" (*__addr)); + + return __res; + } + + /* +- * Load word unaligned. ++ * Load halfword unaligned. + */ +-extern __inline__ unsigned long ldw_u(const unsigned short * __addr) ++extern inline unsigned long __ldw_u(const unsigned short * __addr) + { + unsigned long __res; + +- __asm__("ulh\t%0,(%1)" +- :"=&r" (__res) +- :"r" (__addr)); ++ __asm__("ulh\t%0,%1" ++ : "=&r" (__res) ++ : "m" (*__addr)); + + return __res; + } + + /* +- * Store quad ununaligned. ++ * Store doubleword ununaligned. + */ +-extern __inline__ void stq_u(unsigned long __val, unsigned long long * __addr) ++extern inline void __stq_u(unsigned long __val, unsigned long long * __addr) + { +- __asm__ __volatile__( +- "usd\t%0,(%1)" +- : /* No results */ +- :"r" (__val), +- "r" (__addr)); ++ __asm__("usw\t%1, %0\n\t" ++ "usw\t%D1, 4+%0" ++ : "=m" (*__addr) ++ : "r" (__val)); + } + + /* + * Store long ununaligned. + */ +-extern __inline__ void stl_u(unsigned long __val, unsigned int * __addr) ++extern inline void __stl_u(unsigned long __val, unsigned int * __addr) + { +- __asm__ __volatile__( +- "usw\t%0,(%1)" +- : /* No results */ +- :"r" (__val), +- "r" (__addr)); ++ __asm__("usw\t%1, %0" ++ : "=m" (*__addr) ++ : "r" (__val)); + } + + /* + * Store word ununaligned. + */ +-extern __inline__ void stw_u(unsigned long __val, unsigned short * __addr) ++extern inline void __stw_u(unsigned long __val, unsigned short * __addr) + { +- __asm__ __volatile__( +- "ush\t%0,(%1)" +- : /* No results */ +- :"r" (__val), +- "r" (__addr)); +-} +- +-extern inline unsigned long __get_unaligned(const void *ptr, size_t size) +-{ +- unsigned long val; +- switch (size) { +- case 1: +- val = *(const unsigned char *)ptr; +- break; +- case 2: +- val = ldw_u((const unsigned short *)ptr); +- break; +- case 4: +- val = ldl_u((const unsigned int *)ptr); +- break; +- case 8: +- val = ldq_u((const unsigned long long *)ptr); +- break; +- default: +- __get_unaligned_bad_length(); +- break; +- } +- return val; +-} +- +-extern inline void __put_unaligned(unsigned long val, void *ptr, size_t size) +-{ +- switch (size) { +- case 1: +- *(unsigned char *)ptr = (val); +- break; +- case 2: +- stw_u(val, (unsigned short *)ptr); +- break; +- case 4: +- stl_u(val, (unsigned int *)ptr); +- break; +- case 8: +- stq_u(val, (unsigned long long *)ptr); +- break; +- default: +- __put_unaligned_bad_length(); +- break; +- } ++ __asm__("ush\t%1, %0" ++ : "=m" (*__addr) ++ : "r" (__val)); + } + + /* + * The main single-value unaligned transfer routines. + */ +-#define get_unaligned(ptr) \ +- ((__typeof__(*(ptr)))__get_unaligned((ptr), sizeof(*(ptr)))) +-#define put_unaligned(x,ptr) \ +- __put_unaligned((unsigned long)(x), (ptr), sizeof(*(ptr))) ++#define get_unaligned(ptr) \ ++({ \ ++ __typeof__(*(ptr)) __val; \ ++ \ ++ switch (sizeof(*(ptr))) { \ ++ case 1: \ ++ __val = *(const unsigned char *)ptr; \ ++ break; \ ++ case 2: \ ++ __val = __ldw_u((const unsigned short *)ptr); \ ++ break; \ ++ case 4: \ ++ __val = __ldl_u((const unsigned int *)ptr); \ ++ break; \ ++ case 8: \ ++ __val = __ldq_u((const unsigned long long *)ptr); \ ++ break; \ ++ default: \ ++ __get_unaligned_bad_length(); \ ++ break; \ ++ } \ ++ \ ++ __val; \ ++}) ++ ++#define put_unaligned(val,ptr) \ ++do { \ ++ switch (sizeof(*(ptr))) { \ ++ case 1: \ ++ *(unsigned char *)(ptr) = (val); \ ++ break; \ ++ case 2: \ ++ __stw_u(val, (unsigned short *)(ptr)); \ ++ break; \ ++ case 4: \ ++ __stl_u(val, (unsigned int *)(ptr)); \ ++ break; \ ++ case 8: \ ++ __stq_u(val, (unsigned long long *)(ptr)); \ ++ break; \ ++ default: \ ++ __put_unaligned_bad_length(); \ ++ break; \ ++ } \ ++} while(0) + + #endif /* _ASM_UNALIGNED_H */ +diff -ruN linux/include/asm-mips/unistd.h linux-mips/include/asm-mips/unistd.h +--- linux/include/asm-mips/unistd.h Fri Aug 11 14:29:03 2000 ++++ linux-mips/include/asm-mips/unistd.h Fri Nov 10 00:12:13 2000 +@@ -1,990 +1,16 @@ +-/* $Id: unistd.h,v 1.20 2000/02/18 00:24:48 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle ++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle + * + * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto + * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A + */ +-#ifndef __ASM_MIPS_UNISTD_H +-#define __ASM_MIPS_UNISTD_H +- +-/* +- * The syscalls 0 - 3999 are reserved for a down to the root syscall +- * compatibility with RISC/os and IRIX. We'll see how to deal with the +- * various "real" BSD variants like Ultrix, NetBSD ... +- */ +- +-/* +- * SVR4 syscalls are in the range from 1 to 999 +- */ +-#define __NR_SVR4 0 +-#define __NR_SVR4_syscall (__NR_SVR4 + 0) +-#define __NR_SVR4_exit (__NR_SVR4 + 1) +-#define __NR_SVR4_fork (__NR_SVR4 + 2) +-#define __NR_SVR4_read (__NR_SVR4 + 3) +-#define __NR_SVR4_write (__NR_SVR4 + 4) +-#define __NR_SVR4_open (__NR_SVR4 + 5) +-#define __NR_SVR4_close (__NR_SVR4 + 6) +-#define __NR_SVR4_wait (__NR_SVR4 + 7) +-#define __NR_SVR4_creat (__NR_SVR4 + 8) +-#define __NR_SVR4_link (__NR_SVR4 + 9) +-#define __NR_SVR4_unlink (__NR_SVR4 + 10) +-#define __NR_SVR4_exec (__NR_SVR4 + 11) +-#define __NR_SVR4_chdir (__NR_SVR4 + 12) +-#define __NR_SVR4_gtime (__NR_SVR4 + 13) +-#define __NR_SVR4_mknod (__NR_SVR4 + 14) +-#define __NR_SVR4_chmod (__NR_SVR4 + 15) +-#define __NR_SVR4_chown (__NR_SVR4 + 16) +-#define __NR_SVR4_sbreak (__NR_SVR4 + 17) +-#define __NR_SVR4_stat (__NR_SVR4 + 18) +-#define __NR_SVR4_lseek (__NR_SVR4 + 19) +-#define __NR_SVR4_getpid (__NR_SVR4 + 20) +-#define __NR_SVR4_mount (__NR_SVR4 + 21) +-#define __NR_SVR4_umount (__NR_SVR4 + 22) +-#define __NR_SVR4_setuid (__NR_SVR4 + 23) +-#define __NR_SVR4_getuid (__NR_SVR4 + 24) +-#define __NR_SVR4_stime (__NR_SVR4 + 25) +-#define __NR_SVR4_ptrace (__NR_SVR4 + 26) +-#define __NR_SVR4_alarm (__NR_SVR4 + 27) +-#define __NR_SVR4_fstat (__NR_SVR4 + 28) +-#define __NR_SVR4_pause (__NR_SVR4 + 29) +-#define __NR_SVR4_utime (__NR_SVR4 + 30) +-#define __NR_SVR4_stty (__NR_SVR4 + 31) +-#define __NR_SVR4_gtty (__NR_SVR4 + 32) +-#define __NR_SVR4_access (__NR_SVR4 + 33) +-#define __NR_SVR4_nice (__NR_SVR4 + 34) +-#define __NR_SVR4_statfs (__NR_SVR4 + 35) +-#define __NR_SVR4_sync (__NR_SVR4 + 36) +-#define __NR_SVR4_kill (__NR_SVR4 + 37) +-#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) +-#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) +-#define __NR_SVR4_cxenix (__NR_SVR4 + 40) +-#define __NR_SVR4_dup (__NR_SVR4 + 41) +-#define __NR_SVR4_pipe (__NR_SVR4 + 42) +-#define __NR_SVR4_times (__NR_SVR4 + 43) +-#define __NR_SVR4_profil (__NR_SVR4 + 44) +-#define __NR_SVR4_plock (__NR_SVR4 + 45) +-#define __NR_SVR4_setgid (__NR_SVR4 + 46) +-#define __NR_SVR4_getgid (__NR_SVR4 + 47) +-#define __NR_SVR4_sig (__NR_SVR4 + 48) +-#define __NR_SVR4_msgsys (__NR_SVR4 + 49) +-#define __NR_SVR4_sysmips (__NR_SVR4 + 50) +-#define __NR_SVR4_sysacct (__NR_SVR4 + 51) +-#define __NR_SVR4_shmsys (__NR_SVR4 + 52) +-#define __NR_SVR4_semsys (__NR_SVR4 + 53) +-#define __NR_SVR4_ioctl (__NR_SVR4 + 54) +-#define __NR_SVR4_uadmin (__NR_SVR4 + 55) +-#define __NR_SVR4_exch (__NR_SVR4 + 56) +-#define __NR_SVR4_utssys (__NR_SVR4 + 57) +-#define __NR_SVR4_fsync (__NR_SVR4 + 58) +-#define __NR_SVR4_exece (__NR_SVR4 + 59) +-#define __NR_SVR4_umask (__NR_SVR4 + 60) +-#define __NR_SVR4_chroot (__NR_SVR4 + 61) +-#define __NR_SVR4_fcntl (__NR_SVR4 + 62) +-#define __NR_SVR4_ulimit (__NR_SVR4 + 63) +-#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) +-#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) +-#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) +-#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) +-#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) +-#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) +-#define __NR_SVR4_advfs (__NR_SVR4 + 70) +-#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) +-#define __NR_SVR4_unused1 (__NR_SVR4 + 72) +-#define __NR_SVR4_unused2 (__NR_SVR4 + 73) +-#define __NR_SVR4_rfstart (__NR_SVR4 + 74) +-#define __NR_SVR4_unused3 (__NR_SVR4 + 75) +-#define __NR_SVR4_rdebug (__NR_SVR4 + 76) +-#define __NR_SVR4_rfstop (__NR_SVR4 + 77) +-#define __NR_SVR4_rfsys (__NR_SVR4 + 78) +-#define __NR_SVR4_rmdir (__NR_SVR4 + 79) +-#define __NR_SVR4_mkdir (__NR_SVR4 + 80) +-#define __NR_SVR4_getdents (__NR_SVR4 + 81) +-#define __NR_SVR4_libattach (__NR_SVR4 + 82) +-#define __NR_SVR4_libdetach (__NR_SVR4 + 83) +-#define __NR_SVR4_sysfs (__NR_SVR4 + 84) +-#define __NR_SVR4_getmsg (__NR_SVR4 + 85) +-#define __NR_SVR4_putmsg (__NR_SVR4 + 86) +-#define __NR_SVR4_poll (__NR_SVR4 + 87) +-#define __NR_SVR4_lstat (__NR_SVR4 + 88) +-#define __NR_SVR4_symlink (__NR_SVR4 + 89) +-#define __NR_SVR4_readlink (__NR_SVR4 + 90) +-#define __NR_SVR4_setgroups (__NR_SVR4 + 91) +-#define __NR_SVR4_getgroups (__NR_SVR4 + 92) +-#define __NR_SVR4_fchmod (__NR_SVR4 + 93) +-#define __NR_SVR4_fchown (__NR_SVR4 + 94) +-#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) +-#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) +-#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) +-#define __NR_SVR4_sigaction (__NR_SVR4 + 98) +-#define __NR_SVR4_sigpending (__NR_SVR4 + 99) +-#define __NR_SVR4_setcontext (__NR_SVR4 + 100) +-#define __NR_SVR4_evsys (__NR_SVR4 + 101) +-#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) +-#define __NR_SVR4_statvfs (__NR_SVR4 + 103) +-#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) +-#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) +-#define __NR_SVR4_nfssys (__NR_SVR4 + 106) +-#define __NR_SVR4_waitid (__NR_SVR4 + 107) +-#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) +-#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) +-#define __NR_SVR4_acancel (__NR_SVR4 + 110) +-#define __NR_SVR4_async (__NR_SVR4 + 111) +-#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) +-#define __NR_SVR4_pathconf (__NR_SVR4 + 113) +-#define __NR_SVR4_mincore (__NR_SVR4 + 114) +-#define __NR_SVR4_mmap (__NR_SVR4 + 115) +-#define __NR_SVR4_mprotect (__NR_SVR4 + 116) +-#define __NR_SVR4_munmap (__NR_SVR4 + 117) +-#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) +-#define __NR_SVR4_vfork (__NR_SVR4 + 119) +-#define __NR_SVR4_fchdir (__NR_SVR4 + 120) +-#define __NR_SVR4_readv (__NR_SVR4 + 121) +-#define __NR_SVR4_writev (__NR_SVR4 + 122) +-#define __NR_SVR4_xstat (__NR_SVR4 + 123) +-#define __NR_SVR4_lxstat (__NR_SVR4 + 124) +-#define __NR_SVR4_fxstat (__NR_SVR4 + 125) +-#define __NR_SVR4_xmknod (__NR_SVR4 + 126) +-#define __NR_SVR4_clocal (__NR_SVR4 + 127) +-#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) +-#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) +-#define __NR_SVR4_lchown (__NR_SVR4 + 130) +-#define __NR_SVR4_memcntl (__NR_SVR4 + 131) +-#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) +-#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) +-#define __NR_SVR4_rename (__NR_SVR4 + 134) +-#define __NR_SVR4_nuname (__NR_SVR4 + 135) +-#define __NR_SVR4_setegid (__NR_SVR4 + 136) +-#define __NR_SVR4_sysconf (__NR_SVR4 + 137) +-#define __NR_SVR4_adjtime (__NR_SVR4 + 138) +-#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) +-#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) +-#define __NR_SVR4_seteuid (__NR_SVR4 + 141) +-#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) +-#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) +-#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) +-#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) +-#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) +-#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) +-#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) +-#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) +-#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) +-#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) +-#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) +-#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) +-#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) +-#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) +-#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) +-#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) +-#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) +-#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) +-#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) +-#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) +-#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) +-#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) +-#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) +-#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) +-#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) +-#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) +-#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) +-#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) +-#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) +-#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) +-#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) +-#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) +-#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) +-#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) +-#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) +-#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) +-#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) +-#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) +-#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) +-#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) +-#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) +-#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) +-#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) +-#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) +-#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) +-#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) +-#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) +-#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) +-#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) +-#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) +-#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) +-#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) +-#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) +-#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) +-#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) +-#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) +-#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) +-#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) +-#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) +-#define __NR_SVR4_aread (__NR_SVR4 + 201) +-#define __NR_SVR4_awrite (__NR_SVR4 + 202) +-#define __NR_SVR4_listio (__NR_SVR4 + 203) +-#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) +-#define __NR_SVR4_astatus (__NR_SVR4 + 205) +-#define __NR_SVR4_await (__NR_SVR4 + 206) +-#define __NR_SVR4_areadv (__NR_SVR4 + 207) +-#define __NR_SVR4_awritev (__NR_SVR4 + 208) +-#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) +-#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) +-#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) +-#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) +-#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) +-#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) +-#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) +-#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) +-#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) +-#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) +-#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) +-#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) +-#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) +-#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) +-#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) +-#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) +-#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) +-#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) +-#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) +-#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) +-#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) +-#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) +-#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) +-#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) +-#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) +-#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) +-#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) +-#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) +-#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) +-#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) +-#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) +-#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) +- +-/* +- * SYS V syscalls are in the range from 1000 to 1999 +- */ +-#define __NR_SYSV 1000 +-#define __NR_SYSV_syscall (__NR_SYSV + 0) +-#define __NR_SYSV_exit (__NR_SYSV + 1) +-#define __NR_SYSV_fork (__NR_SYSV + 2) +-#define __NR_SYSV_read (__NR_SYSV + 3) +-#define __NR_SYSV_write (__NR_SYSV + 4) +-#define __NR_SYSV_open (__NR_SYSV + 5) +-#define __NR_SYSV_close (__NR_SYSV + 6) +-#define __NR_SYSV_wait (__NR_SYSV + 7) +-#define __NR_SYSV_creat (__NR_SYSV + 8) +-#define __NR_SYSV_link (__NR_SYSV + 9) +-#define __NR_SYSV_unlink (__NR_SYSV + 10) +-#define __NR_SYSV_execv (__NR_SYSV + 11) +-#define __NR_SYSV_chdir (__NR_SYSV + 12) +-#define __NR_SYSV_time (__NR_SYSV + 13) +-#define __NR_SYSV_mknod (__NR_SYSV + 14) +-#define __NR_SYSV_chmod (__NR_SYSV + 15) +-#define __NR_SYSV_chown (__NR_SYSV + 16) +-#define __NR_SYSV_brk (__NR_SYSV + 17) +-#define __NR_SYSV_stat (__NR_SYSV + 18) +-#define __NR_SYSV_lseek (__NR_SYSV + 19) +-#define __NR_SYSV_getpid (__NR_SYSV + 20) +-#define __NR_SYSV_mount (__NR_SYSV + 21) +-#define __NR_SYSV_umount (__NR_SYSV + 22) +-#define __NR_SYSV_setuid (__NR_SYSV + 23) +-#define __NR_SYSV_getuid (__NR_SYSV + 24) +-#define __NR_SYSV_stime (__NR_SYSV + 25) +-#define __NR_SYSV_ptrace (__NR_SYSV + 26) +-#define __NR_SYSV_alarm (__NR_SYSV + 27) +-#define __NR_SYSV_fstat (__NR_SYSV + 28) +-#define __NR_SYSV_pause (__NR_SYSV + 29) +-#define __NR_SYSV_utime (__NR_SYSV + 30) +-#define __NR_SYSV_stty (__NR_SYSV + 31) +-#define __NR_SYSV_gtty (__NR_SYSV + 32) +-#define __NR_SYSV_access (__NR_SYSV + 33) +-#define __NR_SYSV_nice (__NR_SYSV + 34) +-#define __NR_SYSV_statfs (__NR_SYSV + 35) +-#define __NR_SYSV_sync (__NR_SYSV + 36) +-#define __NR_SYSV_kill (__NR_SYSV + 37) +-#define __NR_SYSV_fstatfs (__NR_SYSV + 38) +-#define __NR_SYSV_setpgrp (__NR_SYSV + 39) +-#define __NR_SYSV_syssgi (__NR_SYSV + 40) +-#define __NR_SYSV_dup (__NR_SYSV + 41) +-#define __NR_SYSV_pipe (__NR_SYSV + 42) +-#define __NR_SYSV_times (__NR_SYSV + 43) +-#define __NR_SYSV_profil (__NR_SYSV + 44) +-#define __NR_SYSV_plock (__NR_SYSV + 45) +-#define __NR_SYSV_setgid (__NR_SYSV + 46) +-#define __NR_SYSV_getgid (__NR_SYSV + 47) +-#define __NR_SYSV_sig (__NR_SYSV + 48) +-#define __NR_SYSV_msgsys (__NR_SYSV + 49) +-#define __NR_SYSV_sysmips (__NR_SYSV + 50) +-#define __NR_SYSV_acct (__NR_SYSV + 51) +-#define __NR_SYSV_shmsys (__NR_SYSV + 52) +-#define __NR_SYSV_semsys (__NR_SYSV + 53) +-#define __NR_SYSV_ioctl (__NR_SYSV + 54) +-#define __NR_SYSV_uadmin (__NR_SYSV + 55) +-#define __NR_SYSV_sysmp (__NR_SYSV + 56) +-#define __NR_SYSV_utssys (__NR_SYSV + 57) +-#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) +-#define __NR_SYSV_execve (__NR_SYSV + 59) +-#define __NR_SYSV_umask (__NR_SYSV + 60) +-#define __NR_SYSV_chroot (__NR_SYSV + 61) +-#define __NR_SYSV_fcntl (__NR_SYSV + 62) +-#define __NR_SYSV_ulimit (__NR_SYSV + 63) +-#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) +-#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) +-#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) +-#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) +-#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) +-#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) +-#define __NR_SYSV_advfs (__NR_SYSV + 70) +-#define __NR_SYSV_unadvfs (__NR_SYSV + 71) +-#define __NR_SYSV_rmount (__NR_SYSV + 72) +-#define __NR_SYSV_rumount (__NR_SYSV + 73) +-#define __NR_SYSV_rfstart (__NR_SYSV + 74) +-#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) +-#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) +-#define __NR_SYSV_nanosleep (__NR_SYSV + 77) +-#define __NR_SYSV_lseek64 (__NR_SYSV + 78) +-#define __NR_SYSV_rmdir (__NR_SYSV + 79) +-#define __NR_SYSV_mkdir (__NR_SYSV + 80) +-#define __NR_SYSV_getdents (__NR_SYSV + 81) +-#define __NR_SYSV_sginap (__NR_SYSV + 82) +-#define __NR_SYSV_sgikopt (__NR_SYSV + 83) +-#define __NR_SYSV_sysfs (__NR_SYSV + 84) +-#define __NR_SYSV_getmsg (__NR_SYSV + 85) +-#define __NR_SYSV_putmsg (__NR_SYSV + 86) +-#define __NR_SYSV_poll (__NR_SYSV + 87) +-#define __NR_SYSV_sigreturn (__NR_SYSV + 88) +-#define __NR_SYSV_accept (__NR_SYSV + 89) +-#define __NR_SYSV_bind (__NR_SYSV + 90) +-#define __NR_SYSV_connect (__NR_SYSV + 91) +-#define __NR_SYSV_gethostid (__NR_SYSV + 92) +-#define __NR_SYSV_getpeername (__NR_SYSV + 93) +-#define __NR_SYSV_getsockname (__NR_SYSV + 94) +-#define __NR_SYSV_getsockopt (__NR_SYSV + 95) +-#define __NR_SYSV_listen (__NR_SYSV + 96) +-#define __NR_SYSV_recv (__NR_SYSV + 97) +-#define __NR_SYSV_recvfrom (__NR_SYSV + 98) +-#define __NR_SYSV_recvmsg (__NR_SYSV + 99) +-#define __NR_SYSV_select (__NR_SYSV + 100) +-#define __NR_SYSV_send (__NR_SYSV + 101) +-#define __NR_SYSV_sendmsg (__NR_SYSV + 102) +-#define __NR_SYSV_sendto (__NR_SYSV + 103) +-#define __NR_SYSV_sethostid (__NR_SYSV + 104) +-#define __NR_SYSV_setsockopt (__NR_SYSV + 105) +-#define __NR_SYSV_shutdown (__NR_SYSV + 106) +-#define __NR_SYSV_socket (__NR_SYSV + 107) +-#define __NR_SYSV_gethostname (__NR_SYSV + 108) +-#define __NR_SYSV_sethostname (__NR_SYSV + 109) +-#define __NR_SYSV_getdomainname (__NR_SYSV + 110) +-#define __NR_SYSV_setdomainname (__NR_SYSV + 111) +-#define __NR_SYSV_truncate (__NR_SYSV + 112) +-#define __NR_SYSV_ftruncate (__NR_SYSV + 113) +-#define __NR_SYSV_rename (__NR_SYSV + 114) +-#define __NR_SYSV_symlink (__NR_SYSV + 115) +-#define __NR_SYSV_readlink (__NR_SYSV + 116) +-#define __NR_SYSV_lstat (__NR_SYSV + 117) +-#define __NR_SYSV_nfsmount (__NR_SYSV + 118) +-#define __NR_SYSV_nfssvc (__NR_SYSV + 119) +-#define __NR_SYSV_getfh (__NR_SYSV + 120) +-#define __NR_SYSV_async_daemon (__NR_SYSV + 121) +-#define __NR_SYSV_exportfs (__NR_SYSV + 122) +-#define __NR_SYSV_setregid (__NR_SYSV + 123) +-#define __NR_SYSV_setreuid (__NR_SYSV + 124) +-#define __NR_SYSV_getitimer (__NR_SYSV + 125) +-#define __NR_SYSV_setitimer (__NR_SYSV + 126) +-#define __NR_SYSV_adjtime (__NR_SYSV + 127) +-#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) +-#define __NR_SYSV_sproc (__NR_SYSV + 129) +-#define __NR_SYSV_prctl (__NR_SYSV + 130) +-#define __NR_SYSV_procblk (__NR_SYSV + 131) +-#define __NR_SYSV_sprocsp (__NR_SYSV + 132) +-#define __NR_SYSV_sgigsc (__NR_SYSV + 133) +-#define __NR_SYSV_mmap (__NR_SYSV + 134) +-#define __NR_SYSV_munmap (__NR_SYSV + 135) +-#define __NR_SYSV_mprotect (__NR_SYSV + 136) +-#define __NR_SYSV_msync (__NR_SYSV + 137) +-#define __NR_SYSV_madvise (__NR_SYSV + 138) +-#define __NR_SYSV_pagelock (__NR_SYSV + 139) +-#define __NR_SYSV_getpagesize (__NR_SYSV + 140) +-#define __NR_SYSV_quotactl (__NR_SYSV + 141) +-#define __NR_SYSV_libdetach (__NR_SYSV + 142) +-#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) +-#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) +-#define __NR_SYSV_vhangup (__NR_SYSV + 145) +-#define __NR_SYSV_fsync (__NR_SYSV + 146) +-#define __NR_SYSV_fchdir (__NR_SYSV + 147) +-#define __NR_SYSV_getrlimit (__NR_SYSV + 148) +-#define __NR_SYSV_setrlimit (__NR_SYSV + 149) +-#define __NR_SYSV_cacheflush (__NR_SYSV + 150) +-#define __NR_SYSV_cachectl (__NR_SYSV + 151) +-#define __NR_SYSV_fchown (__NR_SYSV + 152) +-#define __NR_SYSV_fchmod (__NR_SYSV + 153) +-#define __NR_SYSV_wait3 (__NR_SYSV + 154) +-#define __NR_SYSV_socketpair (__NR_SYSV + 155) +-#define __NR_SYSV_sysinfo (__NR_SYSV + 156) +-#define __NR_SYSV_nuname (__NR_SYSV + 157) +-#define __NR_SYSV_xstat (__NR_SYSV + 158) +-#define __NR_SYSV_lxstat (__NR_SYSV + 159) +-#define __NR_SYSV_fxstat (__NR_SYSV + 160) +-#define __NR_SYSV_xmknod (__NR_SYSV + 161) +-#define __NR_SYSV_ksigaction (__NR_SYSV + 162) +-#define __NR_SYSV_sigpending (__NR_SYSV + 163) +-#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) +-#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) +-#define __NR_SYSV_sigpoll (__NR_SYSV + 166) +-#define __NR_SYSV_swapctl (__NR_SYSV + 167) +-#define __NR_SYSV_getcontext (__NR_SYSV + 168) +-#define __NR_SYSV_setcontext (__NR_SYSV + 169) +-#define __NR_SYSV_waitsys (__NR_SYSV + 170) +-#define __NR_SYSV_sigstack (__NR_SYSV + 171) +-#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) +-#define __NR_SYSV_sigsendset (__NR_SYSV + 173) +-#define __NR_SYSV_statvfs (__NR_SYSV + 174) +-#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) +-#define __NR_SYSV_getpmsg (__NR_SYSV + 176) +-#define __NR_SYSV_putpmsg (__NR_SYSV + 177) +-#define __NR_SYSV_lchown (__NR_SYSV + 178) +-#define __NR_SYSV_priocntl (__NR_SYSV + 179) +-#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) +-#define __NR_SYSV_readv (__NR_SYSV + 181) +-#define __NR_SYSV_writev (__NR_SYSV + 182) +-#define __NR_SYSV_truncate64 (__NR_SYSV + 183) +-#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) +-#define __NR_SYSV_mmap64 (__NR_SYSV + 185) +-#define __NR_SYSV_dmi (__NR_SYSV + 186) +-#define __NR_SYSV_pread (__NR_SYSV + 187) +-#define __NR_SYSV_pwrite (__NR_SYSV + 188) ++#ifndef _ASM_UNISTD_H ++#define _ASM_UNISTD_H + +-/* +- * BSD 4.3 syscalls are in the range from 2000 to 2999 +- */ +-#define __NR_BSD43 2000 +-#define __NR_BSD43_syscall (__NR_BSD43 + 0) +-#define __NR_BSD43_exit (__NR_BSD43 + 1) +-#define __NR_BSD43_fork (__NR_BSD43 + 2) +-#define __NR_BSD43_read (__NR_BSD43 + 3) +-#define __NR_BSD43_write (__NR_BSD43 + 4) +-#define __NR_BSD43_open (__NR_BSD43 + 5) +-#define __NR_BSD43_close (__NR_BSD43 + 6) +-#define __NR_BSD43_wait (__NR_BSD43 + 7) +-#define __NR_BSD43_creat (__NR_BSD43 + 8) +-#define __NR_BSD43_link (__NR_BSD43 + 9) +-#define __NR_BSD43_unlink (__NR_BSD43 + 10) +-#define __NR_BSD43_exec (__NR_BSD43 + 11) +-#define __NR_BSD43_chdir (__NR_BSD43 + 12) +-#define __NR_BSD43_time (__NR_BSD43 + 13) +-#define __NR_BSD43_mknod (__NR_BSD43 + 14) +-#define __NR_BSD43_chmod (__NR_BSD43 + 15) +-#define __NR_BSD43_chown (__NR_BSD43 + 16) +-#define __NR_BSD43_sbreak (__NR_BSD43 + 17) +-#define __NR_BSD43_oldstat (__NR_BSD43 + 18) +-#define __NR_BSD43_lseek (__NR_BSD43 + 19) +-#define __NR_BSD43_getpid (__NR_BSD43 + 20) +-#define __NR_BSD43_oldmount (__NR_BSD43 + 21) +-#define __NR_BSD43_umount (__NR_BSD43 + 22) +-#define __NR_BSD43_setuid (__NR_BSD43 + 23) +-#define __NR_BSD43_getuid (__NR_BSD43 + 24) +-#define __NR_BSD43_stime (__NR_BSD43 + 25) +-#define __NR_BSD43_ptrace (__NR_BSD43 + 26) +-#define __NR_BSD43_alarm (__NR_BSD43 + 27) +-#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) +-#define __NR_BSD43_pause (__NR_BSD43 + 29) +-#define __NR_BSD43_utime (__NR_BSD43 + 30) +-#define __NR_BSD43_stty (__NR_BSD43 + 31) +-#define __NR_BSD43_gtty (__NR_BSD43 + 32) +-#define __NR_BSD43_access (__NR_BSD43 + 33) +-#define __NR_BSD43_nice (__NR_BSD43 + 34) +-#define __NR_BSD43_ftime (__NR_BSD43 + 35) +-#define __NR_BSD43_sync (__NR_BSD43 + 36) +-#define __NR_BSD43_kill (__NR_BSD43 + 37) +-#define __NR_BSD43_stat (__NR_BSD43 + 38) +-#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) +-#define __NR_BSD43_lstat (__NR_BSD43 + 40) +-#define __NR_BSD43_dup (__NR_BSD43 + 41) +-#define __NR_BSD43_pipe (__NR_BSD43 + 42) +-#define __NR_BSD43_times (__NR_BSD43 + 43) +-#define __NR_BSD43_profil (__NR_BSD43 + 44) +-#define __NR_BSD43_msgsys (__NR_BSD43 + 45) +-#define __NR_BSD43_setgid (__NR_BSD43 + 46) +-#define __NR_BSD43_getgid (__NR_BSD43 + 47) +-#define __NR_BSD43_ssig (__NR_BSD43 + 48) +-#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) +-#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) +-#define __NR_BSD43_sysacct (__NR_BSD43 + 51) +-#define __NR_BSD43_phys (__NR_BSD43 + 52) +-#define __NR_BSD43_lock (__NR_BSD43 + 53) +-#define __NR_BSD43_ioctl (__NR_BSD43 + 54) +-#define __NR_BSD43_reboot (__NR_BSD43 + 55) +-#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) +-#define __NR_BSD43_symlink (__NR_BSD43 + 57) +-#define __NR_BSD43_readlink (__NR_BSD43 + 58) +-#define __NR_BSD43_execve (__NR_BSD43 + 59) +-#define __NR_BSD43_umask (__NR_BSD43 + 60) +-#define __NR_BSD43_chroot (__NR_BSD43 + 61) +-#define __NR_BSD43_fstat (__NR_BSD43 + 62) +-#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) +-#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) +-#define __NR_BSD43_mremap (__NR_BSD43 + 65) +-#define __NR_BSD43_vfork (__NR_BSD43 + 66) +-#define __NR_BSD43_vread (__NR_BSD43 + 67) +-#define __NR_BSD43_vwrite (__NR_BSD43 + 68) +-#define __NR_BSD43_sbrk (__NR_BSD43 + 69) +-#define __NR_BSD43_sstk (__NR_BSD43 + 70) +-#define __NR_BSD43_mmap (__NR_BSD43 + 71) +-#define __NR_BSD43_vadvise (__NR_BSD43 + 72) +-#define __NR_BSD43_munmap (__NR_BSD43 + 73) +-#define __NR_BSD43_mprotect (__NR_BSD43 + 74) +-#define __NR_BSD43_madvise (__NR_BSD43 + 75) +-#define __NR_BSD43_vhangup (__NR_BSD43 + 76) +-#define __NR_BSD43_vlimit (__NR_BSD43 + 77) +-#define __NR_BSD43_mincore (__NR_BSD43 + 78) +-#define __NR_BSD43_getgroups (__NR_BSD43 + 79) +-#define __NR_BSD43_setgroups (__NR_BSD43 + 80) +-#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) +-#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) +-#define __NR_BSD43_setitimer (__NR_BSD43 + 83) +-#define __NR_BSD43_wait3 (__NR_BSD43 + 84) +-#define __NR_BSD43_swapon (__NR_BSD43 + 85) +-#define __NR_BSD43_getitimer (__NR_BSD43 + 86) +-#define __NR_BSD43_gethostname (__NR_BSD43 + 87) +-#define __NR_BSD43_sethostname (__NR_BSD43 + 88) +-#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) +-#define __NR_BSD43_dup2 (__NR_BSD43 + 90) +-#define __NR_BSD43_getdopt (__NR_BSD43 + 91) +-#define __NR_BSD43_fcntl (__NR_BSD43 + 92) +-#define __NR_BSD43_select (__NR_BSD43 + 93) +-#define __NR_BSD43_setdopt (__NR_BSD43 + 94) +-#define __NR_BSD43_fsync (__NR_BSD43 + 95) +-#define __NR_BSD43_setpriority (__NR_BSD43 + 96) +-#define __NR_BSD43_socket (__NR_BSD43 + 97) +-#define __NR_BSD43_connect (__NR_BSD43 + 98) +-#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) +-#define __NR_BSD43_getpriority (__NR_BSD43 + 100) +-#define __NR_BSD43_send (__NR_BSD43 + 101) +-#define __NR_BSD43_recv (__NR_BSD43 + 102) +-#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) +-#define __NR_BSD43_bind (__NR_BSD43 + 104) +-#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) +-#define __NR_BSD43_listen (__NR_BSD43 + 106) +-#define __NR_BSD43_vtimes (__NR_BSD43 + 107) +-#define __NR_BSD43_sigvec (__NR_BSD43 + 108) +-#define __NR_BSD43_sigblock (__NR_BSD43 + 109) +-#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) +-#define __NR_BSD43_sigpause (__NR_BSD43 + 111) +-#define __NR_BSD43_sigstack (__NR_BSD43 + 112) +-#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) +-#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) +-#define __NR_BSD43_vtrace (__NR_BSD43 + 115) +-#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) +-#define __NR_BSD43_getrusage (__NR_BSD43 + 117) +-#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) +-#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) +-#define __NR_BSD43_readv (__NR_BSD43 + 120) +-#define __NR_BSD43_writev (__NR_BSD43 + 121) +-#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) +-#define __NR_BSD43_fchown (__NR_BSD43 + 123) +-#define __NR_BSD43_fchmod (__NR_BSD43 + 124) +-#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) +-#define __NR_BSD43_setreuid (__NR_BSD43 + 126) +-#define __NR_BSD43_setregid (__NR_BSD43 + 127) +-#define __NR_BSD43_rename (__NR_BSD43 + 128) +-#define __NR_BSD43_truncate (__NR_BSD43 + 129) +-#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) +-#define __NR_BSD43_flock (__NR_BSD43 + 131) +-#define __NR_BSD43_semsys (__NR_BSD43 + 132) +-#define __NR_BSD43_sendto (__NR_BSD43 + 133) +-#define __NR_BSD43_shutdown (__NR_BSD43 + 134) +-#define __NR_BSD43_socketpair (__NR_BSD43 + 135) +-#define __NR_BSD43_mkdir (__NR_BSD43 + 136) +-#define __NR_BSD43_rmdir (__NR_BSD43 + 137) +-#define __NR_BSD43_utimes (__NR_BSD43 + 138) +-#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) +-#define __NR_BSD43_adjtime (__NR_BSD43 + 140) +-#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) +-#define __NR_BSD43_gethostid (__NR_BSD43 + 142) +-#define __NR_BSD43_sethostid (__NR_BSD43 + 143) +-#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) +-#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) +-#define __NR_BSD43_killpg (__NR_BSD43 + 146) +-#define __NR_BSD43_shmsys (__NR_BSD43 + 147) +-#define __NR_BSD43_quota (__NR_BSD43 + 148) +-#define __NR_BSD43_qquota (__NR_BSD43 + 149) +-#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) +-#define __NR_BSD43_sysmips (__NR_BSD43 + 151) +-#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) +-#define __NR_BSD43_cachectl (__NR_BSD43 + 153) +-#define __NR_BSD43_debug (__NR_BSD43 + 154) +-#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) +-#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) +-#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) +-#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) +-#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) +-#define __NR_BSD43_statfs (__NR_BSD43 + 160) +-#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) +-#define __NR_BSD43_unmount (__NR_BSD43 + 162) +-#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) +-#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) +-#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) +-#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) +-#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) +-#define __NR_BSD43_quotactl (__NR_BSD43 + 168) +-#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) +-#define __NR_BSD43_smount (__NR_BSD43 + 170) +-#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) +-#define __NR_BSD43_exportfs (__NR_BSD43 + 172) +-#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) +-#define __NR_BSD43_libattach (__NR_BSD43 + 174) +-#define __NR_BSD43_libdetach (__NR_BSD43 + 175) +-#define __NR_BSD43_accept (__NR_BSD43 + 176) +-#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) +-#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) +-#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) +-#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) +-#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) +-#define __NR_BSD43_getpeername (__NR_BSD43 + 182) +-#define __NR_BSD43_getsockname (__NR_BSD43 + 183) +-#define __NR_BSD43_aread (__NR_BSD43 + 184) +-#define __NR_BSD43_awrite (__NR_BSD43 + 185) +-#define __NR_BSD43_listio (__NR_BSD43 + 186) +-#define __NR_BSD43_acancel (__NR_BSD43 + 187) +-#define __NR_BSD43_astatus (__NR_BSD43 + 188) +-#define __NR_BSD43_await (__NR_BSD43 + 189) +-#define __NR_BSD43_areadv (__NR_BSD43 + 190) +-#define __NR_BSD43_awritev (__NR_BSD43 + 191) +- +-/* +- * POSIX syscalls are in the range from 3000 to 3999 +- */ +-#define __NR_POSIX 3000 +-#define __NR_POSIX_syscall (__NR_POSIX + 0) +-#define __NR_POSIX_exit (__NR_POSIX + 1) +-#define __NR_POSIX_fork (__NR_POSIX + 2) +-#define __NR_POSIX_read (__NR_POSIX + 3) +-#define __NR_POSIX_write (__NR_POSIX + 4) +-#define __NR_POSIX_open (__NR_POSIX + 5) +-#define __NR_POSIX_close (__NR_POSIX + 6) +-#define __NR_POSIX_wait (__NR_POSIX + 7) +-#define __NR_POSIX_creat (__NR_POSIX + 8) +-#define __NR_POSIX_link (__NR_POSIX + 9) +-#define __NR_POSIX_unlink (__NR_POSIX + 10) +-#define __NR_POSIX_exec (__NR_POSIX + 11) +-#define __NR_POSIX_chdir (__NR_POSIX + 12) +-#define __NR_POSIX_gtime (__NR_POSIX + 13) +-#define __NR_POSIX_mknod (__NR_POSIX + 14) +-#define __NR_POSIX_chmod (__NR_POSIX + 15) +-#define __NR_POSIX_chown (__NR_POSIX + 16) +-#define __NR_POSIX_sbreak (__NR_POSIX + 17) +-#define __NR_POSIX_stat (__NR_POSIX + 18) +-#define __NR_POSIX_lseek (__NR_POSIX + 19) +-#define __NR_POSIX_getpid (__NR_POSIX + 20) +-#define __NR_POSIX_mount (__NR_POSIX + 21) +-#define __NR_POSIX_umount (__NR_POSIX + 22) +-#define __NR_POSIX_setuid (__NR_POSIX + 23) +-#define __NR_POSIX_getuid (__NR_POSIX + 24) +-#define __NR_POSIX_stime (__NR_POSIX + 25) +-#define __NR_POSIX_ptrace (__NR_POSIX + 26) +-#define __NR_POSIX_alarm (__NR_POSIX + 27) +-#define __NR_POSIX_fstat (__NR_POSIX + 28) +-#define __NR_POSIX_pause (__NR_POSIX + 29) +-#define __NR_POSIX_utime (__NR_POSIX + 30) +-#define __NR_POSIX_stty (__NR_POSIX + 31) +-#define __NR_POSIX_gtty (__NR_POSIX + 32) +-#define __NR_POSIX_access (__NR_POSIX + 33) +-#define __NR_POSIX_nice (__NR_POSIX + 34) +-#define __NR_POSIX_statfs (__NR_POSIX + 35) +-#define __NR_POSIX_sync (__NR_POSIX + 36) +-#define __NR_POSIX_kill (__NR_POSIX + 37) +-#define __NR_POSIX_fstatfs (__NR_POSIX + 38) +-#define __NR_POSIX_getpgrp (__NR_POSIX + 39) +-#define __NR_POSIX_syssgi (__NR_POSIX + 40) +-#define __NR_POSIX_dup (__NR_POSIX + 41) +-#define __NR_POSIX_pipe (__NR_POSIX + 42) +-#define __NR_POSIX_times (__NR_POSIX + 43) +-#define __NR_POSIX_profil (__NR_POSIX + 44) +-#define __NR_POSIX_lock (__NR_POSIX + 45) +-#define __NR_POSIX_setgid (__NR_POSIX + 46) +-#define __NR_POSIX_getgid (__NR_POSIX + 47) +-#define __NR_POSIX_sig (__NR_POSIX + 48) +-#define __NR_POSIX_msgsys (__NR_POSIX + 49) +-#define __NR_POSIX_sysmips (__NR_POSIX + 50) +-#define __NR_POSIX_sysacct (__NR_POSIX + 51) +-#define __NR_POSIX_shmsys (__NR_POSIX + 52) +-#define __NR_POSIX_semsys (__NR_POSIX + 53) +-#define __NR_POSIX_ioctl (__NR_POSIX + 54) +-#define __NR_POSIX_uadmin (__NR_POSIX + 55) +-#define __NR_POSIX_exch (__NR_POSIX + 56) +-#define __NR_POSIX_utssys (__NR_POSIX + 57) +-#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) +-#define __NR_POSIX_exece (__NR_POSIX + 59) +-#define __NR_POSIX_umask (__NR_POSIX + 60) +-#define __NR_POSIX_chroot (__NR_POSIX + 61) +-#define __NR_POSIX_fcntl (__NR_POSIX + 62) +-#define __NR_POSIX_ulimit (__NR_POSIX + 63) +-#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) +-#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) +-#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) +-#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) +-#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) +-#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) +-#define __NR_POSIX_advfs (__NR_POSIX + 70) +-#define __NR_POSIX_unadvfs (__NR_POSIX + 71) +-#define __NR_POSIX_rmount (__NR_POSIX + 72) +-#define __NR_POSIX_rumount (__NR_POSIX + 73) +-#define __NR_POSIX_rfstart (__NR_POSIX + 74) +-#define __NR_POSIX_reserved1 (__NR_POSIX + 75) +-#define __NR_POSIX_rdebug (__NR_POSIX + 76) +-#define __NR_POSIX_rfstop (__NR_POSIX + 77) +-#define __NR_POSIX_rfsys (__NR_POSIX + 78) +-#define __NR_POSIX_rmdir (__NR_POSIX + 79) +-#define __NR_POSIX_mkdir (__NR_POSIX + 80) +-#define __NR_POSIX_getdents (__NR_POSIX + 81) +-#define __NR_POSIX_sginap (__NR_POSIX + 82) +-#define __NR_POSIX_sgikopt (__NR_POSIX + 83) +-#define __NR_POSIX_sysfs (__NR_POSIX + 84) +-#define __NR_POSIX_getmsg (__NR_POSIX + 85) +-#define __NR_POSIX_putmsg (__NR_POSIX + 86) +-#define __NR_POSIX_poll (__NR_POSIX + 87) +-#define __NR_POSIX_sigreturn (__NR_POSIX + 88) +-#define __NR_POSIX_accept (__NR_POSIX + 89) +-#define __NR_POSIX_bind (__NR_POSIX + 90) +-#define __NR_POSIX_connect (__NR_POSIX + 91) +-#define __NR_POSIX_gethostid (__NR_POSIX + 92) +-#define __NR_POSIX_getpeername (__NR_POSIX + 93) +-#define __NR_POSIX_getsockname (__NR_POSIX + 94) +-#define __NR_POSIX_getsockopt (__NR_POSIX + 95) +-#define __NR_POSIX_listen (__NR_POSIX + 96) +-#define __NR_POSIX_recv (__NR_POSIX + 97) +-#define __NR_POSIX_recvfrom (__NR_POSIX + 98) +-#define __NR_POSIX_recvmsg (__NR_POSIX + 99) +-#define __NR_POSIX_select (__NR_POSIX + 100) +-#define __NR_POSIX_send (__NR_POSIX + 101) +-#define __NR_POSIX_sendmsg (__NR_POSIX + 102) +-#define __NR_POSIX_sendto (__NR_POSIX + 103) +-#define __NR_POSIX_sethostid (__NR_POSIX + 104) +-#define __NR_POSIX_setsockopt (__NR_POSIX + 105) +-#define __NR_POSIX_shutdown (__NR_POSIX + 106) +-#define __NR_POSIX_socket (__NR_POSIX + 107) +-#define __NR_POSIX_gethostname (__NR_POSIX + 108) +-#define __NR_POSIX_sethostname (__NR_POSIX + 109) +-#define __NR_POSIX_getdomainname (__NR_POSIX + 110) +-#define __NR_POSIX_setdomainname (__NR_POSIX + 111) +-#define __NR_POSIX_truncate (__NR_POSIX + 112) +-#define __NR_POSIX_ftruncate (__NR_POSIX + 113) +-#define __NR_POSIX_rename (__NR_POSIX + 114) +-#define __NR_POSIX_symlink (__NR_POSIX + 115) +-#define __NR_POSIX_readlink (__NR_POSIX + 116) +-#define __NR_POSIX_lstat (__NR_POSIX + 117) +-#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) +-#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) +-#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) +-#define __NR_POSIX_async_daemon (__NR_POSIX + 121) +-#define __NR_POSIX_exportfs (__NR_POSIX + 122) +-#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) +-#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) +-#define __NR_POSIX_getitimer (__NR_POSIX + 125) +-#define __NR_POSIX_setitimer (__NR_POSIX + 126) +-#define __NR_POSIX_adjtime (__NR_POSIX + 127) +-#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) +-#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) +-#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) +-#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) +-#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) +-#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) +-#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) +-#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) +-#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) +-#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) +-#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) +-#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) +-#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) +-#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) +-#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) +-#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) +-#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) +-#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) +-#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) +-#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) +-#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) +-#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) +-#define __NR_POSIX_cacheflush (__NR_POSIX + 150) +-#define __NR_POSIX_cachectl (__NR_POSIX + 151) +-#define __NR_POSIX_fchown (__NR_POSIX + 152) +-#define __NR_POSIX_fchmod (__NR_POSIX + 153) +-#define __NR_POSIX_wait3 (__NR_POSIX + 154) +-#define __NR_POSIX_mmap (__NR_POSIX + 155) +-#define __NR_POSIX_munmap (__NR_POSIX + 156) +-#define __NR_POSIX_madvise (__NR_POSIX + 157) +-#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) +-#define __NR_POSIX_setreuid (__NR_POSIX + 159) +-#define __NR_POSIX_setregid (__NR_POSIX + 160) +-#define __NR_POSIX_setpgid (__NR_POSIX + 161) +-#define __NR_POSIX_getgroups (__NR_POSIX + 162) +-#define __NR_POSIX_setgroups (__NR_POSIX + 163) +-#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) +-#define __NR_POSIX_getrusage (__NR_POSIX + 165) +-#define __NR_POSIX_getrlimit (__NR_POSIX + 166) +-#define __NR_POSIX_setrlimit (__NR_POSIX + 167) +-#define __NR_POSIX_waitpid (__NR_POSIX + 168) +-#define __NR_POSIX_dup2 (__NR_POSIX + 169) +-#define __NR_POSIX_reserved2 (__NR_POSIX + 170) +-#define __NR_POSIX_reserved3 (__NR_POSIX + 171) +-#define __NR_POSIX_reserved4 (__NR_POSIX + 172) +-#define __NR_POSIX_reserved5 (__NR_POSIX + 173) +-#define __NR_POSIX_reserved6 (__NR_POSIX + 174) +-#define __NR_POSIX_reserved7 (__NR_POSIX + 175) +-#define __NR_POSIX_reserved8 (__NR_POSIX + 176) +-#define __NR_POSIX_reserved9 (__NR_POSIX + 177) +-#define __NR_POSIX_reserved10 (__NR_POSIX + 178) +-#define __NR_POSIX_reserved11 (__NR_POSIX + 179) +-#define __NR_POSIX_reserved12 (__NR_POSIX + 180) +-#define __NR_POSIX_reserved13 (__NR_POSIX + 181) +-#define __NR_POSIX_reserved14 (__NR_POSIX + 182) +-#define __NR_POSIX_reserved15 (__NR_POSIX + 183) +-#define __NR_POSIX_reserved16 (__NR_POSIX + 184) +-#define __NR_POSIX_reserved17 (__NR_POSIX + 185) +-#define __NR_POSIX_reserved18 (__NR_POSIX + 186) +-#define __NR_POSIX_reserved19 (__NR_POSIX + 187) +-#define __NR_POSIX_reserved20 (__NR_POSIX + 188) +-#define __NR_POSIX_reserved21 (__NR_POSIX + 189) +-#define __NR_POSIX_reserved22 (__NR_POSIX + 190) +-#define __NR_POSIX_reserved23 (__NR_POSIX + 191) +-#define __NR_POSIX_reserved24 (__NR_POSIX + 192) +-#define __NR_POSIX_reserved25 (__NR_POSIX + 193) +-#define __NR_POSIX_reserved26 (__NR_POSIX + 194) +-#define __NR_POSIX_reserved27 (__NR_POSIX + 195) +-#define __NR_POSIX_reserved28 (__NR_POSIX + 196) +-#define __NR_POSIX_reserved29 (__NR_POSIX + 197) +-#define __NR_POSIX_reserved30 (__NR_POSIX + 198) +-#define __NR_POSIX_reserved31 (__NR_POSIX + 199) +-#define __NR_POSIX_reserved32 (__NR_POSIX + 200) +-#define __NR_POSIX_reserved33 (__NR_POSIX + 201) +-#define __NR_POSIX_reserved34 (__NR_POSIX + 202) +-#define __NR_POSIX_reserved35 (__NR_POSIX + 203) +-#define __NR_POSIX_reserved36 (__NR_POSIX + 204) +-#define __NR_POSIX_reserved37 (__NR_POSIX + 205) +-#define __NR_POSIX_reserved38 (__NR_POSIX + 206) +-#define __NR_POSIX_reserved39 (__NR_POSIX + 207) +-#define __NR_POSIX_reserved40 (__NR_POSIX + 208) +-#define __NR_POSIX_reserved41 (__NR_POSIX + 209) +-#define __NR_POSIX_reserved42 (__NR_POSIX + 210) +-#define __NR_POSIX_reserved43 (__NR_POSIX + 211) +-#define __NR_POSIX_reserved44 (__NR_POSIX + 212) +-#define __NR_POSIX_reserved45 (__NR_POSIX + 213) +-#define __NR_POSIX_reserved46 (__NR_POSIX + 214) +-#define __NR_POSIX_reserved47 (__NR_POSIX + 215) +-#define __NR_POSIX_reserved48 (__NR_POSIX + 216) +-#define __NR_POSIX_reserved49 (__NR_POSIX + 217) +-#define __NR_POSIX_reserved50 (__NR_POSIX + 218) +-#define __NR_POSIX_reserved51 (__NR_POSIX + 219) +-#define __NR_POSIX_reserved52 (__NR_POSIX + 220) +-#define __NR_POSIX_reserved53 (__NR_POSIX + 221) +-#define __NR_POSIX_reserved54 (__NR_POSIX + 222) +-#define __NR_POSIX_reserved55 (__NR_POSIX + 223) +-#define __NR_POSIX_reserved56 (__NR_POSIX + 224) +-#define __NR_POSIX_reserved57 (__NR_POSIX + 225) +-#define __NR_POSIX_reserved58 (__NR_POSIX + 226) +-#define __NR_POSIX_reserved59 (__NR_POSIX + 227) +-#define __NR_POSIX_reserved60 (__NR_POSIX + 228) +-#define __NR_POSIX_reserved61 (__NR_POSIX + 229) +-#define __NR_POSIX_reserved62 (__NR_POSIX + 230) +-#define __NR_POSIX_reserved63 (__NR_POSIX + 231) +-#define __NR_POSIX_reserved64 (__NR_POSIX + 232) +-#define __NR_POSIX_reserved65 (__NR_POSIX + 233) +-#define __NR_POSIX_reserved66 (__NR_POSIX + 234) +-#define __NR_POSIX_reserved67 (__NR_POSIX + 235) +-#define __NR_POSIX_reserved68 (__NR_POSIX + 236) +-#define __NR_POSIX_reserved69 (__NR_POSIX + 237) +-#define __NR_POSIX_reserved70 (__NR_POSIX + 238) +-#define __NR_POSIX_reserved71 (__NR_POSIX + 239) +-#define __NR_POSIX_reserved72 (__NR_POSIX + 240) +-#define __NR_POSIX_reserved73 (__NR_POSIX + 241) +-#define __NR_POSIX_reserved74 (__NR_POSIX + 242) +-#define __NR_POSIX_reserved75 (__NR_POSIX + 243) +-#define __NR_POSIX_reserved76 (__NR_POSIX + 244) +-#define __NR_POSIX_reserved77 (__NR_POSIX + 245) +-#define __NR_POSIX_reserved78 (__NR_POSIX + 246) +-#define __NR_POSIX_reserved79 (__NR_POSIX + 247) +-#define __NR_POSIX_reserved80 (__NR_POSIX + 248) +-#define __NR_POSIX_reserved81 (__NR_POSIX + 249) +-#define __NR_POSIX_reserved82 (__NR_POSIX + 250) +-#define __NR_POSIX_reserved83 (__NR_POSIX + 251) +-#define __NR_POSIX_reserved84 (__NR_POSIX + 252) +-#define __NR_POSIX_reserved85 (__NR_POSIX + 253) +-#define __NR_POSIX_reserved86 (__NR_POSIX + 254) +-#define __NR_POSIX_reserved87 (__NR_POSIX + 255) +-#define __NR_POSIX_reserved88 (__NR_POSIX + 256) +-#define __NR_POSIX_reserved89 (__NR_POSIX + 257) +-#define __NR_POSIX_reserved90 (__NR_POSIX + 258) +-#define __NR_POSIX_reserved91 (__NR_POSIX + 259) +-#define __NR_POSIX_netboot (__NR_POSIX + 260) +-#define __NR_POSIX_netunboot (__NR_POSIX + 261) +-#define __NR_POSIX_rdump (__NR_POSIX + 262) +-#define __NR_POSIX_setsid (__NR_POSIX + 263) +-#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) +-#define __NR_POSIX_sigpending (__NR_POSIX + 265) +-#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) +-#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) +-#define __NR_POSIX_sigaction (__NR_POSIX + 268) +-#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) +-#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) +-#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) +-#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) +-#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) +-#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) +-#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) +-#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) +-#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) +-#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) +-#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) +-#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) +-#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) +-#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) +-#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) +-#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) +-#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) +-#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) +-#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) +-#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) +-#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) +-#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) +-#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) +-#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) +-#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) +-#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) +-#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) +-#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) +-#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) +-#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) +-#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) +-#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) +-#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) +-#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) +-#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) +-#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) +-#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) +-#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) +-#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) +-#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) +-#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) +-#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) +-#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) +-#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) +-#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) +-#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) +-#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) +-#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) +-#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) +-#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) +-#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) +- +-/* +- * Linux syscalls are in the range from 4000 to 4999 +- * Hopefully these syscall numbers are unused ... If not everyone using +- * statically linked binaries is pretty upsh*t. You've been warned. +- */ + #define __NR_Linux 4000 + #define __NR_syscall (__NR_Linux + 0) + #define __NR_exit (__NR_Linux + 1) +@@ -1045,7 +71,7 @@ + #define __NR_mpx (__NR_Linux + 56) + #define __NR_setpgid (__NR_Linux + 57) + #define __NR_ulimit (__NR_Linux + 58) +-#define __NR_oldolduname (__NR_Linux + 59) ++#define __NR_unused59 (__NR_Linux + 59) + #define __NR_umask (__NR_Linux + 60) + #define __NR_chroot (__NR_Linux + 61) + #define __NR_ustat (__NR_Linux + 62) +@@ -1095,7 +121,7 @@ + #define __NR_stat (__NR_Linux + 106) + #define __NR_lstat (__NR_Linux + 107) + #define __NR_fstat (__NR_Linux + 108) +-#define __NR_olduname (__NR_Linux + 109) ++#define __NR_unused109 (__NR_Linux + 109) + #define __NR_iopl (__NR_Linux + 110) + #define __NR_vhangup (__NR_Linux + 111) + #define __NR_idle (__NR_Linux + 112) +@@ -1206,11 +232,12 @@ + #define __NR_mincore (__NR_Linux + 217) + #define __NR_madvise (__NR_Linux + 218) + #define __NR_getdents64 (__NR_Linux + 219) ++#define __NR_fcntl64 (__NR_Linux + 220) + + /* + * Offset of the last Linux flavoured syscall + */ +-#define __NR_Linux_syscalls 219 ++#define __NR_Linux_syscalls 220 + + #ifndef _LANGUAGE_ASSEMBLY + +@@ -1218,13 +245,15 @@ + #define _syscall0(type,name) \ + type name(void) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name) \ +- : "$8","$9","$10","$11","$12","$13","$14","$15","$24"); \ ++ : "$2","$7","$8","$9","$10","$11","$12","$13","$14","$15", \ ++ "$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1238,14 +267,15 @@ + #define _syscall1(type,name,atype,a) \ + type name(atype a) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ +- : "=r" (__res), "=r" (__err) \ +- : "i" (__NR_##name),"r" ((long)(a)) \ +- : "$4","$8","$9","$10","$11","$12","$13","$14","$15","$24"); \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ ++ : "=r" (__res), "=r" (__err) \ ++ : "i" (__NR_##name),"r" ((long)(a)) \ ++ : "$2","$4","$7","$8","$9","$10","$11","$12","$13","$14","$15","$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1255,17 +285,18 @@ + #define _syscall2(type,name,atype,a,btype,b) \ + type name(atype a,btype b) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)) \ +- : "$4","$5","$8","$9","$10","$11","$12","$13","$14","$15", \ +- "$24"); \ ++ : "$2","$4","$5","$7","$8","$9","$10","$11","$12","$13", \ ++ "$14","$15", "$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1275,19 +306,20 @@ + #define _syscall3(type,name,atype,a,btype,b,ctype,c) \ + type name (atype a, btype b, ctype c) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)), \ + "r" ((long)(c)) \ +- : "$4","$5","$6","$8","$9","$10","$11","$12","$13","$14", \ +- "$15","$24"); \ ++ : "$2","$4","$5","$6","$7","$8","$9","$10","$11","$12", \ ++ "$13","$14","$15","$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1297,21 +329,22 @@ + #define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ + type name (atype a, btype b, ctype c, dtype d) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "move\t$7,%6\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)), \ + "r" ((long)(c)), \ + "r" ((long)(d)) \ +- : "$4","$5","$6","$8","$9","$10","$11","$12","$13","$14", \ +- "$15","$24"); \ ++ : "$2","$4","$5","$6","$7","$8","$9","$10","$11","$12", \ ++ "$13","$14","$15","$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1321,8 +354,7 @@ + #define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ + type name (atype a,btype b,ctype c,dtype d,etype e) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ +@@ -1331,7 +363,9 @@ + "subu\t$29,24\n\t" \ + "sw\t$2,16($29)\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall\n\t" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7\n\t" \ + "addiu\t$29,24" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ +@@ -1350,8 +384,7 @@ + #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ + type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ +@@ -1362,7 +395,9 @@ + "sw\t$2,16($29)\n\t" \ + "sw\t$3,20($29)\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall\n\t" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7\n\t" \ + "addiu\t$29,24" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ +@@ -1382,8 +417,7 @@ + #define _syscall7(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f,gtype,g) \ + type name (atype a,btype b,ctype c,dtype d,etype e,ftype f,gtype g) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ +@@ -1396,7 +430,9 @@ + "sw\t$3,20($29)\n\t" \ + "sw\t$2,24($29)\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall\n\t" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7\n\t" \ + "addiu\t$29,32" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ +@@ -1450,4 +486,4 @@ + #endif /* !defined (__KERNEL_SYSCALLS__) */ + #endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +-#endif /* __ASM_MIPS_UNISTD_H */ ++#endif /* _ASM_UNISTD_H */ +diff -ruN linux/include/asm-mips/xxx linux-mips/include/asm-mips/xxx +--- linux/include/asm-mips/xxx Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/xxx Fri Nov 10 00:12:13 2000 +@@ -0,0 +1,187 @@ ++*************** ++*** 174,180 **** ++ extern __inline__ void set_bit(int nr, volatile void * addr) ++ { ++ int mask; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 202,208 ---- ++ extern __inline__ void set_bit(int nr, volatile void * addr) ++ { ++ int mask; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 184,219 **** ++ __bi_restore_flags(flags); ++ } ++ ++- extern __inline__ void clear_bit(int nr, volatile void * addr) ++ { ++ int mask; ++- int *a = addr; ++- __bi_flags; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++- __bi_save_and_cli(flags); ++- *a &= ~mask; ++- __bi_restore_flags(flags); ++ } ++ ++- extern __inline__ void change_bit(int nr, volatile void * addr) ++ { ++ int mask; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ __bi_save_and_cli(flags); ++- *a ^= mask; ++ __bi_restore_flags(flags); ++ } ++ ++ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 212,249 ---- ++ __bi_restore_flags(flags); ++ } ++ +++ extern __inline__ void __set_bit(int nr, volatile void * addr) ++ { ++ int mask; +++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); +++ *a |= mask; ++ } ++ +++ extern __inline__ void clear_bit(int nr, volatile void * addr) ++ { ++ int mask; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ __bi_save_and_cli(flags); +++ *a &= ~mask; ++ __bi_restore_flags(flags); ++ } ++ +++ /* +++ * It will also imply a memory barrier, thus it must clobber memory +++ * to make sure to reload anything that was cached into registers +++ * outside _this_ critical section. +++ */ ++ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 226,235 **** ++ return retval; ++ } ++ ++ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 256,278 ---- ++ return retval; ++ } ++ +++ extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +++ { +++ int mask, retval; +++ volatile int *a = addr; +++ +++ a += nr >> 5; +++ mask = 1 << (nr & 0x1f); +++ retval = (mask & *a) != 0; +++ *a |= mask; +++ +++ return retval; +++ } +++ ++ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 242,251 **** ++ return retval; ++ } ++ ++ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 285,307 ---- ++ return retval; ++ } ++ +++ extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +++ { +++ int mask, retval; +++ volatile int *a = addr; +++ +++ a += nr >> 5; +++ mask = 1 << (nr & 0x1f); +++ retval = (mask & *a) != 0; +++ *a &= ~mask; +++ +++ return retval; +++ } +++ ++ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 259,267 **** ++ } ++ ++ #undef __bi_flags ++- #undef __bi_cli() ++- #undef __bi_save_flags(x) ++- #undef __bi_restore_flags(x) ++ ++ #endif /* MIPS I */ ++ ++--- 315,323 ---- ++ } ++ ++ #undef __bi_flags +++ #undef __bi_cli +++ #undef __bi_save_flags +++ #undef __bi_restore_flags ++ ++ #endif /* MIPS I */ ++ +diff -ruN linux/include/linux/pci_ids.h linux-mips/include/linux/pci_ids.h +--- linux/include/linux/pci_ids.h Thu Nov 23 15:51:51 2000 ++++ linux-mips/include/linux/pci_ids.h Fri Nov 10 00:17:29 2000 +@@ -318,6 +318,7 @@ + #define PCI_VENDOR_ID_NEC 0x1033 + #define PCI_DEVICE_ID_NEC_PCX2 0x0046 + #define PCI_DEVICE_ID_NEC_NILE4 0x005a ++#define PCI_DEVICE_ID_NEC_VRC5476 0x009b + + #define PCI_VENDOR_ID_FD 0x1036 + #define PCI_DEVICE_ID_FD_36C70 0x0000 +diff -ruN linux/include/linux/sched.h linux-mips/include/linux/sched.h +--- linux/include/linux/sched.h Thu Nov 23 15:51:51 2000 ++++ linux-mips/include/linux/sched.h Fri Nov 10 00:17:40 2000 +@@ -552,6 +552,8 @@ + extern int in_group_p(gid_t); + extern int in_egroup_p(gid_t); + ++extern void release(struct task_struct * p); ++ + extern void proc_caches_init(void); + extern void flush_signals(struct task_struct *); + extern void flush_signal_handlers(struct task_struct *); |