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Commit message (
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Author
Age
Files
Lines
*
New port: cad/archimedes: Semiconductor device simulation software
Yuri Victorovich
2020-12-10
1
-0
/
+1
*
New port: cad/stm32flash: Flash program for STM32 using the ST serial bootloader
Yuri Victorovich
2020-11-18
1
-0
/
+1
*
New port: cad/ecpprog: Driver for FTDI based JTAG probes, to program ECP5 FPGAs
Yuri Victorovich
2020-09-16
1
-0
/
+1
*
cad/opensta: Remove because it is now included in OpenRoad (cad/openroad)
Yuri Victorovich
2020-09-15
1
-1
/
+0
*
New port: cad/openroad: ASIC physical design tool
Yuri Victorovich
2020-09-14
1
-0
/
+1
*
Clean up some things
Tobias Kortkamp
2020-08-18
1
-0
/
+3
*
New port: cad/openfpgaloader: Universal utility for programming FPGA
Yuri Victorovich
2020-08-11
1
-0
/
+1
*
New port: cad/horizon-eda: EDA package for printed circuit board design
Yuri Victorovich
2020-08-07
1
-0
/
+1
*
[NEW PORT] cad/py-ezdxf: Create and modify DXF drawings
Loïc Bartoletti
2020-07-30
1
-0
/
+1
*
cad/meshlab: Resurrect, update to 2020.05 and take maintainer'ship
Loïc Bartoletti
2020-07-18
1
-0
/
+1
*
[NEW PORT] cad/ifcopenshell: Open source IFC library and geometry engine
Loïc Bartoletti
2020-05-23
1
-0
/
+1
*
This is the new, shiny frontend for Cura. Check daid/LegacyCura for the
Diane Bruce
2020-03-26
1
-0
/
+1
*
Uranium is a Python framework for building 3D printing related applications.
Diane Bruce
2020-03-25
1
-0
/
+1
*
In preparation for Cura updates add the FDM material database
Diane Bruce
2020-03-25
1
-0
/
+1
*
New port: cad/opensta: Gate level static timing verifier
Yuri Victorovich
2020-03-23
1
-0
/
+1
*
New port: cad/graywolf: Fork of TimberWolf, a placement tool in VLSI design
Yuri Victorovich
2020-03-22
1
-0
/
+1
*
New port: cad/qflow: End-to-end digital synthesis flow for ASIC designs
Yuri Victorovich
2020-03-22
1
-0
/
+1
*
New port: cad/qrouter: Tool to generate metal layers and vias
Yuri Victorovich
2020-03-19
1
-0
/
+1
*
New port: cad/netgen-lvs: Tool for comparing netlists (a process known as LVS)
Yuri Victorovich
2020-03-19
1
-0
/
+1
*
OpenCTM is a file format, a software library and a tool set for compression
Diane Bruce
2020-03-15
1
-0
/
+1
*
Remove expired ports:
Rene Ladan
2020-03-01
1
-1
/
+0
*
Remove expired ports, all Python-2.7-only:
Rene Ladan
2020-02-22
1
-1
/
+0
*
New port: cad/veroroute: PCB (printed circuit board) design software
Yuri Victorovich
2020-02-02
1
-0
/
+1
*
Remove expired ports:
Rene Ladan
2020-01-27
1
-1
/
+0
*
sort SUBDIRs.
Mathieu Arnold
2020-01-24
1
-1
/
+1
*
New port: cad/PrusaSlicer
Eugene Grosbein
2020-01-24
1
-0
/
+1
*
Move cad/elmerfem -> science/elmerfem
Yuri Victorovich
2020-01-15
1
-1
/
+0
*
Remove expired ports:
Rene Ladan
2020-01-10
1
-1
/
+0
*
Move cad/ujprog -> comms/ujprog
Yuri Victorovich
2020-01-06
1
-1
/
+0
*
New port: cad/ujprog: ULX2S/ULX3S FPGA JTAG programmer
Yuri Victorovich
2020-01-06
1
-0
/
+1
*
New/resurrected port: cad/gerbv
Kurt Jaeger
2020-01-05
1
-0
/
+1
*
New port: cad/cascade-compiler: Just-In-Time Compiler for Verilog from VMware...
Yuri Victorovich
2020-01-05
1
-0
/
+1
*
Move the port devel/yosys -> cad/yosys, to the proper category
Yuri Victorovich
2020-01-04
1
-0
/
+1
*
New port: cad/ktechlab: IDE for microcontrollers and electronics
Yuri Victorovich
2019-11-27
1
-0
/
+1
*
Re-add cad/oregano: Schematic capture and circuit simulator
Yuri Victorovich
2019-11-23
1
-0
/
+1
*
New port: cad/librepcb: Schematic and PCB editing software
Yuri Victorovich
2019-11-23
1
-0
/
+1
*
New port: cad/caneda: EDA software suite focused on ease of use and portability
Yuri Victorovich
2019-11-21
1
-0
/
+1
*
- Resurrect `cad/elmerfem' and update to version 8.4
Alexey Dokuchaev
2019-11-11
1
-0
/
+1
*
- Chase r517198 and reconnect `cad/brlcad' to the build
Alexey Dokuchaev
2019-11-10
1
-0
/
+1
*
cad/fasm: Make PKGBASE unique
Yuri Victorovich
2019-10-27
1
-0
/
+1
*
Remove port with duplicate PKGBASE
Antoine Brodin
2019-10-27
1
-1
/
+0
*
New port: cad/fasm: FPGA assembly (FASM) parser and generator
Yuri Victorovich
2019-10-27
1
-0
/
+1
*
New port: cad/nvc: VHDL compiler and simulator
Yuri Victorovich
2019-10-23
1
-0
/
+1
*
Re-add cad/ghdl: GNU VHDL simulator
Yuri Victorovich
2019-10-23
1
-0
/
+1
*
Remove expired ports:
Rene Ladan
2019-10-16
1
-3
/
+0
*
Remove expired port:
Rene Ladan
2019-08-12
1
-1
/
+0
*
New port: cad/digital: Digital logic designer and circuit simulator
Yuri Victorovich
2019-07-22
1
-0
/
+1
*
cad/kicad-doc: online help files and documentation for cad/kicad
Christoph Moench-Tegeder
2019-06-21
1
-0
/
+1
*
Re-add cad/leocad
Yuri Victorovich
2019-05-18
1
-0
/
+1
*
Remove epxired ports:
Rene Ladan
2019-05-13
1
-1
/
+0
[next]