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* FreeCAD is an OpenSource CAD/CAE, based on OpenCasCade, QT and Python.Thierry Thomas2007-05-261-0/+1
| | | | | | | | | | | | | | | It features some key concepts like macro recording, workbenches, ability to run as a server and dynamically loadable application extensions and it is designed to be platform independent. Warning: FreeCAD is still in ALPHA state and not in shape for end user usage! <http://juergen-riegel.net/FreeCAD/Docu/> Suggested by: Pedro F. Giffuni <giffunip (at) yahoo.com> Notes: svn path=/head/; revision=191927
* GDT (graphics data text) format translator written in C/C++ thatHiroki Sato2007-04-291-0/+1
| | | | | | | | converts a binary gdsii file to a text format that is compact and easy to parse. Notes: svn path=/head/; revision=191098
* p5-GDS2, a Perl module for quickly creating programs to read and/orHiroki Sato2007-04-291-0/+1
| | | | | | | write GDS2 files. Notes: svn path=/head/; revision=191096
* KLayout is a Qt-based GDS2 viewer.Hiroki Sato2007-04-281-0/+1
| | | | Notes: svn path=/head/; revision=191075
* FindHier is a road-map generator for Magic/CIF/gdsII/PCSTR/GED/TeX.Hiroki Sato2007-04-281-0/+1
| | | | | | | | | | | ---When you have a large number of or big layout/schematic/TeX files which have possibly many top cells made by other people, how can you manage those layout/schematic/TeXs? FH is written for that. It can be useful up to your imagination or shell programming skill. FH analyses the hidden hierarchies of those cells and shows you the hierarchy information. Notes: svn path=/head/; revision=191070
* GDSreader is a simple Calma (GDSii) parser/printer tool.Hiroki Sato2007-04-281-0/+1
| | | | Notes: svn path=/head/; revision=191068
* 2007-04-12 cad/geda-projectmanager: project deadMartin Wilke2007-04-231-1/+0
| | | | | | | 2007-04-19 audio/xmpeg3: does not work Notes: svn path=/head/; revision=190695
* A Qt based application for tutorial to Open CASCADE Technology.Thierry Thomas2007-04-011-0/+1
| | | | Notes: svn path=/head/; revision=188920
* Open CASCADE Technology is a software development platform freely available inThierry Thomas2007-04-011-0/+1
| | | | | | | | | | | | | | | open source. It includes components for 3D surface and solid modeling, visualization, data exchange and rapid application development. Open CASCADE Technology can be best applied in development of numerical simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM applications. BUGS: the module WOK does not work, but the other modules (the most interesting parts) are OK. Notes: svn path=/head/; revision=188917
* The SystemC Verification (SCV) library is an extension library to SystemCMartin Wilke2006-12-221-0/+1
| | | | | | | | | | | | | | | which adds advanced verification capabilities to SystemC, including constrained randomization, complex constraint solvers, data-structure creation, Transaction Level Modeling (TLM), concurrency, and dynamic resource allocation management. WWW: http://www.systemc.org/ PR: ports/106822 Submitted by: Peter Johnson Notes: svn path=/head/; revision=180469
* The goals of the FreeHDL project are to develop a VHDL simulator that hasAlejandro Pulver2006-11-051-0/+1
| | | | | | | | | | | | | a graphical waveform viewer and a source level debugger. It also aims at VHDL-93 compliancy. The project is at a very early development stage. WWW: http://www.freehdl.seul.org/ PR: ports/104634 Submitted by: lon_kamikaze at gmx.de Notes: svn path=/head/; revision=176541
* Electric is a sophisticated electrical CAD system that can handleStanislav Sedov2006-09-301-0/+1
| | | | | | | | | | | | | | | | | many forms of circuit design, including: - Custom IC layout (ASICs) - Schematic drawing - Hardware description language specifications Author: Static Free Software & Sun Microsystems, Inc. WWW: http://www.staticfreesoft.com/ PR: ports/100355 Submitted by: me (stas) Approved by: sem (mentor) Notes: svn path=/head/; revision=174152
* This port provides a GUI for two freely available SPICE electronic circuitIon-Mihai Tetcu2006-08-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | simulation engines: GNU-Cap and Ng-Spice. Current features: Import gschem schematic files using gentlist. Load and parse circuit description (net list) files. Provides a GUI interface for GNU-Cap OP, DC, AC and Transient analyses and generates appropriate simulator commands based on user input. Provides a GUI interface for Ng-Spice DC, AC and Transient analyses and generates appropriate simulator commands based on user input. The raw output may be viewed for any processes initiated by gspiceui. Formatting of simulator output so that it may be plotted using gwave. WWW: http://www.geda.seul.org/tools/gspiceui/index.html PR: ports/99357 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru> Notes: svn path=/head/; revision=169394
* ADMS is a code generator that converts electrical compact device modelsIon-Mihai Tetcu2006-07-291-0/+1
| | | | | | | | | | | | | specified in high-level description language into ready-to-compile c code for the API of spice simulators. WWW: http://mot-adms.sourceforge.net/ PR: ports/101014 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru> Notes: svn path=/head/; revision=169094
* - gschem -> geda-gschemRong-En Fan2006-07-161-2/+2
| | | | | | | | | | - gnetlist -> geda-netlist PR: ports/100222, ports/100230 Submitted by: maintainer Notes: svn path=/head/; revision=167956
* Jspice3 is a circuit simulator developed to meet the needs of researchersIon-Mihai Tetcu2006-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability. WWW: http://www.wrcad.com/jspice3.html PR: ports/93958 Submitted by: Pedro F. Giffuni Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it. Notes: svn path=/head/; revision=167526
* Various examples for gEDA suite. This includes:Renato Botelho2006-07-041-0/+1
| | | | | | | | | | | | | | | 1) gTAG - USB to JTAG interface 2) lightning_detector - a lightning detector 3) RF_Amp - schematics and associated materials for a SPICE model 4) TwoStageAmp - a two stage amplifier SPICE playpen WWW: http://www.geda.seul.org PR: ports/99564 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> Notes: svn path=/head/; revision=166922
* Various documentation for gEDA suite, including architecture-relatedRenato Botelho2006-07-041-0/+1
| | | | | | | | | | | | docs as well as examples of usage and tutorials. WWW: http://www.geda.seul.org PR: ports/99565 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> Notes: svn path=/head/; revision=166920
* The gEDA project manager suite.Pav Lucistnik2006-06-261-0/+1
| | | | | | | | | | WWW: http://www.geda.seul.org PR: ports/99481 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> Notes: svn path=/head/; revision=166406
* Gattrib is gEDA's attribute editor.Pav Lucistnik2006-06-261-0/+1
| | | | | | | | | | WWW: http://www.geda.seul.org PR: ports/99480 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> Notes: svn path=/head/; revision=166403
* TclSpice is an improved version of Berkeley Spice designed to be used withPav Lucistnik2006-06-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | the Tcl/Tk scripting language. The project is open-source (BSD license) and based upon the NG-Spice source code base with many improvements Features and Improvements - Fully Tcl scriptable - installs with 'package require spice' statement - Hspice syntax (SpicePP). - GUI interfaces, various (Tk). - SpiceWish (BLT graph widget) - BLT (tcl compatible) vectors for storage, manipulation and arithmetic upon Spice waveforms. - Xspice additions (Georgia Tech). - Trigger upon waveform events. - Spice 'simulator state' save and restore for rapid 'what-if' simulations (no longer need to re-simulate from the beginning each time a device value is changed). Author: Stefan Jones <stefan.jones@multigig.com> WWW: http://tclspice.sourceforge.net/ PR: ports/99399 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> Notes: svn path=/head/; revision=166388
* Add feappv 2.0, finite Element Analysis Program "personal version".Thierry Thomas2006-04-031-0/+1
| | | | | | | | | | | | | | | | This is a FEA program used in a classic FEM book. A complete (commercial) version is available here: <http://www.ce.berkeley.edu/~rlt/feap/> The "personal version" is very limited, but it keeps the same format as the complete (commercial) version and cad/netgen can produce files for it. PR: ports/95210 Submitted by: Pedro F. Giffuni <giffunip (at) asme.org> Notes: svn path=/head/; revision=158739
* SCOTCH is a software package and libraries for graph, mesh and hypergraphThierry Thomas2006-02-031-0/+1
| | | | | | | | | | | | | | | partitioning, static mapping, and sparse matrix block ordering. Its purpose of Scotch is to apply graph theory, with a divide and conquer approach, to scientific computing problems such as graph and mesh partitioning, static mapping, and sparse matrix ordering, in application domains ranging from structural mechanics to operating systems or bio-chemistry. Note: there is an older tarball included in Aster's distfile, but I prefer a separate distfile from the official site. Notes: svn path=/head/; revision=155160
* [NEW PORT] cad/gplcver: A Verilog HDL simulatorEdwin Groothuis2005-12-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw> Notes: svn path=/head/; revision=152326
* Add systemc 2.1.v1, a modeling platform for system-level C++ models.Sam Lawrance2005-12-181-0/+1
| | | | | | | | PR: ports/89987 Submitted by: Daniel Thiele Notes: svn path=/head/; revision=151479
* Add Kicad, a software for the creation of electronic schematicThierry Thomas2005-12-081-0/+1
| | | | | | | | | | | | | | | diagrams and printed circuit board artwork. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager. Notes: svn path=/head/; revision=150689
* Remove expired portsKris Kennaway2005-11-051-1/+0
| | | | Notes: svn path=/head/; revision=147349
* Move recently added port cad/fig2sxd to a new and more accurate categoryRenato Botelho2005-09-081-1/+0
| | | | | | | | | | graphics, with extra category converters. Pointed by: danfe Approved by: maintainer Notes: svn path=/head/; revision=142227
* Add fig2sxd 0.13, convert .xfig files to the OpenOffice draw format.Renato Botelho2005-09-081-0/+1
| | | | | | | | PR: ports/85794 Submitted by: Emanuel Haupt <ehaupt@critical.ch> Notes: svn path=/head/; revision=142216
* Graphical circuit design and simulation tool.Dag-Erling Smørgrav2005-06-111-0/+1
| | | | Notes: svn path=/head/; revision=137272
* Add linux-gid 7.4.9b,Simon Barner2005-03-161-0/+1
| | | | | | | | | | | | a graphical pre- and post-processor for numerical simulation programs. PR: ports/78383 Submitted by: Pedro Giffuni Approved by: arved (mentor) Notes: svn path=/head/; revision=131394
* add impact 0.5.3Ying-Chieh Liao2005-03-041-0/+1
| | | | | | | Dynamic Finite Element Program Suite Notes: svn path=/head/; revision=130327
* Add brlcad 7.0.4, CSG modelling system from the US BalisticThierry Thomas2005-02-201-0/+1
| | | | | | | | | | Research Laboratory. PR: 76122 Submitted by: Pedro F. Giffuni Notes: svn path=/head/; revision=129418
* Add z88 11.0, a compact Finite Element Analysis System.Thierry Thomas2005-01-221-0/+1
| | | | | | | | PR: 75698 Submitted by: Pedro F. Giffuni. Notes: svn path=/head/; revision=127103
* Add triangle 1.5, a Two-Dimensional Quality Mesh Generator andThierry Thomas2004-11-151-1/+0
| | | | | | | | | | | | Delaunay Triangulator. Change category from cad to math. Requested by: Pedro F. Giffuni Approved by: marcus Notes: svn path=/head/; revision=121715
* Add triangle 1.5, a Two-Dimensional Quality Mesh Generator andThierry Thomas2004-11-151-0/+1
| | | | | | | Delaunay Triangulator. Notes: svn path=/head/; revision=121650
* add dxf2fig 2.07Ying-Chieh Liao2004-08-261-0/+1
| | | | | | | DXF to FIG converter Notes: svn path=/head/; revision=117302
* Add dinotrace, a mature signal waveform viewer used to debug digital designPav Lucistnik2004-07-051-0/+1
| | | | | | | | | | simulations. PR: ports/68688 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se> Notes: svn path=/head/; revision=113000
* Add cad/alliance, which is a complete set of free CAD tools andHiroki Sato2004-05-131-0/+1
| | | | | | | | | | | portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, automatic place and route tools, and portable CMOS libraries. Approved by: linimon (mentor) Notes: svn path=/head/; revision=109077
* Add netgen 4.3.1, an automatic 3D tetrahedral mesh generator.Thierry Thomas2004-05-051-0/+1
| | | | Notes: svn path=/head/; revision=108482
* Remove category pkg/COMMENT files in favour of a COMMENT variable in theKris Kennaway2004-04-021-0/+2
| | | | | | | | | | category makefile. Submitted by: Matthew Seaman <m.seaman@infracaninophile.co.uk> PR: 59651 Notes: svn path=/head/; revision=105948
* add qcad-partslib the parts-library for qcad.Michael Reifenberger2004-03-281-0/+1
| | | | Notes: svn path=/head/; revision=105493
* Reorder those filesMathieu Arnold2004-03-201-1/+1
| | | | Notes: svn path=/head/; revision=104767
* add fandango 0.2.5Ying-Chieh Liao2004-02-201-0/+1
| | | | | | | A python scripted 3D CAD application Notes: svn path=/head/; revision=101449
* . Remove metis-edf after a repo copy to the math category.Greg Lewis2003-12-091-1/+0
| | | | | | | | PR: 58178 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> Notes: svn path=/head/; revision=95488
* add pythoncad release 10Ying-Chieh Liao2003-11-121-0/+1
| | | | | | | An open-source CAD package built designed around Python Notes: svn path=/head/; revision=93776
* . Remove kaskade port after repo copy to math category.Greg Lewis2003-11-081-1/+0
| | | | | | | | PR: 58178 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> Notes: svn path=/head/; revision=93386
* . Remove felt port now its been repo copied to the science category.Greg Lewis2003-11-081-1/+0
| | | | | | | | PR: 58178 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> Notes: svn path=/head/; revision=93380
* NEW port CAD/admeshEdwin Groothuis2003-10-101-0/+1
| | | | | | | | | | A tool to analyze STL (stereolitholigraphy) files. PR: ports/52997 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> Notes: svn path=/head/; revision=90740
* As announced on May 6, remove the broken sis port.Kris Kennaway2003-08-081-1/+0
| | | | Notes: svn path=/head/; revision=86541
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