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* - Get Rid MD5 supportMartin Wilke2011-03-201-1/+0
| | | | Notes: svn path=/head/; revision=271346
* - Update to 3.251Sylvio Cesar Teixeira2010-07-233-7/+9
| | | | | | | | PR: ports/148726 Submitted by: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer) Notes: svn path=/head/; revision=258101
* - Update to 3.223Philip M. Gollucci2010-01-182-4/+4
| | | | | | | | | PR: ports/142626 Submitted by: myself (pgollucci@) Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer) Notes: svn path=/head/; revision=248046
* - Update to 3.222Philip M. Gollucci2009-12-272-4/+4
| | | | | | | | | PR: ports/141552 Approved by: maintainer Submitted by: myself (pgollucci@) Notes: svn path=/head/; revision=246738
* - Update to 3.221Martin Wilke2009-11-043-7/+9
| | | | | | | | PR: 140231 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer) Notes: svn path=/head/; revision=243787
* - Fix compile problem with over optimization caused by -O2 flag for gcc in baseAndrej Zverev2009-09-151-3/+8
| | | | | | | | | | | prior OSVERSION 700042 - Unbreak Approved by: portmgr (miwi) Feature safe: yes Notes: svn path=/head/; revision=241459
* - mark BROKEN does not compileMartin Wilke2009-09-141-0/+2
| | | | Notes: svn path=/head/; revision=241366
* Update to 2.213Andrej Zverev2009-08-242-4/+4
| | | | | | | | PR: ports/138081 Submitted by: tacilio.net at ee.ufcg.edu.br (maintainer) Notes: svn path=/head/; revision=240246
* - Update to 2.11Philip M. Gollucci2009-07-153-34/+36
| | | | | | | | PR: ports/136485 Submitted by: otacilio.neto@ee.ufcg.edu.br (maintainer) Notes: svn path=/head/; revision=237842
* - Add missing dependency (bison)Renato Botelho2009-05-261-0/+1
| | | | | | | | Reported by: QAT Pointyhat to: garga Notes: svn path=/head/; revision=234578
* The Verilog-Perl library is a building point for Verilog support in the PerlRenato Botelho2009-05-264-0/+97
language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br> Notes: svn path=/head/; revision=234576
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