src-test/contrib/llvm/lib, branch main

Move all sources from the llvm project into contrib/llvm-project.

2019-12-20T19:53:05Z

This uses the new layout of the upstream repository, which was recently migrated to GitHub, and converted into a "monorepo". That is, most of the earlier separate sub-projects with their own branches and tags were consolidated into one top-level directory, and are now branched and tagged together. Updating the vendor area to match this layout is next.

Merge commit 241cbf201 from llvm git (by Nemanja Ivanovic):

2019-12-04T18:38:50Z

[PowerPC] Fix crash in peephole optimization When converting reg+reg shifts to reg+imm rotates, we neglect to consider the CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a rotate with missing operands which causes a crash. Committing this fix without review since it is non-controversial that the list of mnemonics to consider should include the 64-bit aliases for the exact mnemonics. Fixes PR44183. This should fix "Assertion failed: (idx < size()), function operator[], file /usr/src/contrib/llvm/include/llvm/ADT/SmallVector.h, line 153" when building the graphics/mesa-dri port for the PowerPC64 ELFv2 ABI. Reported by: Alfredo Dal'Ava Júnior MFC after: 1 month X-MFC-With: r353358

Merge commit bf996f761 from llvm git (by Simon Atanasyan):

2019-11-21T20:25:12Z

[mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` section Differential Revision: https://reviews.llvm.org/D69851 This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358

Merge commit 3718102d4 from llvm git (by Simon Atanasyan):

2019-11-21T20:23:35Z

[mips] Support `octeon+` CPU in the `.set arch=` directive Differential Revision: https://reviews.llvm.org/D69850 This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358

Merge commit 7bed381ea from llvm git (by Simon Atanasyan):

2019-11-21T20:22:07Z

[mips] Implement Octeon+ `saa` and `saad` instructions `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849 This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358

Merge commit 5bbb604bb from llvm git (by Craig Topper):

2019-11-15T06:56:25Z

[InstCombine] Disable some portions of foldGEPICmp for GEPs that return a vector of pointers. Fix other portions. llvm-svn: 370114 This should fix instances of 'Assertion failed: (isa(Val) && "cast() argument of incompatible type!"), function cast, file /usr/src/contrib/llvm/include/llvm/Support/Casting.h, line 255', when building openjdk8 for aarch64 and armv7. Reported by: jbeich PR: 236566 MFC after: 3 days

llvm: use elf_aux_info to get executable's path, if available

2019-11-14T15:10:01Z

Obtained from: LLVM a0a38b81ea MFC with: r354692 Sponsored by: The FreeBSD Foundation

llvm: use AT_EXECPATH from ELF auxiliary vectors for getExecutablePath

2019-11-13T21:02:18Z

/proc/curproc/file and the KERN_PROC_PATHNAME sysctl may not return the desired path if there are multiple hardlinks to the file. PR: 241932 Tested by: ler Sponsored by: The FreeBSD Foundation

Merge commit f596f4507 from llvm git (by Sam Elliott):

2019-11-07T19:54:08Z

[RISCV] Add Custom Parser for Atomic Memory Operands Summary: GCC Accepts both (reg) and 0(reg) for atomic instruction memory operands. These instructions do not allow for an offset in their encoding, so in the latter case, the 0 is silently dropped. Due to how we have structured the RISCVAsmParser, the easiest way to add support for parsing this offset is to add a custom AsmOperand and parser. This parser drops all the parens, and just keeps the register. This commit also adds a custom printer for these operands, which matches the GCC canonical printer, printing both `(a0)` and `0(a0)` as `(a0)`. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: s.egerton, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65205 llvm-svn: 367553 Merge commit f596f4507 from llvm git (by Sam Elliott): [RISCV] Add FreeBSD targets Reviewers: asb Reviewed By: asb Subscribers: simoncook, s.egerton, lenary, psnobl, benna, mhorne, emaste, kito-cheng, shiva0217, rogfer01, rkruppe, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57795 Patch by James Clarke (jrtc27) llvm-svn: 367557 Merge commit f596f4507 from llvm git (by Hsiangkai Wang): [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524 Merge commit f596f4507 from llvm git (by Hsiangkai Wang): [DebugInfo] Some fields do not need relocations even relax is enabled. In debug frame information, some fields, e.g., Length in CIE/FDE and Offset in FDE are attributes to describe the structure of CIE/FDE. They are not related to the relaxed code. However, these attributes are symbol differences. So, in current design, these attributes will be filled as zero and LLVM generates relocations for them. We only need to generate relocations for symbols in executable sections. So, if the symbols are not located in executable sections, we still evaluate their values under relaxation. Differential Revision: https://reviews.llvm.org/D61584 llvm-svn: 366531 Merge commit f596f4507 from llvm git (by Alex Bradbury): [RISCV] Don't force absolute FK_Data_X fixups to relocs The current behavior of shouldForceRelocation forces relocations for the majority of fixups when relaxation is enabled. This makes sense for fixups which incorporate symbols but is unnecessary for simple data fixups where the fixup target is already resolved to an absolute value. Differential Revision: https://reviews.llvm.org/D63404 Patch by Edward Jones. llvm-svn: 369257 Merge commit f596f4507 from llvm git (by Alex Bradbury): [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit , the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375 This series of merges will permit riscv64 kernels and riscv64sf worlds to build with clang instead of gcc (but still using the bfd linker). Requested by: jhb Obtained from: https://github.com/freebsd/freebsd/compare/master...bsdjhb:riscv_clang MFC after: 1 month X-MFC-With: r353358

Merge commit 8e34dd941 from llvm git (by Sanjay Patel):

2019-11-07T06:59:09Z

[x86] avoid crashing when splitting AVX stores with non-simple type (PR43916) The store splitting transform was assuming a simple type (MVT), but that's not necessarily the case as shown in the test. This should fix 'Assertion failed: (isSimple() && "Expected a SimpleValueType!")' when building the security/openssl111 port targeting a CPU that supports AVX, but not AVX2, such as sandybridge. PR: 241747 MFC after: 1 month X-MFC-With: r353358