FreeBSD source tree https://cgit-dev.freebsd.org/src-test/atom?h=main 2020-09-01T21:43:05Z 2020-09-01T21:43:05Z Mateusz Guzik mjg@FreeBSD.org 2020-09-01T21:43:05Z urn:sha1:ab3fad6ea26bda380ecb9ddc3bc4e9014ab3d4b2 2017-12-14T01:58:05Z Landon J. Fuller landonf@FreeBSD.org 2017-12-14T01:58:05Z urn:sha1:566ca880a1361331e9dfd340bf39d6f14238151d the expected default board_vendor value on MIPS SoCs. This is required by bwn(4) to differentiate between single-band and dual-band device variants that otherwise share a common chip ID. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation 2017-12-08T15:57:29Z Pedro F. Giffuni pfg@FreeBSD.org 2017-12-08T15:57:29Z urn:sha1:6e778a7efdc0e804471750157f6bacd1ef7d1580 2017-11-27T22:29:35Z Landon J. Fuller landonf@FreeBSD.org 2017-11-27T22:29:35Z urn:sha1:3fcd245ef1b9b0f378cc5680838b8d9173518da9 BUS_PROBE_NOMATCH(). Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation 2017-11-22T20:27:46Z Landon J. Fuller landonf@FreeBSD.org 2017-11-22T20:27:46Z urn:sha1:4e96bf3a37e326dcb741f289d8adfac8884cca78 The bwn(4) driver requires a number of extensions to the bhnd(4) PMU interface to support external configuration of PLLs, LDOs, and other parameters that require chipset or PHY-specific workarounds. These changes add support for: - Writing raw voltage register values to PHY-specific LDO regulator registers (required by LP-PHY). - Enabling/disabling PHY-specific LDOs (required by LP-PHY) - Writing to arbitrary PMU chipctrl registers (required for common PHY PLL reset support). - Requesting chipset/PLL-specific spurious signal avoidance modes. - Querying clock frequency and latency. Additionally, rather than updating legacy PWRCTL support to conform to the new PMU interface: - PWRCTL API is now provided by a bhnd_pwrctl_if.m interface. - Since PWRCTL is only found in older SSB-based chipsets, translation from bhnd(4) bus APIs to corresponding PWRCTL operations is now handled entirely within the siba(4) driver. - The PWRCTL-specific host bridge clock gating APIs in bhnd_bus_if.m have been lifted out into a standalone bhnd_pwrctl_hostb_if.m interface. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12664 2017-11-21T23:15:20Z Landon J. Fuller landonf@FreeBSD.org 2017-11-21T23:15:20Z urn:sha1:caeff9a3c2626660d3e080d4d3b35bc53ec4417f On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518 2017-09-27T19:44:23Z Landon J. Fuller landonf@FreeBSD.org 2017-09-27T19:44:23Z urn:sha1:8e35bf8319f3f087abd63079aa5b8820e5f837b4 Add bhnd(4) API for explicitly registering BHND platform devices (ChipCommon, PMU, NVRAM, etc) with the bus, rather than walking the newbus hierarchy to discover platform devices. These devices are now also refcounted; attempting to deregister an actively used platform device will return EBUSY. This resolves a lock ordering incompatibility with bwn(4)'s firmware loading threads; previously it was necessary to acquire Giant to protect newbus access when locating and querying the NVRAM device. Approved by: adrian (mentor) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12392 2016-09-24T04:08:16Z Landon J. Fuller landonf@FreeBSD.org 2016-09-24T04:08:16Z urn:sha1:8a03f98a8bbbfe45211330f7634c93321ba34813 - Added bhnd(4) bus APIs for per-core ioctl/iost register access. - Updated reset/suspend bhnd(4) APIs for compatibility with ioctl/iost changes. - Implemented core reset/suspend support for both bcma(4) and siba(4). - Implemented explicit release of all outstanding PMU requests at the bus level when putting a core into reset. Approved by: adrian (mentor, implicit) Differential Revision: https://reviews.freebsd.org/D8009 2016-09-05T22:11:46Z Landon J. Fuller landonf@FreeBSD.org 2016-09-05T22:11:46Z urn:sha1:824b48eff36156b1d9adbb7372b26f2b853fb310 This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit) 2016-08-27T00:03:02Z Landon J. Fuller landonf@FreeBSD.org 2016-08-27T00:03:02Z urn:sha1:f90f4b65322a1d76ae934c5aa9e2bfbc2d9f5477 - Added bhnd_pmu driver implementations for PMU and PWRCTL chipsets, derived from Broadcom's ISC-licensed HND code. - Added bhnd bus-level support for routing per-core clock and resource power requests to the PMU device. - Lift ChipCommon support out into the bhnd module, dropping bhnd_chipc. Reviewed by: mizhka Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D7492