FreeBSD source tree https://cgit-dev.freebsd.org/src-test/atom?h=main 2020-05-20T11:20:45Z 2020-05-20T11:20:45Z Konstantin Belousov kib@FreeBSD.org 2020-05-20T11:20:45Z urn:sha1:d0a4068359b4934af67add550fecd52f5691f35c Reviewed by: hselasky Sponsored by: Mellanox Technologies MFC after: 3 days 2020-05-20T11:10:10Z Konstantin Belousov kib@FreeBSD.org 2020-05-20T11:10:10Z urn:sha1:6418350cf4c9dad3d13de5ac1123d739bdc87091 Reviewed by: hselasky Sponsored by: Mellanox Technologies MFC after: 3 days 2020-03-18T22:38:57Z Konstantin Belousov kib@FreeBSD.org 2020-03-18T22:38:57Z urn:sha1:8982c8003b9bd98d448951c67f114085e55bddc3 Reviewed by: hselasky Sponsored by: Mellanox Technologies MFC after: 2 weeks 2019-12-06T15:36:32Z Hans Petter Selasky hselasky@FreeBSD.org 2019-12-06T15:36:32Z urn:sha1:7272f9cd774c4643a33d92db6cc3e1641ceab5c9 ConnectX-6 DX. Currently TLS v1.2 and v1.3 with AES 128/256 crypto over TCP/IP (v4 and v6) is supported. A per PCI device UMA zone is used to manage the memory of the send tags. To optimize performance some crypto contexts may be cached by the UMA zone, until the UMA zone finishes the memory of the given send tag. An asynchronous task is used manage setup of the send tags towards the firmware. Most importantly setting the AES 128/256 bit pre-shared keys for the crypto context. Updating the state of the AES crypto engine and encrypting data, is all done in the fast path. Each send tag tracks the TCP sequence number in order to detect non-contiguous blocks of data, which may require a dump of prior unencrypted data, to restore the crypto state prior to wire transmission. Statistics counters have been added to count the amount of TLS data transmitted in total, and the amount of TLS data which has been dumped prior to transmission. When non-contiguous TCP sequence numbers are detected, the software needs to dump the beginning of the current TLS record up until the point of retransmission. All TLS counters utilize the counter(9) API. In order to enable hardware TLS offload the following sysctls must be set: kern.ipc.mb_use_ext_pgs=1 kern.ipc.tls.ifnet.permitted=1 kern.ipc.tls.enable=1 Sponsored by: Mellanox Technologies 2019-12-05T15:16:19Z Hans Petter Selasky hselasky@FreeBSD.org 2019-12-05T15:16:19Z urn:sha1:04f1690bf0f7cf363abdf4257a64f23eb4b26f7d The hardware offload is primarily targeted for TLS v1.2 and v1.3, using AES 128/256 bit pre-shared keys. This patch adds all the needed hardware structures, capabilites and firmware commands. Sponsored by: Mellanox Technologies 2019-10-02T10:53:28Z Hans Petter Selasky hselasky@FreeBSD.org 2019-10-02T10:53:28Z urn:sha1:59efbf791dd0b498f68e4fe9d1751e1ce930b632 Before attempting to initialize the command interface we must wait till the fw_initializing bit is clear. If we fail to meet this condition the hardware will drop our configuration, specifically the descriptors page address. This scenario can happen when the firmware is still executing an FLR flow and did not finish yet so the driver needs to wait for that to finish. Linux commits: 6c780a0267b8 b8a92577f4be. MFC after: 3 days Sponsored by: Mellanox Technologies 2019-10-02T10:22:15Z Hans Petter Selasky hselasky@FreeBSD.org 2019-10-02T10:22:15Z urn:sha1:96425f44c9ba6dae76157fdf759841d5d1afed8b in mlx5en(4). MFC after: 3 days Sponsored by: Mellanox Technologies 2019-10-02T09:29:55Z Hans Petter Selasky hselasky@FreeBSD.org 2019-10-02T09:29:55Z urn:sha1:111b57c3592fe91e2a3c0a1d5ff301ff26d53dbc While at it, fixup PME based on latest PRM defines. Submitted by: slavash@ MFC after: 3 days Sponsored by: Mellanox Technologies 2019-05-08T11:04:40Z Hans Petter Selasky hselasky@FreeBSD.org 2019-05-08T11:04:40Z urn:sha1:939c79a2132f66dd5abdb62ddc534a77db5819dd Submitted by: kib@ MFC after: 3 days Sponsored by: Mellanox Technologies 2019-05-08T10:58:06Z Hans Petter Selasky hselasky@FreeBSD.org 2019-05-08T10:58:06Z urn:sha1:adb6fd50c8ebe502fa53e4a6eb413b9f3e8acaf8 Implement a watchdog as part of the healtcare subsystem which reads the PCI power status during startup and upon the PCI power status change event and store it into the core device structure. This value is then exported to user-space via a read-only SYSCTL. A dmesg print has been added to inform the admin about the PCI power status. MFC after: 3 days Sponsored by: Mellanox Technologies