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<title>src-test/sys/dev/mlx5/driver.h, branch main</title>
<subtitle>FreeBSD source tree</subtitle>
<id>https://cgit-dev.freebsd.org/src-test/atom?h=main</id>
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<updated>2020-11-16T10:15:03Z</updated>
<entry>
<title>Make mlx5_cmd_exec_cb() a safe API in mlx5core.</title>
<updated>2020-11-16T10:15:03Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2020-11-16T10:15:03Z</published>
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<id>urn:sha1:7eefcb5eead518d9db75411beece922618587297</id>
<content type='text'>
APIs that have deferred callbacks should have some kind of cleanup
function that callers can use to fence the callbacks. Otherwise things
like module unloading can lead to dangling function pointers, or worse.

The IB MR code is the only place that calls this function and had a
really poor attempt at creating this fence. Provide a good version in
the core code as future patches will add more places that need this
fence.

Linux commit:
e355477ed9e4f401e3931043df97325d38552d54

MFC after:	1 week
Sponsored by:	Mellanox Technologies // NVIDIA Networking
</content>
</entry>
<entry>
<title>Report EQE data upon CQ completion in mlx5core.</title>
<updated>2020-11-16T10:10:53Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2020-11-16T10:10:53Z</published>
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<id>urn:sha1:f34f0a65b2223db5f307a0e6d376e1cf89623da6</id>
<content type='text'>
Report EQE data upon CQ completion to let upper layers use this data.

Linux commit:
4e0e2ea1886afe8c001971ff767f6670312a9b04

MFC after:	1 week
Sponsored by:	Mellanox Technologies // NVIDIA Networking
</content>
</entry>
<entry>
<title>mlx5_core: Import PDDR register definitions</title>
<updated>2020-08-31T16:23:51Z</updated>
<author>
<name>Konstantin Belousov</name>
<email>kib@FreeBSD.org</email>
</author>
<published>2020-08-31T16:23:51Z</published>
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<id>urn:sha1:e088db5eaec5b43e1effc7edb82b37c4a0ff0282</id>
<content type='text'>
PDDR (Port Diagnostics Database Register) is used to read the physical
layer debug database, which contains helpful troubleshooting information
regarding the state of the link.

PDDR register can only be queried when PCAM register reports it as
supported in its register mask. A new helper macro was added to
the MLX5_CAP_* infrastructure in order to access this mask.

Sponsored by:	Mellanox Technologies - Nvidia
MFC after:	1 week
</content>
</entry>
<entry>
<title>mlx5: Restore eswitch management code from attic.</title>
<updated>2020-03-18T22:30:56Z</updated>
<author>
<name>Konstantin Belousov</name>
<email>kib@FreeBSD.org</email>
</author>
<published>2020-03-18T22:30:56Z</published>
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<id>urn:sha1:91ad1bd953596f716eaac964954f58f5d4bda039</id>
<content type='text'>
Reviewed by:	hselasky
Sponsored by:	Mellanox Technologies
MFC after:	2 weeks
</content>
</entry>
<entry>
<title>Add support for disabling and polling MSIX interrupts in mlx5core.</title>
<updated>2020-02-12T09:58:19Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2020-02-12T09:58:19Z</published>
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<id>urn:sha1:f14d849862946c8bc241b901706929a2920005e8</id>
<content type='text'>
MFC after:	1 week
Sponsored by:	Mellanox Technologies
</content>
</entry>
<entry>
<title>Widen EPOCH(9) usage in mlx5en(4).</title>
<updated>2020-01-30T12:35:13Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2020-01-30T12:35:13Z</published>
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<id>urn:sha1:e48813009c6adbc8b461d24074ab3e926d9ae3df</id>
<content type='text'>
Make completion event path mostly lockless using EPOCH(9).

Implement a mechanism using EPOCH(9) which allows us to make
the callback path for completion events mostly lockless.

Simplify draining callback events using epoch_wait().

While at it make sure all receive completion callbacks are
covered by the network EPOCH(9), because this is required
when calling if_input() and ether_input() after r357012.

Sponsored by:	Mellanox Technologies
</content>
</entry>
<entry>
<title>mlx5: Do not poke hardware for statistic after teardown is started.</title>
<updated>2019-12-05T15:21:13Z</updated>
<author>
<name>Konstantin Belousov</name>
<email>kib@FreeBSD.org</email>
</author>
<published>2019-12-05T15:21:13Z</published>
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<id>urn:sha1:0cf6ff0a77b1a123168976b8fa40d4fe63332f53</id>
<content type='text'>
Sponsored by:	Mellanox Technologies
MFC after:	1 week
</content>
</entry>
<entry>
<title>Add sysctl(8) to get and set forward error correction, FEC, configuration</title>
<updated>2019-10-02T10:22:15Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2019-10-02T10:22:15Z</published>
<link rel='alternate' type='text/html' href='https://cgit-dev.freebsd.org/src-test/commit/?id=96425f44c9ba6dae76157fdf759841d5d1afed8b'/>
<id>urn:sha1:96425f44c9ba6dae76157fdf759841d5d1afed8b</id>
<content type='text'>
in mlx5en(4).

MFC after:	3 days
Sponsored by:	Mellanox Technologies
</content>
</entry>
<entry>
<title>Add definition for the Port Buffer Status Register in mlx5core.</title>
<updated>2019-10-02T09:57:12Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2019-10-02T09:57:12Z</published>
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<id>urn:sha1:207ff00e26b68b4ababdb95c26c50dce4c09a3cc</id>
<content type='text'>
Submitted by:	kib@
MFC after:	3 days
Sponsored by:	Mellanox Technologies
</content>
</entry>
<entry>
<title>Sort the ports registers definitions numerically in mlx5core.</title>
<updated>2019-10-02T09:56:27Z</updated>
<author>
<name>Hans Petter Selasky</name>
<email>hselasky@FreeBSD.org</email>
</author>
<published>2019-10-02T09:56:27Z</published>
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<id>urn:sha1:8ae1c36f8b5afddd4a5ab04d3fe6fa03bfc80174</id>
<content type='text'>
Submitted by:	kib@
MFC after:	3 days
Sponsored by:	Mellanox Technologies
</content>
</entry>
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