src-test/sys/dev/xilinx, branch main

RISC-V: fix some mismatched format specifiers

2020-09-08T13:21:13Z

RISC-V is currently built with -Wno-format, which is how these went undetected. Address them now before re-enabling those warnings. Differential Revision: https://reviews.freebsd.org/D26319

xilinx: clean up empty lines in .c and .h files

2020-09-01T21:44:42Z

Enter the network epoch in the xdma interrupt handler if required

2020-02-08T23:07:29Z

by a peripheral device driver. Sponsored by: DARPA, AFRL

Fix xae(4) driver attachement on the Government Furnished Equipment (GFE)

2020-02-07T14:36:28Z

riscv cores. GFE cores come with standard DTS file that lacks standard 'dmas =' property, which means xae(4) could not find a DMA controller to use. The 'dmas' property could not be added to the DTS file because the ethernet controller and DMA engine parts in Linux are implemented in a single driver. Instead of 'dmas' property the standard Xilinx 'axistream-connected' property is provided, so fallback to use it instead. Suggested by: James Clarke Reviewed by: James Clarke Sponsored by: DARPA, AFRL

Add driver for Xilinx XDMA PCIe Bridge found in the U.S. Government

2020-01-29T16:52:12Z

Furnished Equipment (GFE) riscv cores. GFE cores are synthesized on the Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Kit. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D23337

Convert to if_foreach_llmaddr() KPI.

2019-10-21T18:12:58Z

Negate the logic of XCHAN_CAP_NOBUFS macro and rename it to

2019-07-04T14:04:08Z

XCHAN_CAP_BOUNCE. The only application that uses bounce buffering for now is the Government Furnished Equipment (GFE) P2's dma core (AXIDMA) with its own dedicated cacheless bounce buffer. Sponsored by: DARPA, AFRL

Add driver for the Xilinx AXI Direct Memory Access (AXI DMA) controller

2019-05-08T15:43:17Z

found in the U.S. Government Furnished Equipment (GFE) 64-bit RISC-V cores. Sponsored by: DARPA, AFRL

Add driver for Xilinx AXI Ethernet tri-mode (10/100/1000 Mb/s) MAC found

2019-05-08T15:36:57Z

in the U.S. Government Furnished Equipment (GFE) 64-bit RISC-V cores. Sponsored by: DARPA, AFRL

ofw_spi: Parse property for the SPI mode and CS polarity.

2016-12-18T14:54:20Z

As cs is stored in a uint32_t, use the last bit to store the active high flag as it's unlikely that we will have that much CS. Reviewed by: loos MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D8614