13 files changed, 305 insertions, 294 deletions

diff --git a/sys/amd64/amd64/exception.S b/sys/amd64/amd64/exception.S
index a7b457415a494..611a895fd1b3d 100644
--- a/sys/amd64/amd64/exception.S
+++ b/sys/amd64/amd64/exception.S
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.16 1996/04/12 12:22:14 phk Exp $
+ *	$Id: exception.s,v 1.17 1996/05/02 09:34:20 phk Exp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -41,6 +41,7 @@
 #include <machine/trap.h>			/* trap codes */
 #include <sys/syscall.h>			/* syscall numbers */
 #include <machine/asmacros.h>			/* miscellaneous macros */
+#include <sys/cdefs.h>				/* CPP macros */
 
 #define	KDSEL		0x10			/* kernel data selector */
 #define	SEL_RPL_MASK	0x0003
@@ -54,7 +55,7 @@
 /*
  * Trap and fault vector routines
  */
-#define	IDTVEC(name)	ALIGN_TEXT ; .globl _X/**/name ; _X/**/name:
+#define	IDTVEC(name)	ALIGN_TEXT; .globl __CONCAT(_X,name); __CONCAT(_X,name):
 #define	TRAP(a)		pushl $(a) ; jmp _alltraps
 
 /*
@@ -69,8 +70,8 @@
 	testb	$SEL_RPL_MASK,4(%esp) ; \
 	jne	1f ; \
 	ss ; \
-	.globl	bdb_/**/name/**/_ljmp ; \
-bdb_/**/name/**/_ljmp: ; \
+	.globl	__CONCAT(__CONCAT(bdb_,name),_ljmp); \
+__CONCAT(__CONCAT(bdb_,name),_ljmp): \
 	ljmp	$0,$0 ; \
 1:
 #else
@@ -123,8 +124,8 @@ IDTVEC(fpu)
 	 * interrupts, but now it is fairly easy - mask nested ones the
 	 * same as SWI_AST's.
 	 */
-	pushl	$0				/* dumby error code */
-	pushl	$0				/* dumby trap type */
+	pushl	$0				/* dummy error code */
+	pushl	$0				/* dummy trap type */
 	pushal
 	pushl	%ds
 	pushl	%es				/* now the stack frame is a trap frame */
diff --git a/sys/amd64/amd64/exception.s b/sys/amd64/amd64/exception.s
index a7b457415a494..611a895fd1b3d 100644
--- a/sys/amd64/amd64/exception.s
+++ b/sys/amd64/amd64/exception.s
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.16 1996/04/12 12:22:14 phk Exp $
+ *	$Id: exception.s,v 1.17 1996/05/02 09:34:20 phk Exp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -41,6 +41,7 @@
 #include <machine/trap.h>			/* trap codes */
 #include <sys/syscall.h>			/* syscall numbers */
 #include <machine/asmacros.h>			/* miscellaneous macros */
+#include <sys/cdefs.h>				/* CPP macros */
 
 #define	KDSEL		0x10			/* kernel data selector */
 #define	SEL_RPL_MASK	0x0003
@@ -54,7 +55,7 @@
 /*
  * Trap and fault vector routines
  */
-#define	IDTVEC(name)	ALIGN_TEXT ; .globl _X/**/name ; _X/**/name:
+#define	IDTVEC(name)	ALIGN_TEXT; .globl __CONCAT(_X,name); __CONCAT(_X,name):
 #define	TRAP(a)		pushl $(a) ; jmp _alltraps
 
 /*
@@ -69,8 +70,8 @@
 	testb	$SEL_RPL_MASK,4(%esp) ; \
 	jne	1f ; \
 	ss ; \
-	.globl	bdb_/**/name/**/_ljmp ; \
-bdb_/**/name/**/_ljmp: ; \
+	.globl	__CONCAT(__CONCAT(bdb_,name),_ljmp); \
+__CONCAT(__CONCAT(bdb_,name),_ljmp): \
 	ljmp	$0,$0 ; \
 1:
 #else
@@ -123,8 +124,8 @@ IDTVEC(fpu)
 	 * interrupts, but now it is fairly easy - mask nested ones the
 	 * same as SWI_AST's.
 	 */
-	pushl	$0				/* dumby error code */
-	pushl	$0				/* dumby trap type */
+	pushl	$0				/* dummy error code */
+	pushl	$0				/* dummy trap type */
 	pushal
 	pushl	%ds
 	pushl	%es				/* now the stack frame is a trap frame */
diff --git a/sys/amd64/amd64/support.S b/sys/amd64/amd64/support.S
index 1dbf8ee180cac..0d5bc5dd3f7c8 100644
--- a/sys/amd64/amd64/support.S
+++ b/sys/amd64/amd64/support.S
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: support.s,v 1.34 1996/05/02 14:19:53 phk Exp $
+ *	$Id: support.s,v 1.35 1996/05/03 21:01:00 phk Exp $
  */
 
 #include "assym.s"				/* system definitions */
@@ -74,11 +74,11 @@ ENTRY(i486_bzero)
 	movl	4(%esp),%edx
 	movl	8(%esp),%ecx
 	xorl	%eax,%eax
-/
-/ do 64 byte chunks first
-/
-/ XXX this is probably over-unrolled at least for DX2's
-/
+/*
+ * do 64 byte chunks first
+ *
+ * XXX this is probably over-unrolled at least for DX2's
+ */
 2:
 	cmpl	$64,%ecx
 	jb	3f
@@ -103,9 +103,9 @@ ENTRY(i486_bzero)
 	jnz	2b
 	ret
 
-/
-/ do 16 byte chunks
-/
+/*
+ * do 16 byte chunks
+ */
 	SUPERALIGN_TEXT
 3:
 	cmpl	$16,%ecx
@@ -119,9 +119,9 @@ ENTRY(i486_bzero)
 	jnz	3b
 	ret
 
-/
-/ do 4 byte chunks
-/
+/*
+ * do 4 byte chunks
+ */
 	SUPERALIGN_TEXT
 4:
 	cmpl	$4,%ecx
@@ -132,12 +132,12 @@ ENTRY(i486_bzero)
 	jnz	4b
 	ret
 
-/
-/ do 1 byte chunks
-/ a jump table seems to be faster than a loop or more range reductions
-/
-/ XXX need a const section for non-text
-/
+/*
+ * do 1 byte chunks
+ * a jump table seems to be faster than a loop or more range reductions
+ *
+ * XXX need a const section for non-text
+ */
 	SUPERALIGN_TEXT
 jtab:
 	.long	do0
diff --git a/sys/amd64/amd64/support.s b/sys/amd64/amd64/support.s
index 1dbf8ee180cac..0d5bc5dd3f7c8 100644
--- a/sys/amd64/amd64/support.s
+++ b/sys/amd64/amd64/support.s
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: support.s,v 1.34 1996/05/02 14:19:53 phk Exp $
+ *	$Id: support.s,v 1.35 1996/05/03 21:01:00 phk Exp $
  */
 
 #include "assym.s"				/* system definitions */
@@ -74,11 +74,11 @@ ENTRY(i486_bzero)
 	movl	4(%esp),%edx
 	movl	8(%esp),%ecx
 	xorl	%eax,%eax
-/
-/ do 64 byte chunks first
-/
-/ XXX this is probably over-unrolled at least for DX2's
-/
+/*
+ * do 64 byte chunks first
+ *
+ * XXX this is probably over-unrolled at least for DX2's
+ */
 2:
 	cmpl	$64,%ecx
 	jb	3f
@@ -103,9 +103,9 @@ ENTRY(i486_bzero)
 	jnz	2b
 	ret
 
-/
-/ do 16 byte chunks
-/
+/*
+ * do 16 byte chunks
+ */
 	SUPERALIGN_TEXT
 3:
 	cmpl	$16,%ecx
@@ -119,9 +119,9 @@ ENTRY(i486_bzero)
 	jnz	3b
 	ret
 
-/
-/ do 4 byte chunks
-/
+/*
+ * do 4 byte chunks
+ */
 	SUPERALIGN_TEXT
 4:
 	cmpl	$4,%ecx
@@ -132,12 +132,12 @@ ENTRY(i486_bzero)
 	jnz	4b
 	ret
 
-/
-/ do 1 byte chunks
-/ a jump table seems to be faster than a loop or more range reductions
-/
-/ XXX need a const section for non-text
-/
+/*
+ * do 1 byte chunks
+ * a jump table seems to be faster than a loop or more range reductions
+ *
+ * XXX need a const section for non-text
+ */
 	SUPERALIGN_TEXT
 jtab:
 	.long	do0
diff --git a/sys/amd64/include/asmacros.h b/sys/amd64/include/asmacros.h
index 98633543ded3f..4ecabdf5f2d0c 100644
--- a/sys/amd64/include/asmacros.h
+++ b/sys/amd64/include/asmacros.h
@@ -30,13 +30,14 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: asmacros.h,v 1.6 1995/12/29 15:28:53 bde Exp $
+ *	$Id: asmacros.h,v 1.7 1996/03/31 04:17:25 bde Exp $
  */
 
 #ifndef _MACHINE_ASMACROS_H_
 #define _MACHINE_ASMACROS_H_
 
 #ifdef KERNEL
+#include <sys/cdefs.h>
 
 /* XXX too much duplication in various asm*.h's and gprof.h's */
 
@@ -44,7 +45,7 @@
 #define ALIGN_TEXT	.align	2,0x90	/* 4-byte alignment, nop filled */
 #define SUPERALIGN_TEXT	.align	4,0x90	/* 16-byte alignment (better for 486), nop filled */
 
-#define GEN_ENTRY(name)		ALIGN_TEXT; .globl _/**/name; _/**/name:
+#define GEN_ENTRY(name)		ALIGN_TEXT; .globl __CONCAT(_,name); __CONCAT(_,name):
 #define NON_GPROF_ENTRY(name)	GEN_ENTRY(name)
 
 #ifdef GPROF
diff --git a/sys/amd64/isa/vector.S b/sys/amd64/isa/vector.S
index a5056afa851e3..94691f5f7f184 100644
--- a/sys/amd64/isa/vector.S
+++ b/sys/amd64/isa/vector.S
@@ -1,6 +1,6 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: vector.s,v 1.18 1996/03/31 03:31:29 bde Exp $
+ *	$Id: vector.s,v 1.19 1996/04/11 21:18:47 bde Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -98,10 +98,10 @@
  * loading segregs.
  */
 
-#define	FAST_INTR(irq_num, enable_icus) \
+#define	FAST_INTR(irq_num, vec_name, enable_icus) \
 	.text ; \
 	SUPERALIGN_TEXT ; \
-IDTVEC(fastintr/**/irq_num) ; \
+IDTVEC(vec_name) ; \
 	pushl	%eax ;		/* save only call-used registers */ \
 	pushl	%ecx ; \
 	pushl	%edx ; \
@@ -153,12 +153,12 @@ IDTVEC(fastintr/**/irq_num) ; \
 	MEXITCOUNT ; \
 	jmp	_doreti
 
-#define	INTR(irq_num, icu, enable_icus, reg) \
+#define	INTR(irq_num, vec_name, icu, enable_icus, reg) \
 	.text ; \
 	SUPERALIGN_TEXT ; \
-IDTVEC(intr/**/irq_num) ; \
-	pushl	$0 ;		/* dumby error code */ \
-	pushl	$0 ;		/* dumby trap type */ \
+IDTVEC(vec_name) ; \
+	pushl	$0 ;		/* dummy error code */ \
+	pushl	$0 ;		/* dummy trap type */ \
 	pushal ; \
 	pushl	%ds ;		/* save our data and extra segments ... */ \
 	pushl	%es ; \
@@ -175,7 +175,7 @@ IDTVEC(intr/**/irq_num) ; \
 	testb	$IRQ_BIT(irq_num),%reg ; \
 	jne	2f ; \
 	incb	_intr_nesting_level ; \
-Xresume/**/irq_num: ; \
+__CONCAT(Xresume,irq_num): ; \
 	FAKE_MCOUNT(12*4(%esp)) ;	/* XXX late to avoid double count */ \
 	movl	_intr_countp + (irq_num) * 4,%eax ; \
 	incl	(%eax) ; \
@@ -208,38 +208,38 @@ Xresume/**/irq_num: ; \
 	iret
 
 MCOUNT_LABEL(bintr)
-	FAST_INTR(0, ENABLE_ICU1)
-	FAST_INTR(1, ENABLE_ICU1)
-	FAST_INTR(2, ENABLE_ICU1)
-	FAST_INTR(3, ENABLE_ICU1)
-	FAST_INTR(4, ENABLE_ICU1)
-	FAST_INTR(5, ENABLE_ICU1)
-	FAST_INTR(6, ENABLE_ICU1)
-	FAST_INTR(7, ENABLE_ICU1)
-	FAST_INTR(8, ENABLE_ICU1_AND_2)
-	FAST_INTR(9, ENABLE_ICU1_AND_2)
-	FAST_INTR(10, ENABLE_ICU1_AND_2)
-	FAST_INTR(11, ENABLE_ICU1_AND_2)
-	FAST_INTR(12, ENABLE_ICU1_AND_2)
-	FAST_INTR(13, ENABLE_ICU1_AND_2)
-	FAST_INTR(14, ENABLE_ICU1_AND_2)
-	FAST_INTR(15, ENABLE_ICU1_AND_2)
-	INTR(0, IO_ICU1, ENABLE_ICU1, al)
-	INTR(1, IO_ICU1, ENABLE_ICU1, al)
-	INTR(2, IO_ICU1, ENABLE_ICU1, al)
-	INTR(3, IO_ICU1, ENABLE_ICU1, al)
-	INTR(4, IO_ICU1, ENABLE_ICU1, al)
-	INTR(5, IO_ICU1, ENABLE_ICU1, al)
-	INTR(6, IO_ICU1, ENABLE_ICU1, al)
-	INTR(7, IO_ICU1, ENABLE_ICU1, al)
-	INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	FAST_INTR(0,fastintr0, ENABLE_ICU1)
+	FAST_INTR(1,fastintr1, ENABLE_ICU1)
+	FAST_INTR(2,fastintr2, ENABLE_ICU1)
+	FAST_INTR(3,fastintr3, ENABLE_ICU1)
+	FAST_INTR(4,fastintr4, ENABLE_ICU1)
+	FAST_INTR(5,fastintr5, ENABLE_ICU1)
+	FAST_INTR(6,fastintr6, ENABLE_ICU1)
+	FAST_INTR(7,fastintr7, ENABLE_ICU1)
+	FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
+	FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
+	FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
+	FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
+	FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
+	FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
+	FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
+	FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
+	INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al)
+	INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al)
+	INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al)
+	INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al)
+	INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al)
+	INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al)
+	INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al)
+	INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al)
+	INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
 MCOUNT_LABEL(eintr)
 
 	.data
diff --git a/sys/amd64/isa/vector.s b/sys/amd64/isa/vector.s
index a5056afa851e3..94691f5f7f184 100644
--- a/sys/amd64/isa/vector.s
+++ b/sys/amd64/isa/vector.s
@@ -1,6 +1,6 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: vector.s,v 1.18 1996/03/31 03:31:29 bde Exp $
+ *	$Id: vector.s,v 1.19 1996/04/11 21:18:47 bde Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -98,10 +98,10 @@
  * loading segregs.
  */
 
-#define	FAST_INTR(irq_num, enable_icus) \
+#define	FAST_INTR(irq_num, vec_name, enable_icus) \
 	.text ; \
 	SUPERALIGN_TEXT ; \
-IDTVEC(fastintr/**/irq_num) ; \
+IDTVEC(vec_name) ; \
 	pushl	%eax ;		/* save only call-used registers */ \
 	pushl	%ecx ; \
 	pushl	%edx ; \
@@ -153,12 +153,12 @@ IDTVEC(fastintr/**/irq_num) ; \
 	MEXITCOUNT ; \
 	jmp	_doreti
 
-#define	INTR(irq_num, icu, enable_icus, reg) \
+#define	INTR(irq_num, vec_name, icu, enable_icus, reg) \
 	.text ; \
 	SUPERALIGN_TEXT ; \
-IDTVEC(intr/**/irq_num) ; \
-	pushl	$0 ;		/* dumby error code */ \
-	pushl	$0 ;		/* dumby trap type */ \
+IDTVEC(vec_name) ; \
+	pushl	$0 ;		/* dummy error code */ \
+	pushl	$0 ;		/* dummy trap type */ \
 	pushal ; \
 	pushl	%ds ;		/* save our data and extra segments ... */ \
 	pushl	%es ; \
@@ -175,7 +175,7 @@ IDTVEC(intr/**/irq_num) ; \
 	testb	$IRQ_BIT(irq_num),%reg ; \
 	jne	2f ; \
 	incb	_intr_nesting_level ; \
-Xresume/**/irq_num: ; \
+__CONCAT(Xresume,irq_num): ; \
 	FAKE_MCOUNT(12*4(%esp)) ;	/* XXX late to avoid double count */ \
 	movl	_intr_countp + (irq_num) * 4,%eax ; \
 	incl	(%eax) ; \
@@ -208,38 +208,38 @@ Xresume/**/irq_num: ; \
 	iret
 
 MCOUNT_LABEL(bintr)
-	FAST_INTR(0, ENABLE_ICU1)
-	FAST_INTR(1, ENABLE_ICU1)
-	FAST_INTR(2, ENABLE_ICU1)
-	FAST_INTR(3, ENABLE_ICU1)
-	FAST_INTR(4, ENABLE_ICU1)
-	FAST_INTR(5, ENABLE_ICU1)
-	FAST_INTR(6, ENABLE_ICU1)
-	FAST_INTR(7, ENABLE_ICU1)
-	FAST_INTR(8, ENABLE_ICU1_AND_2)
-	FAST_INTR(9, ENABLE_ICU1_AND_2)
-	FAST_INTR(10, ENABLE_ICU1_AND_2)
-	FAST_INTR(11, ENABLE_ICU1_AND_2)
-	FAST_INTR(12, ENABLE_ICU1_AND_2)
-	FAST_INTR(13, ENABLE_ICU1_AND_2)
-	FAST_INTR(14, ENABLE_ICU1_AND_2)
-	FAST_INTR(15, ENABLE_ICU1_AND_2)
-	INTR(0, IO_ICU1, ENABLE_ICU1, al)
-	INTR(1, IO_ICU1, ENABLE_ICU1, al)
-	INTR(2, IO_ICU1, ENABLE_ICU1, al)
-	INTR(3, IO_ICU1, ENABLE_ICU1, al)
-	INTR(4, IO_ICU1, ENABLE_ICU1, al)
-	INTR(5, IO_ICU1, ENABLE_ICU1, al)
-	INTR(6, IO_ICU1, ENABLE_ICU1, al)
-	INTR(7, IO_ICU1, ENABLE_ICU1, al)
-	INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	FAST_INTR(0,fastintr0, ENABLE_ICU1)
+	FAST_INTR(1,fastintr1, ENABLE_ICU1)
+	FAST_INTR(2,fastintr2, ENABLE_ICU1)
+	FAST_INTR(3,fastintr3, ENABLE_ICU1)
+	FAST_INTR(4,fastintr4, ENABLE_ICU1)
+	FAST_INTR(5,fastintr5, ENABLE_ICU1)
+	FAST_INTR(6,fastintr6, ENABLE_ICU1)
+	FAST_INTR(7,fastintr7, ENABLE_ICU1)
+	FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
+	FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
+	FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
+	FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
+	FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
+	FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
+	FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
+	FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
+	INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al)
+	INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al)
+	INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al)
+	INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al)
+	INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al)
+	INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al)
+	INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al)
+	INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al)
+	INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
 MCOUNT_LABEL(eintr)
 
 	.data
diff --git a/sys/i386/i386/exception.s b/sys/i386/i386/exception.s
index a7b457415a494..611a895fd1b3d 100644
--- a/sys/i386/i386/exception.s
+++ b/sys/i386/i386/exception.s
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.16 1996/04/12 12:22:14 phk Exp $
+ *	$Id: exception.s,v 1.17 1996/05/02 09:34:20 phk Exp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -41,6 +41,7 @@
 #include <machine/trap.h>			/* trap codes */
 #include <sys/syscall.h>			/* syscall numbers */
 #include <machine/asmacros.h>			/* miscellaneous macros */
+#include <sys/cdefs.h>				/* CPP macros */
 
 #define	KDSEL		0x10			/* kernel data selector */
 #define	SEL_RPL_MASK	0x0003
@@ -54,7 +55,7 @@
 /*
  * Trap and fault vector routines
  */
-#define	IDTVEC(name)	ALIGN_TEXT ; .globl _X/**/name ; _X/**/name:
+#define	IDTVEC(name)	ALIGN_TEXT; .globl __CONCAT(_X,name); __CONCAT(_X,name):
 #define	TRAP(a)		pushl $(a) ; jmp _alltraps
 
 /*
@@ -69,8 +70,8 @@
 	testb	$SEL_RPL_MASK,4(%esp) ; \
 	jne	1f ; \
 	ss ; \
-	.globl	bdb_/**/name/**/_ljmp ; \
-bdb_/**/name/**/_ljmp: ; \
+	.globl	__CONCAT(__CONCAT(bdb_,name),_ljmp); \
+__CONCAT(__CONCAT(bdb_,name),_ljmp): \
 	ljmp	$0,$0 ; \
 1:
 #else
@@ -123,8 +124,8 @@ IDTVEC(fpu)
 	 * interrupts, but now it is fairly easy - mask nested ones the
 	 * same as SWI_AST's.
 	 */
-	pushl	$0				/* dumby error code */
-	pushl	$0				/* dumby trap type */
+	pushl	$0				/* dummy error code */
+	pushl	$0				/* dummy trap type */
 	pushal
 	pushl	%ds
 	pushl	%es				/* now the stack frame is a trap frame */
diff --git a/sys/i386/i386/microtime.s b/sys/i386/i386/microtime.s
index ab644adf21a59..884a809e794f6 100644
--- a/sys/i386/i386/microtime.s
+++ b/sys/i386/i386/microtime.s
@@ -32,7 +32,7 @@
  * SUCH DAMAGE.
  *
  *	from: Steve McCanne's microtime code
- *	$Id: microtime.s,v 1.11 1995/11/29 19:57:03 wollman Exp $
+ *	$Id: microtime.s,v 1.12 1995/12/24 08:10:43 davidg Exp $
  */
 
 #include <machine/asmacros.h>
@@ -49,129 +49,135 @@ ENTRY(microtime)
 	testl	%ecx, %ecx
 	jne	pentium_microtime
 #else
-	xorl	%ecx, %ecx	# clear ecx
+	xorl	%ecx, %ecx	/* clear ecx */
 #endif
 
-	movb	$TIMER_SEL0|TIMER_LATCH, %al	# prepare to latch
+	movb	$TIMER_SEL0|TIMER_LATCH, %al	/* prepare to latch */
 
-	cli			# disable interrupts
+	cli			/* disable interrupts */
 
-	outb	%al, $TIMER_MODE	# latch timer 0's counter
-	inb	$TIMER_CNTR0, %al	# read counter value, LSB first
+	outb	%al, $TIMER_MODE	/* latch timer 0's counter */
+	inb	$TIMER_CNTR0, %al	/* read counter value, LSB first */
 	movb	%al, %cl
 	inb	$TIMER_CNTR0, %al
 	movb	%al, %ch
 
-	# Now check for counter overflow.  This is tricky because the
-	# timer chip doesn't let us atomically read the current counter
-	# value and the output state (i.e., overflow state).  We have
-	# to read the ICU interrupt request register (IRR) to see if the
-	# overflow has occured.  Because we lack atomicity, we use
-	# the (very accurate) heuristic that we only check for
-	# overflow if the value read is close to the interrupt period.
-	# E.g., if we just checked the IRR, we might read a non-overflowing
-	# value close to 0, experience overflow, then read this overflow
-	# from the IRR, and mistakenly add a correction to the "close
-	# to zero" value.
-	#
-	# We compare the counter value to the prepared overflow threshold.
-	# If the counter value is less than this, we assume the counter
-	# didn't overflow between disabling timer interrupts and latching
-	# the counter value above.  For example, we assume that interrupts
-	# are enabled when we are called (or were disabled just a few
-	# cycles before we are called and that the instructions before the
-	# "cli" are fast) and that the "cli" and "outb" instructions take
-	# less than 10 timer cycles to execute.  The last assumption is
-	# very safe.
-	#
-	# Otherwise, the counter might have overflowed.  We check for this
-	# condition by reading the interrupt request register out of the ICU.
-	# If it overflowed, we add in one clock period.
-	#
-	# The heuristic is "very accurate" because it works 100% if we're
-	# called with interrupts enabled.  Otherwise, it might not work.
-	# Currently, only siointrts() calls us with interrupts disabled, so
-	# the problem can be avoided at some cost to the general case.  The
-	# costs are complications in callers to disable interrupts in
-	# IO_ICU1 and extra reads of the IRR forced by a conservative
-	# overflow threshold.
-	#
-	# In 2.0, we are called at splhigh() from mi_switch(), so we have
-	# to allow for the overflow bit being in ipending instead of in
-	# the IRR.  Our caller may have executed many instructions since
-	# ipending was set, so the heuristic for the IRR is inappropriate
-	# for ipending.  However, we don't need another heuristic, since
-	# the "cli" suffices to lock ipending.
-
-	movl	_timer0_max_count, %edx	# prepare for 2 uses
-
-	testb	$IRQ0, _ipending	# is a soft timer interrupt pending?
+	/*
+	 * Now check for counter overflow.  This is tricky because the
+	 * timer chip doesn't let us atomically read the current counter
+	 * value and the output state (i.e., overflow state).  We have
+	 * to read the ICU interrupt request register (IRR) to see if the
+	 * overflow has occured.  Because we lack atomicity, we use
+	 * the (very accurate) heuristic that we only check for
+	 * overflow if the value read is close to the interrupt period.
+	 * E.g., if we just checked the IRR, we might read a non-overflowing
+	 * value close to 0, experience overflow, then read this overflow
+	 * from the IRR, and mistakenly add a correction to the "close
+	 * to zero" value.
+	 *
+	 * We compare the counter value to the prepared overflow threshold.
+	 * If the counter value is less than this, we assume the counter
+	 * didn't overflow between disabling timer interrupts and latching
+	 * the counter value above.  For example, we assume that interrupts
+	 * are enabled when we are called (or were disabled just a few
+	 * cycles before we are called and that the instructions before the
+	 * "cli" are fast) and that the "cli" and "outb" instructions take
+	 * less than 10 timer cycles to execute.  The last assumption is
+	 * very safe.
+	 *
+	 * Otherwise, the counter might have overflowed.  We check for this
+	 * condition by reading the interrupt request register out of the ICU.
+	 * If it overflowed, we add in one clock period.
+	 *
+	 * The heuristic is "very accurate" because it works 100% if we're
+	 * called with interrupts enabled.  Otherwise, it might not work.
+	 * Currently, only siointrts() calls us with interrupts disabled, so
+	 * the problem can be avoided at some cost to the general case.  The
+	 * costs are complications in callers to disable interrupts in
+	 * IO_ICU1 and extra reads of the IRR forced by a conservative
+	 * overflow threshold.
+	 *
+	 * In 2.0, we are called at splhigh() from mi_switch(), so we have
+	 * to allow for the overflow bit being in ipending instead of in
+	 * the IRR.  Our caller may have executed many instructions since
+	 * ipending was set, so the heuristic for the IRR is inappropriate
+	 * for ipending.  However, we don't need another heuristic, since
+	 * the "cli" suffices to lock ipending.
+	 */
+
+	movl	_timer0_max_count, %edx	/* prepare for 2 uses */
+
+	testb	$IRQ0, _ipending	/* is a soft timer interrupt pending? */
 	jne	overflow
 
-	# Do we have a possible overflow condition?
+	/* Do we have a possible overflow condition? */
 	cmpl	_timer0_overflow_threshold, %ecx
 	jbe	1f
 
-	inb	$IO_ICU1, %al	# read IRR in ICU
-	testb	$IRQ0, %al	# is a hard timer interrupt pending?
+	inb	$IO_ICU1, %al	/* read IRR in ICU */
+	testb	$IRQ0, %al	/* is a hard timer interrupt pending? */
 	je	1f
 overflow:
-	subl	%edx, %ecx	# some intr pending, count timer down through 0
+	subl	%edx, %ecx	/* some intr pending, count timer down through 0 */
 1:
 
-	# Subtract counter value from max count since it is a count-down value.
+	/*
+	 * Subtract counter value from max count since it is a count-down value.
+	 */
 	subl	%ecx, %edx
 
-	# Adjust for partial ticks.
+	/* Adjust for partial ticks. */
 	addl	_timer0_prescaler_count, %edx
 
-	# To divide by 1.193200, we multiply by 27465 and shift right by 15.
-	#
-	# The multiplier was originally calculated to be
-	#
-	#	2^18 * 1000000 / 1193200 = 219698.
-	#
-	# The frequency is 1193200 to be compatible with rounding errors in
-	# the calculation of the usual maximum count.  2^18 is the largest
-	# power of 2 such that multiplying `i' by it doesn't overflow for i
-	# in the range of interest ([0, 11932 + 5)).  We adjusted the
-	# multiplier a little to minimise the average of
-	#
-	#	fabs(i / 1.1193200 - ((multiplier * i) >> 18))
-	#
-	# for i in the range and then removed powers of 2 to speed up the
-	# multiplication and to avoid overflow for i outside the range
-	# (i may be as high as 2^17 if the timer is programmed to its
-	# maximum maximum count).  The absolute error is less than 1 for
-	# all i in the range.
+	/*
+	 * To divide by 1.193200, we multiply by 27465 and shift right by 15.
+	 *
+	 * The multiplier was originally calculated to be
+	 *
+	 *	2^18 * 1000000 / 1193200 = 219698.
+	 *
+	 * The frequency is 1193200 to be compatible with rounding errors in
+	 * the calculation of the usual maximum count.  2^18 is the largest
+	 * power of 2 such that multiplying `i' by it doesn't overflow for i
+	 * in the range of interest ([0, 11932 + 5)).  We adjusted the
+	 * multiplier a little to minimise the average of
+	 *
+	 *	fabs(i / 1.1193200 - ((multiplier * i) >> 18))
+	 *
+	 * for i in the range and then removed powers of 2 to speed up the
+	 * multiplication and to avoid overflow for i outside the range
+	 * (i may be as high as 2^17 if the timer is programmed to its
+	 * maximum maximum count).  The absolute error is less than 1 for
+	 * all i in the range.
+	 */
 
 #if 0
-	imul	$27645, %edx				# 25 cycles on a 486
+	imul	$27645, %edx				/* 25 cycles on a 486 */
 #else
-	leal	(%edx,%edx,2), %eax	# a = 3		2 cycles on a 486
-	leal	(%edx,%eax,4), %eax	# a = 13	2
-	movl	%eax, %ecx		# c = 13	1
-	shl	$5, %eax		# a = 416	2
-	addl	%ecx, %eax		# a = 429	1
-	leal	(%edx,%eax,8), %eax	# a = 3433	2
-	leal	(%edx,%eax,8), %eax	# a = 27465	2 (total 12 cycles)
+	leal	(%edx,%edx,2), %eax	/* a = 3	2 cycles on a 486   */
+	leal	(%edx,%eax,4), %eax	/* a = 13	2		    */
+	movl	%eax, %ecx		/* c = 13	1		    */
+	shl	$5, %eax		/* a = 416	2		    */
+	addl	%ecx, %eax		/* a = 429	1		    */
+	leal	(%edx,%eax,8), %eax	/* a = 3433	2		    */
+	leal	(%edx,%eax,8), %eax	/* a = 27465	2 (total 12 cycles) */
 #endif /* 0 */
 	shr	$15, %eax
 
 common_microtime:
-	addl	_time+4, %eax	# usec += time.tv_sec
-	movl	_time, %edx	# sec = time.tv_sec
+	addl	_time+4, %eax	/* usec += time.tv_sec */
+	movl	_time, %edx	/* sec = time.tv_sec */
 
-	sti			# enable interrupts
+	sti			/* enable interrupts */
 
-	cmpl	$1000000, %eax	# usec valid?
+	cmpl	$1000000, %eax	/* usec valid? */
 	jb	1f
-	subl	$1000000, %eax	# adjust usec
-	incl	%edx		# bump sec
+	subl	$1000000, %eax	/* adjust usec */
+	incl	%edx		/* bump sec */
 1:
-	movl	4(%esp), %ecx	# load timeval pointer arg
-	movl	%edx, (%ecx)	# tvp->tv_sec = sec
-	movl	%eax, 4(%ecx)	# tvp->tv_usec = usec
+	movl	4(%esp), %ecx	/* load timeval pointer arg */
+	movl	%edx, (%ecx)	/* tvp->tv_sec = sec */
+	movl	%eax, 4(%ecx)	/* tvp->tv_usec = usec */
 
 	ret
 
@@ -179,11 +185,11 @@ common_microtime:
 	ALIGN_TEXT
 pentium_microtime:
 	cli
-	.byte	0x0f, 0x31	# RDTSC
+	.byte	0x0f, 0x31	/* RDTSC */
 	subl	_i586_ctr_bias, %eax
 	sbbl	_i586_ctr_bias+4, %edx
-	shldl	$I586_CTR_RATE_SHIFT, %eax, %edx	# magic suggested by
-	shll	$I586_CTR_RATE_SHIFT, %eax		# math_emulate.c
-	divl	%ecx		# get value in usec
+	shldl	$I586_CTR_RATE_SHIFT, %eax, %edx	/* magic suggested by */
+	shll	$I586_CTR_RATE_SHIFT, %eax		/* math_emulate.c */
+	divl	%ecx		/* get value in usec */
 	jmp	common_microtime
 #endif
diff --git a/sys/i386/i386/support.s b/sys/i386/i386/support.s
index 1dbf8ee180cac..0d5bc5dd3f7c8 100644
--- a/sys/i386/i386/support.s
+++ b/sys/i386/i386/support.s
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: support.s,v 1.34 1996/05/02 14:19:53 phk Exp $
+ *	$Id: support.s,v 1.35 1996/05/03 21:01:00 phk Exp $
  */
 
 #include "assym.s"				/* system definitions */
@@ -74,11 +74,11 @@ ENTRY(i486_bzero)
 	movl	4(%esp),%edx
 	movl	8(%esp),%ecx
 	xorl	%eax,%eax
-/
-/ do 64 byte chunks first
-/
-/ XXX this is probably over-unrolled at least for DX2's
-/
+/*
+ * do 64 byte chunks first
+ *
+ * XXX this is probably over-unrolled at least for DX2's
+ */
 2:
 	cmpl	$64,%ecx
 	jb	3f
@@ -103,9 +103,9 @@ ENTRY(i486_bzero)
 	jnz	2b
 	ret
 
-/
-/ do 16 byte chunks
-/
+/*
+ * do 16 byte chunks
+ */
 	SUPERALIGN_TEXT
 3:
 	cmpl	$16,%ecx
@@ -119,9 +119,9 @@ ENTRY(i486_bzero)
 	jnz	3b
 	ret
 
-/
-/ do 4 byte chunks
-/
+/*
+ * do 4 byte chunks
+ */
 	SUPERALIGN_TEXT
 4:
 	cmpl	$4,%ecx
@@ -132,12 +132,12 @@ ENTRY(i486_bzero)
 	jnz	4b
 	ret
 
-/
-/ do 1 byte chunks
-/ a jump table seems to be faster than a loop or more range reductions
-/
-/ XXX need a const section for non-text
-/
+/*
+ * do 1 byte chunks
+ * a jump table seems to be faster than a loop or more range reductions
+ *
+ * XXX need a const section for non-text
+ */
 	SUPERALIGN_TEXT
 jtab:
 	.long	do0
diff --git a/sys/i386/include/asmacros.h b/sys/i386/include/asmacros.h
index 98633543ded3f..4ecabdf5f2d0c 100644
--- a/sys/i386/include/asmacros.h
+++ b/sys/i386/include/asmacros.h
@@ -30,13 +30,14 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: asmacros.h,v 1.6 1995/12/29 15:28:53 bde Exp $
+ *	$Id: asmacros.h,v 1.7 1996/03/31 04:17:25 bde Exp $
  */
 
 #ifndef _MACHINE_ASMACROS_H_
 #define _MACHINE_ASMACROS_H_
 
 #ifdef KERNEL
+#include <sys/cdefs.h>
 
 /* XXX too much duplication in various asm*.h's and gprof.h's */
 
@@ -44,7 +45,7 @@
 #define ALIGN_TEXT	.align	2,0x90	/* 4-byte alignment, nop filled */
 #define SUPERALIGN_TEXT	.align	4,0x90	/* 16-byte alignment (better for 486), nop filled */
 
-#define GEN_ENTRY(name)		ALIGN_TEXT; .globl _/**/name; _/**/name:
+#define GEN_ENTRY(name)		ALIGN_TEXT; .globl __CONCAT(_,name); __CONCAT(_,name):
 #define NON_GPROF_ENTRY(name)	GEN_ENTRY(name)
 
 #ifdef GPROF
diff --git a/sys/i386/isa/icu.s b/sys/i386/isa/icu.s
index f04d72d65f8d3..1107c13b4f88b 100644
--- a/sys/i386/isa/icu.s
+++ b/sys/i386/isa/icu.s
@@ -36,7 +36,7 @@
  *
  *	@(#)icu.s	7.2 (Berkeley) 5/21/91
  *
- *	$Id: icu.s,v 1.23 1995/07/05 14:35:34 bde Exp $
+ *	$Id: icu.s,v 1.24 1996/03/12 05:44:25 nate Exp $
  */
 
 /*
@@ -290,7 +290,7 @@ vec8:
 
 #define BUILD_VEC(irq_num) \
 	ALIGN_TEXT ; \
-vec/**/irq_num: ; \
+__CONCAT(vec,irq_num): ; \
 	int	$ICU_OFFSET + (irq_num) ; \
 	ret
 
diff --git a/sys/i386/isa/vector.s b/sys/i386/isa/vector.s
index a5056afa851e3..94691f5f7f184 100644
--- a/sys/i386/isa/vector.s
+++ b/sys/i386/isa/vector.s
@@ -1,6 +1,6 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: vector.s,v 1.18 1996/03/31 03:31:29 bde Exp $
+ *	$Id: vector.s,v 1.19 1996/04/11 21:18:47 bde Exp $
  */
 
 #include "opt_auto_eoi.h"
@@ -98,10 +98,10 @@
  * loading segregs.
  */
 
-#define	FAST_INTR(irq_num, enable_icus) \
+#define	FAST_INTR(irq_num, vec_name, enable_icus) \
 	.text ; \
 	SUPERALIGN_TEXT ; \
-IDTVEC(fastintr/**/irq_num) ; \
+IDTVEC(vec_name) ; \
 	pushl	%eax ;		/* save only call-used registers */ \
 	pushl	%ecx ; \
 	pushl	%edx ; \
@@ -153,12 +153,12 @@ IDTVEC(fastintr/**/irq_num) ; \
 	MEXITCOUNT ; \
 	jmp	_doreti
 
-#define	INTR(irq_num, icu, enable_icus, reg) \
+#define	INTR(irq_num, vec_name, icu, enable_icus, reg) \
 	.text ; \
 	SUPERALIGN_TEXT ; \
-IDTVEC(intr/**/irq_num) ; \
-	pushl	$0 ;		/* dumby error code */ \
-	pushl	$0 ;		/* dumby trap type */ \
+IDTVEC(vec_name) ; \
+	pushl	$0 ;		/* dummy error code */ \
+	pushl	$0 ;		/* dummy trap type */ \
 	pushal ; \
 	pushl	%ds ;		/* save our data and extra segments ... */ \
 	pushl	%es ; \
@@ -175,7 +175,7 @@ IDTVEC(intr/**/irq_num) ; \
 	testb	$IRQ_BIT(irq_num),%reg ; \
 	jne	2f ; \
 	incb	_intr_nesting_level ; \
-Xresume/**/irq_num: ; \
+__CONCAT(Xresume,irq_num): ; \
 	FAKE_MCOUNT(12*4(%esp)) ;	/* XXX late to avoid double count */ \
 	movl	_intr_countp + (irq_num) * 4,%eax ; \
 	incl	(%eax) ; \
@@ -208,38 +208,38 @@ Xresume/**/irq_num: ; \
 	iret
 
 MCOUNT_LABEL(bintr)
-	FAST_INTR(0, ENABLE_ICU1)
-	FAST_INTR(1, ENABLE_ICU1)
-	FAST_INTR(2, ENABLE_ICU1)
-	FAST_INTR(3, ENABLE_ICU1)
-	FAST_INTR(4, ENABLE_ICU1)
-	FAST_INTR(5, ENABLE_ICU1)
-	FAST_INTR(6, ENABLE_ICU1)
-	FAST_INTR(7, ENABLE_ICU1)
-	FAST_INTR(8, ENABLE_ICU1_AND_2)
-	FAST_INTR(9, ENABLE_ICU1_AND_2)
-	FAST_INTR(10, ENABLE_ICU1_AND_2)
-	FAST_INTR(11, ENABLE_ICU1_AND_2)
-	FAST_INTR(12, ENABLE_ICU1_AND_2)
-	FAST_INTR(13, ENABLE_ICU1_AND_2)
-	FAST_INTR(14, ENABLE_ICU1_AND_2)
-	FAST_INTR(15, ENABLE_ICU1_AND_2)
-	INTR(0, IO_ICU1, ENABLE_ICU1, al)
-	INTR(1, IO_ICU1, ENABLE_ICU1, al)
-	INTR(2, IO_ICU1, ENABLE_ICU1, al)
-	INTR(3, IO_ICU1, ENABLE_ICU1, al)
-	INTR(4, IO_ICU1, ENABLE_ICU1, al)
-	INTR(5, IO_ICU1, ENABLE_ICU1, al)
-	INTR(6, IO_ICU1, ENABLE_ICU1, al)
-	INTR(7, IO_ICU1, ENABLE_ICU1, al)
-	INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
-	INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	FAST_INTR(0,fastintr0, ENABLE_ICU1)
+	FAST_INTR(1,fastintr1, ENABLE_ICU1)
+	FAST_INTR(2,fastintr2, ENABLE_ICU1)
+	FAST_INTR(3,fastintr3, ENABLE_ICU1)
+	FAST_INTR(4,fastintr4, ENABLE_ICU1)
+	FAST_INTR(5,fastintr5, ENABLE_ICU1)
+	FAST_INTR(6,fastintr6, ENABLE_ICU1)
+	FAST_INTR(7,fastintr7, ENABLE_ICU1)
+	FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
+	FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
+	FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
+	FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
+	FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
+	FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
+	FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
+	FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
+	INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al)
+	INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al)
+	INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al)
+	INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al)
+	INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al)
+	INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al)
+	INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al)
+	INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al)
+	INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
+	INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
 MCOUNT_LABEL(eintr)
 
 	.data