10 files changed, 1587 insertions, 217 deletions

diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile
index 33234c49e518a..ffd840271aab1 100644
--- a/lib/libpmc/Makefile
+++ b/lib/libpmc/Makefile
@@ -39,6 +39,7 @@ MAN+=	pmc.corei7.3
 MAN+=	pmc.corei7uc.3
 MAN+=	pmc.sandybridge.3
 MAN+=	pmc.sandybridgeuc.3	
+MAN+=	pmc.sandybridgexeon.3	
 MAN+=	pmc.westmere.3
 MAN+=	pmc.westmereuc.3
 MAN+=	pmc.tsc.3
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c
index eda2c8c7a1695..04debf6f685fd 100644
--- a/lib/libpmc/libpmc.c
+++ b/lib/libpmc/libpmc.c
@@ -192,6 +192,11 @@ static const struct pmc_event_descr sandybridge_event_table[] =
 	__PMC_EV_ALIAS_SANDYBRIDGE()
 };
 
+static const struct pmc_event_descr sandybridge_xeon_event_table[] = 
+{
+	__PMC_EV_ALIAS_SANDYBRIDGE_XEON()
+};
+
 static const struct pmc_event_descr westmere_event_table[] =
 {
 	__PMC_EV_ALIAS_WESTMERE()
@@ -228,6 +233,7 @@ PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
@@ -265,6 +271,7 @@ PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
+PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
@@ -569,6 +576,8 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
 #define ivybridge_aliases_without_iaf	core2_aliases_without_iaf
 #define sandybridge_aliases		core2_aliases
 #define sandybridge_aliases_without_iaf	core2_aliases_without_iaf
+#define sandybridge_xeon_aliases	core2_aliases
+#define sandybridge_xeon_aliases_without_iaf	core2_aliases_without_iaf
 #define westmere_aliases		core2_aliases
 #define westmere_aliases_without_iaf	core2_aliases_without_iaf
 
@@ -688,7 +697,7 @@ static struct pmc_masks iap_rsp_mask_i7_wm[] = {
 	NULLMASK
 };
 
-static struct pmc_masks iap_rsp_mask_sb_ib[] = {
+static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
 	PMCMASK(REQ_DMND_DATA_RD,	(1ULL <<  0)),
 	PMCMASK(REQ_DMND_RFO,		(1ULL <<  1)),
 	PMCMASK(REQ_DMND_IFETCH,	(1ULL <<  2)),
@@ -794,9 +803,10 @@ iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
 			} else
 				return (-1);
 		} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
-		    cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) {
+		    cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
+			cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) {
 			if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
-				n = pmc_parse_mask(iap_rsp_mask_sb_ib, p, &rsp);
+				n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
 			} else
 				return (-1);
 		} else
@@ -2667,6 +2677,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
 			ev = sandybridge_event_table;
 			count = PMC_EVENT_TABLE_SIZE(sandybridge);
 			break;
+		case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
+			ev = sandybridge_xeon_event_table;
+			count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
+			break;
 		case PMC_CPU_INTEL_WESTMERE:
 			ev = westmere_event_table;
 			count = PMC_EVENT_TABLE_SIZE(westmere);
@@ -2959,6 +2973,9 @@ pmc_init(void)
 		pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
 		PMC_MDEP_INIT_INTEL_V2(sandybridge);
 		break;
+	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
+		PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon);
+		break;
 	case PMC_CPU_INTEL_WESTMERE:
 		pmc_class_table[n++] = &ucf_class_table_descr;
 		pmc_class_table[n++] = &westmereuc_class_table_descr;
@@ -3093,6 +3110,10 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
 			ev = sandybridge_event_table;
 			evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
 			break;
+		case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
+			ev = sandybridge_xeon_event_table;
+			evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
+			break;
 		case PMC_CPU_INTEL_WESTMERE:
 			ev = westmere_event_table;
 			evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3
index bd05eb6ed5bd1..675343ec24e1b 100644
--- a/lib/libpmc/pmc.ivybridge.3
+++ b/lib/libpmc/pmc.ivybridge.3
@@ -23,7 +23,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd August 24, 2012
+.Dd October 19, 2012
 .Dt PMC.IVYBRIDGE 3
 .Os
 .Sh NAME
@@ -856,6 +856,7 @@ Dirty L2 cache lines evicted by the MLC prefetcher.
 .Xr pmc.corei7uc 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
+.Xr pmc.sandybridgexeon 3 ,
 .Xr pmc.westmere 3 ,
 .Xr pmc.westmereuc 3 ,
 .Xr pmc.soft 3 ,
diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3
index 8572302efeea2..2f398fad485a9 100644
--- a/lib/libpmc/pmc.sandybridge.3
+++ b/lib/libpmc/pmc.sandybridge.3
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd February 12, 2012
+.Dd October 19, 2012
 .Dt PMC.SANDYBRIDGE 3
 .Os
 .Sh NAME
@@ -932,6 +932,7 @@ Split locks in SQ.
 .Xr pmc.p5 3 ,
 .Xr pmc.p6 3 ,
 .Xr pmc.sandybridgeuc 3 ,
+.Xr pmc.sandybridgexeon 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,
diff --git a/lib/libpmc/pmc.sandybridgeuc.3 b/lib/libpmc/pmc.sandybridgeuc.3
index 970191656d95f..93e6ffe455166 100644
--- a/lib/libpmc/pmc.sandybridgeuc.3
+++ b/lib/libpmc/pmc.sandybridgeuc.3
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd February 12, 2012
+.Dd October 19, 2012
 .Dt PMC.SANDYBRIDGEUC 3
 .Os
 .Sh NAME
@@ -208,6 +208,7 @@ Counts the number of core-outgoing entries in the coherent tracker queue.
 .Xr pmc.p5 3 ,
 .Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
+.Xr pmc.sandybridgexeon 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,
diff --git a/lib/libpmc/pmc.sandybridgexeon.3 b/lib/libpmc/pmc.sandybridgexeon.3
new file mode 100644
index 0000000000000..e55f28324bc77
--- /dev/null
+++ b/lib/libpmc/pmc.sandybridgexeon.3
@@ -0,0 +1,1023 @@
+.\" Copyright (c) 2012 Hiren Panchasara <hiren.panchasara@gmail.com>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd October 18, 2012
+.Dt PMC.SANDYBRIDGEXEON 3
+.Os
+.Sh NAME
+.Nm pmc.sandybridgexeon
+.Nd measurement events for
+.Tn Intel
+.Tn Sandy Bridge Xeon
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel
+.Tn "Sandy Bridge Xeon"
+CPUs contain PMCs conforming to version 2 of the
+.Tn Intel
+performance measurement architecture.
+These CPUs may contain up to two classes of PMCs:
+.Bl -tag -width "Li PMC_CLASS_IAP"
+.It Li PMC_CLASS_IAF
+Fixed-function counters that count only one hardware event per counter.
+.It Li PMC_CLASS_IAP
+Programmable counters that may be configured to count one of a defined
+set of hardware events.
+.El
+.Pp
+The number of PMCs available in each class and their widths need to be
+determined at run time by calling
+.Xr pmc_cpuinfo 3 .
+.Pp
+Intel Sandy Bridge Xeon PMCs are documented in
+.Rs
+.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
+.%T "Volume 3B: System Programming Guide, Part 2"
+.%N "Order Number: 253669-043US"
+.%D August 2012
+.%Q "Intel Corporation"
+.Re
+.Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS
+These PMCs and their supported events are documented in
+.Xr pmc.iaf 3 .
+.Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS
+The programmable PMCs support the following capabilities:
+.Bl -column "PMC_CAP_INTERRUPT" "Support"
+.It Em Capability Ta Em Support
+.It PMC_CAP_CASCADE Ta \&No
+.It PMC_CAP_EDGE Ta Yes
+.It PMC_CAP_INTERRUPT Ta Yes
+.It PMC_CAP_INVERT Ta Yes
+.It PMC_CAP_READ Ta Yes
+.It PMC_CAP_PRECISE Ta \&No
+.It PMC_CAP_SYSTEM Ta Yes
+.It PMC_CAP_TAGGING Ta \&No
+.It PMC_CAP_THRESHOLD Ta Yes
+.It PMC_CAP_USER Ta Yes
+.It PMC_CAP_WRITE Ta Yes
+.El
+.Ss Event Qualifiers
+Event specifiers for these PMCs support the following common
+qualifiers:
+.Bl -tag -width indent
+.It Li rsp= Ns Ar value
+Configure the Off-core Response bits.
+.Bl -tag -width indent
+.It Li REQ_DMND_DATA_RD
+Counts the number of demand and DCU prefetch data reads of full and partial
+cachelines as well as demand data page table entry cacheline reads. Does not
+count L2 data read prefetches or instruction fetches.
+.It Li REQ_DMND_RFO
+Counts the number of demand and DCU prefetch reads for ownership (RFO)
+requests generated by a write to data cacheline. Does not count L2 RFO
+prefetches.
+.It Li REQ_DMND_IFETCH
+Counts the number of demand and DCU prefetch instruction cacheline reads.
+Does not count L2 code read prefetches.
+.It Li REQ_WB
+Counts the number of writeback (modified to exclusive) transactions.
+.It Li REQ_PF_DATA_RD
+Counts the number of data cacheline reads generated by L2 prefetchers.
+.It Li REQ_PF_RFO
+Counts the number of RFO requests generated by L2 prefetchers.
+.It Li REQ_PF_IFETCH
+Counts the number of code reads generated by L2 prefetchers.
+.It Li REQ_PF_LLC_DATA_RD
+L2 prefetcher to L3 for loads.
+.It Li REQ_PF_LLC_RFO
+RFO requests generated by L2 prefetcher
+.It Li REQ_PF_LLC_IFETCH
+L2 prefetcher to L3 for instruction fetches.
+.It Li REQ_BUS_LOCKS
+Bus lock and split lock requests.
+.It Li REQ_STRM_ST
+Streaming store requests.
+.It Li REQ_OTHER
+Any other request that crosses IDI, including I/O.
+.It Li RES_ANY
+Catch all value for any response types.
+.It Li RES_SUPPLIER_NO_SUPP
+No Supplier Information available.
+.It Li RES_SUPPLIER_LLC_HITM
+M-state initial lookup stat in L3.
+.It Li RES_SUPPLIER_LLC_HITE
+E-state.
+.It Li RES_SUPPLIER_LLC_HITS
+S-state.
+.It Li RES_SUPPLIER_LLC_HITF
+F-state.
+.It Li RES_SUPPLIER_LOCAL
+Local DRAM Controller.
+.It Li RES_SNOOP_SNPI_NONE
+No details on snoop-related information.
+.It Li RES_SNOOP_SNP_NO_NEEDED
+No snoop was needed to satisfy the request.
+.It Li RES_SNOOP_SNP_MISS
+A snoop was needed and it missed all snooped caches:
+-For LLC Hit, ReslHitl was returned by all cores
+-For LLC Miss, Rspl was returned by all sockets and data was returned from
+DRAM.
+.It Li RES_SNOOP_HIT_NO_FWD
+A snoop was needed and it hits in at least one snooped cache. Hit denotes a
+cache-line was valid before snoop effect. This includes:
+-Snoop Hit w/ Invalidation (LLC Hit, RFO)
+-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
+-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
+In the LLC Miss case, data is returned from DRAM.
+.It Li RES_SNOOP_HIT_FWD
+A snoop was needed and data was forwarded from a remote socket.
+This includes:
+-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
+.It Li RES_SNOOP_HITM
+A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
+cache-line was in modified state before effect as a results of snoop. This
+includes:
+-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
+-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
+-Snoop MtoS (LLC Hit, IFetch/Data_RD).
+.It Li RES_NON_DRAM
+Target was non-DRAM system address. This includes MMIO transactions.
+.El
+.It Li cmask= Ns Ar value
+Configure the PMC to increment only if the number of configured
+events measured in a cycle is greater than or equal to
+.Ar value .
+.It Li edge
+Configure the PMC to count the number of de-asserted to asserted
+transitions of the conditions expressed by the other qualifiers.
+If specified, the counter will increment only once whenever a
+condition becomes true, irrespective of the number of clocks during
+which the condition remains true.
+.It Li inv
+Invert the sense of comparison when the
+.Dq Li cmask
+qualifier is present, making the counter increment when the number of
+events per cycle is less than the value specified by the
+.Dq Li cmask
+qualifier.
+.It Li os
+Configure the PMC to count events happening at processor privilege
+level 0.
+.It Li usr
+Configure the PMC to count events occurring at privilege levels 1, 2
+or 3.
+.El
+.Pp
+If neither of the
+.Dq Li os
+or
+.Dq Li usr
+qualifiers are specified, the default is to enable both.
+.Ss Event Specifiers (Programmable PMCs)
+Sandy Bridge Xeon programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li LD_BLOCKS.DATA_UNKNOWN
+.Pq Event 03H , Umask 01H
+blocked loads due to store buffer blocks with unknown data.
+.It Li LD_BLOCKS.STORE_FORWARD
+.Pq Event 03H , Umask 02H
+loads blocked by overlapping with store buffer that cannot
+be forwarded .
+.It Li LD_BLOCKS.NO_SR
+.Pq Event 03H , Umask 08H
+# of Split loads blocked due to resource not available.
+.It Li LD_BLOCKS.ALL_BLOCK
+.Pq Event 03H , Umask 10H
+Number of cases where any load is blocked but has no
+DCU miss.
+.It Li MISALIGN_MEM_REF.LOADS
+.Pq Event 05H , Umask 01H
+Speculative cache-line split load uops dispatched to
+L1D.
+.It Li MISALIGN_MEM_REF.STORES
+.Pq Event 05H , Umask 02H
+Speculative cache-line split Store- address uops
+dispatchedto L1D.
+.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
+.Pq Event 07H , Umask 01H
+False dependencies in MOB due to partial compare on
+address.
+.It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK
+.Pq Event 07H , Umask 08H
+The number of times that load operations are temporarily
+blocked because of older stores, with addresses that are
+not yet known.  A load operation may incur more than one
+block of this type.
+.It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 08H , Umask 01H
+Misses in all TLB levels that cause a page walk of any
+page size.
+.It Li TLB_LOAD_MISSES.WALK_COMPLETED
+.Pq Event 08H , Umask 02H
+Misses in all TLB levels that caused page walk completed
+of any size.
+.It Li DTLB_LOAD_MISSES.WALK_DURATION
+.Pq Event 08H , Umask 04H
+Cycle PMH is busy with a walk.
+.It Li DTLB_LOAD_MISSES.STLB_HIT
+.Pq Event 08H , Umask 10H
+Number of cache load STLB hits. No page walk.
+.It Li INT_MISC.RECOVERY_CYCLES
+.Pq Event 0DH , Umask 03H
+Cycles waiting to recover after Machine Clears or EClear.
+Set Cmask= 1.
+.It Li INT_MISC.RAT_STALL_CYCLES
+.Pq Event 0DH , Umask 40H
+Cycles RAT external stall is sent to IDQ for this thread.
+.It Li UOPS_ISSUED.ANY
+.Pq Event 0EH , Umask 01H
+Increments each cycle the # of Uops issued by the
+RAT to RS.
+Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
+of this core.
+.It Li FP_COMP_OPS_EXE.X87
+.Pq Event 10H , Umask 01H
+Counts number of X87 uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE
+.Pq Event 10H , Umask 10H
+Counts number of SSE* double precision FP packed
+uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE
+.Pq Event 10H , Umask 20H
+Counts number of SSE* single precision FP scalar
+uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE
+.Pq Event 10H , Umask 40H
+Counts number of SSE* single precision FP packed
+uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE
+.Pq Event 10H , Umask 80H
+Counts number of SSE* double precision FP scalar
+uops executed.
+.It Li SIMD_FP_256.PACKED_SINGLE
+.Pq Event 11H , Umask 01H
+Counts 256-bit packed single-precision floating-
+point instructions.
+.It Li SIMD_FP_256.PACKED_DOUBLE
+.Pq Event 11H , Umask 02H
+Counts 256-bit packed double-precision floating-
+point instructions.
+.It Li ARITH.FPU_DIV_ACTIVE
+.Pq Event 14H , Umask 01H
+Cycles that the divider is active, includes INT and FP.
+Set 'edge =1, cmask=1' to count the number of
+divides.
+.It Li INSTS_WRITTEN_TO_IQ.INSTS
+.Pq Event 17H , Umask 01H
+Counts the number of instructions written into the
+IQ every cycle.
+.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
+.Pq Event 24H , Umask 01H
+Demand Data Read requests that hit L2 cache.
+.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
+.Pq Event 24H , Umask 03H
+Counts any demand and L1 HW prefetch data load
+requests to L2.
+.It Li L2_RQSTS.RFO_HITS
+.Pq Event 24H , Umask 04H
+Counts the number of store RFO requests that
+hit the L2 cache.
+.It Li L2_RQSTS.RFO_MISS
+.Pq Event 24H , Umask 08H
+Counts the number of store RFO requests that
+miss the L2 cache.
+.It Li L2_RQSTS.ALL_RFO
+.Pq Event 24H , Umask 0CH
+Counts all L2 store RFO requests.
+.It Li L2_RQSTS.CODE_RD_HIT
+.Pq Event 24H , Umask 10H
+Number of instruction fetches that hit the L2
+cache.
+.It Li L2_RQSTS.CODE_RD_MISS
+.Pq Event 24H , Umask 20H
+Number of instruction fetches that missed the L2
+cache.
+.It Li L2_RQSTS.ALL_CODE_RD
+.Pq Event 24H , Umask 30H
+Counts all L2 code requests.
+.It Li L2_RQSTS.PF_HIT
+.Pq Event 24H , Umask 40H
+Requests from L2 Hardware prefetcher that hit L2.
+.It Li L2_RQSTS.PF_MISS
+.Pq Event 24H , Umask 80H
+Requests from L2 Hardware prefetcher that missed
+L2.
+.It Li L2_RQSTS.ALL_PF
+.Pq Event 24H , Umask C0H
+Any requests from L2 Hardware prefetchers.
+.It Li L2_STORE_LOCK_RQSTS.MISS
+.Pq Event 27H , Umask 01H
+ROs that miss cache lines.
+.It Li L2_STORE_LOCK_RQSTS.HIT_E
+.Pq Event 27H , Umask 04H
+RFOs that hit cache lines in E state.
+.It Li L2_STORE_LOCK_RQSTS.HIT_M
+.Pq Event 27H , Umask 08H
+RFOs that hit cache lines in M state.
+.It Li L2_STORE_LOCK_RQSTS.ALL
+.Pq Event 27H , Umask 0FH
+RFOs that access cache lines in any state.
+.It Li L2_L1D_WB_RQSTS.MISS
+.Pq Event 28H , Umask 01H
+Not rejected writebacks from L1D to L2 cache lines
+that missed L2.
+.It Li L2_L1D_WB_RQSTS.HIT_S
+.Pq Event 28H , Umask 02H
+Not rejected writebacks from L1D to L2 cache lines
+in S state.
+.It Li L2_L1D_WB_RQSTS.HIT_E
+.Pq Event 28H , Umask 04H
+Not rejected writebacks from L1D to L2 cache lines
+in E state.
+.It Li L2_L1D_WB_RQSTS.HIT_M
+.Pq Event 28H , Umask 08H
+Not rejected writebacks from L1D to L2 cache lines
+in M state.
+.It Li L2_L1D_WB_RQSTS.ALL
+.Pq Event 28H , Umask 0FH
+Not rejected writebacks from L1D to L2 cache.
+.It Li LONGEST_LAT_CACHE.REFERENCE
+.Pq Event 2EH , Umask 4FH
+This event counts requests originating from the
+core that reference
+a cache line in the last level cache.
+.It Li LONGEST_LAT_CACHE.MISS
+.Pq Event 2EH , Umask 41H
+This event counts each cache miss condition for
+references to the last level cache.
+.It Li CPU_CLK_UNHALTED.THREAD_P
+.Pq Event 3CH , Umask 00H
+Counts the number of thread cycles while the
+thread is not in a halt state. The thread enters
+the halt state when it is running the HLT
+instruction. The core frequency may change from
+time to time due to power or thermal throttling.
+.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
+.Pq Event 3CH , Umask 01H
+Increments at the frequency of XCLK (100 MHz)
+when not halted.
+.It Li L1D_PEND_MISS.PENDING
+.Pq Event 48H , Umask 01H
+Increments the number of outstanding L1D misses
+every cycle.
+Set Cmaks = 1 and Edge =1 to count occurrences.
+.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 49H , Umask 01H
+Miss in all TLB levels causes an page walk of
+any page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED
+.Pq Event 49H , Umask 02H
+Miss in all TLB levels causes a page walk that
+completes of any page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_DURATION
+.Pq Event 49H , Umask 04H
+Cycles PMH is busy with this walk.
+.It Li DTLB_STORE_MISSES.STLB_HIT
+.Pq Event 49H , Umask 10H
+Store operations that miss the first TLB level
+but hit the second and do not cause page walks.
+.It Li LOAD_HIT_PRE.SW_PF
+.Pq Event 4CH , Umask 01H
+Not SW-prefetch load dispatches that hit fill
+buffer allocated for S/W prefetch.
+.It Li LOAD_HIT_PER.HW_PF
+.Pq Event 4CH , Umask 02H
+Not SW-prefetch load dispatches that hit fill
+buffer allocated for H/W prefetch.
+.It Li HW_PRE_REQ.DL1_MISS
+.Pq Event 4EH , Umask 02H
+Hardware Prefetch requests that miss the L1D
+cache. A request is being counted each time
+it access the cache & miss it, including if
+a block is applicable or if hit the Fill
+Buffer for example.
+.It Li L1D.REPLACEMENT
+.Pq Event 51H , Umask 01H
+Counts the number of lines brought into the
+L1 data cache.
+.It Li L1D.ALLOCATED_IN_M
+.Pq Event 51H , Umask 02H
+Counts the number of allocations of modified
+L1D cache lines.
+.It Li L1D.EVICTION
+.Pq Event 51H , Umask 04H
+Counts the number of modified lines evicted
+from the L1 data cache due to replacement.
+.It Li L1D.ALL_M_REPLACEMENT
+.Pq Event 51H , Umask 08H
+Cache lines in M state evicted out of L1D due
+to Snoop HitM or dirty line replacement.
+.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP
+.Pq Event 59H , Umask 0CH
+Increments the number of flags-merge uops in
+flight each cycle.
+Set Cmask = 1 to count cycles.
+.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW
+.Pq Event 59H , Umask 0FH
+Cycles with at least one slow LEA uop allocated.
+.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
+.Pq Event 59H , Umask 40H
+Number of Multiply packed/scalar single precision
+uops allocated.
+.It Li RESOURCE_STALLS2.ALL_FL_EMPTY
+.Pq Event 5BH , Umask 0CH
+Cycles stalled due to free list empty.
+.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL
+.Pq Event 5BH , Umask 0FH
+Cycles stalled due to control structures full for
+physical registers.
+.It Li RESOURCE_STALLS2.BOB_FULL
+.Pq Event 5BH , Umask 40H
+Cycles Allocator is stalled due Branch Order Buffer.
+.It Li RESOURCE_STALLS2.OOO_RSRC
+.Pq Event 5BH , Umask 4FH
+Cycles stalled due to out of order resources full.
+.It Li CPL_CYCLES.RING0
+.Pq Event 5CH , Umask 01H
+Unhalted core cycles when the thread is in ring 0.
+.It Li CPL_CYCLES.RING123
+.Pq Event 5CH , Umask 02H
+Unhalted core cycles when the thread is not in ring
+0.
+.It Li RS_EVENTS.EMPTY_CYCLES
+.Pq Event 5EH , Umask 01H
+Cycles the RS is empty for the thread.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
+.Pq Event 60H , Umask 01H
+Offcore outstanding Demand Data Read
+transactions in SQ to uncore. Set Cmask=1 to count
+cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
+.Pq Event 60H , Umask 04H
+Offcore outstanding RFO store transactions in SQ to
+uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
+.Pq Event 60H , Umask 08H
+Offcore outstanding cacheable data read
+transactions in SQ to uncore. Set Cmask=1 to count
+cycles.
+.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
+.Pq Event 63H , Umask 01H
+Cycles in which the L1D and L2 are locked, due to a
+UC lock or split lock.
+.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
+.Pq Event 63H , Umask 02H
+Cycles in which the L1D is locked.
+.It Li IDQ.EMPTY
+.Pq Event 79H , Umask 02H
+Counts cycles the IDQ is empty.
+.It Li IDQ.MITE_UOPS
+.Pq Event 79H , Umask 04H
+Increment each cycle # of uops delivered to IDQ
+from MITE path.
+Set Cmask = 1 to count cycles.
+.It Li IDQ.DSB_UOPS
+.Pq Event 79H , Umask 08H
+Increment each cycle. # of uops delivered to IDQ
+from DSB path.
+Set Cmask = 1 to count cycles.
+.It Li IDQ.MS_DSB_UOPS
+.Pq Event 79H , Umask 10H
+Increment each cycle # of uops delivered to IDQ
+when MS busy by DSB. Set Cmask = 1 to count
+cycles MS is busy. Set Cmask=1 and Edge =1 to
+count MS activations.
+.It Li IDQ.MS_MITE_UOPS
+.Pq Event 79H , Umask 20H
+Increment each cycle # of uops delivered to IDQ
+when MS is busy by MITE. Set Cmask = 1 to count
+cycles.
+.It Li IDQ.MS_UOPS
+.Pq Event 79H , Umask 30H
+Increment each cycle # of uops delivered to IDQ
+from MS by either DSB or MITE. Set Cmask = 1 to
+count cycles.
+.It Li ICACHE.MISSES
+.Pq Event 80H , Umask 02H
+Number of Instruction Cache, Streaming Buffer and
+Victim Cache Misses. Includes UC accesses.
+.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 85H , Umask 01H
+Misses in all ITLB levels that cause page walks.
+.It Li ITLB_MISSES.WALK_COMPLETED
+.Pq Event 85H , Umask 02H
+Misses in all ITLB levels that cause completed page
+walks.
+.It Li ITLB_MISSES.WALK_DURATION
+.Pq Event 85H , Umask 04H
+Cycle PMH is busy with a walk.
+.It Li ITLB_MISSES.STLB_HIT
+.Pq Event 85H , Umask 10H
+Number of cache load STLB hits. No page walk.
+.It Li ILD_STALL.LCP
+.Pq Event 87H , Umask 01H
+Stalls caused by changing prefix length of the
+instruction.
+.It Li ILD_STALL.IQ_FULL
+.Pq Event 87H , Umask 04H
+Stall cycles due to IQ is full.
+.It Li BR_INST_EXEC.COND
+.Pq Event 88H , Umask 01H
+Qualify conditional near branch instructions
+executed, but not necessarily retired.
+.It Li BR_INST_EXEC.DIRECT_JMP
+.Pq Event 88H , Umask 02H
+Qualify all unconditional near branch instructions
+excluding calls and indirect branches.
+.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 88H , Umask 04H
+Qualify executed indirect near branch instructions
+that are not calls nor returns.
+.It Li BR_INST_EXEC.RETURN_NEAR
+.Pq Event 88H , Umask 08H
+Qualify indirect near branches that have a return
+mnemonic.
+.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
+.Pq Event 88H , Umask 10H
+Qualify unconditional near call branch instructions,
+excluding non call branch, executed.
+.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 88H , Umask 20H
+Qualify indirect near calls, including both register
+and memory indirect, executed.
+.It Li BR_INST_EXEC.NONTAKEN
+.Pq Event 88H , Umask 40H
+Qualify non-taken near branches executed.
+.It Li BR_INST_EXEC.TAKEN
+.Pq Event 88H , Umask 80H
+Qualify taken near branches executed. Must
+combine with 01H,02H, 04H, 08H, 10H, 20H.
+.It Li BR_INST_EXE.ALL_BRANCHES
+.Pq Event 88H , Umask FFH
+Counts all near executed branches (not necessarily
+retired).
+.It Li BR_MISP_EXEC.COND
+.Pq Event 89H , Umask 01H
+Qualify conditional near branch instructions
+mispredicted.
+.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 89H , Umask 04H
+Qualify mispredicted indirect near branch
+instructions that are not calls nor returns.
+.It Li BR_MISP_EXEC.RETURN_NEAR
+.Pq Event 89H , Umask 08H
+Qualify mispredicted indirect near branches that
+have a return mnemonic.
+.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
+.Pq Event 89H , Umask 10H
+Qualify mispredicted unconditional near call branch
+instructions, excluding non call branch, executed.
+.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 89H , Umask 20H
+Qualify mispredicted indirect near calls, including
+both register and memory indirect, executed.
+.It Li BR_MISP_EXEC.NONTAKEN
+.Pq Event 89H , Umask 40H
+Qualify mispredicted non-taken near branches
+executed,.
+.It Li BR_MISP_EXEC.TAKEN
+.Pq Event 89H , Umask 80H
+Qualify mispredicted taken near branches executed.
+Must combine with 01H,02H, 04H, 08H, 10H, 20H
+.It Li BR_MISP_EXEC.ALL_BRANCHES
+.Pq Event 89H , Umask FFH
+Counts all near executed branches (not necessarily
+retired).
+.It Li IDQ_UOPS_NOT_DELIVERED.CORE
+.Pq Event 9CH , Umask 01H
+Count number of non-delivered uops to RAT per
+thread.
+.It Li UOPS_DISPATCHED_PORT.PORT_0
+.Pq Event A1H , Umask 01H
+Cycles which a Uop is dispatched on port 0.
+.It Li UOPS_DISPATCHED_PORT.PORT_1
+.Pq Event A1H , Umask 02H
+Cycles which a Uop is dispatched on port 1.
+.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
+.Pq Event A1H , Umask 04H
+Cycles which a load uop is dispatched on port 2.
+.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
+.Pq Event A1H , Umask 08H
+Cycles which a store address uop is dispatched on
+port 2.
+.It Li UOPS_DISPATCHED_PORT.PORT_2
+.Pq Event A1H , Umask 0CH
+Cycles which a Uop is dispatched on port 2.
+.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
+.Pq Event A1H , Umask 10H
+Cycles which a load uop is dispatched on port 3.
+.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
+.Pq Event A1H , Umask 20H
+Cycles which a store address uop is dispatched on
+port 3.
+.It Li UOPS_DISPATCHED_PORT.PORT_3
+.Pq Event A1H , Umask 30H
+Cycles which a Uop is dispatched on port 3.
+.It Li UOPS_DISPATCHED_PORT.PORT_4
+.Pq Event A1H , Umask 40H
+Cycles which a Uop is dispatched on port 4.
+.It Li UOPS_DISPATCHED_PORT.PORT_5
+.Pq Event A1H , Umask 80H
+Cycles which a Uop is dispatched on port 5.
+.It Li RESOURCE_STALLS.ANY
+.Pq Event A2H , Umask 01H
+Cycles Allocation is stalled due to Resource Related
+reason.
+.It Li RESOURCE_STALLS.LB
+.Pq Event A2H , Umask 01H
+Counts the cycles of stall due to lack of load buffers.
+.It Li RESOURCE_STALLS.RS
+.Pq Event A2H , Umask 04H
+Cycles stalled due to no eligible RS entry available.
+.It Li RESOURCE_STALLS.SB
+.Pq Event A2H , Umask 08H
+Cycles stalled due to no store buffers available. (not
+including draining form sync).
+.It Li RESOURCE_STALLS.ROB
+.Pq Event A2H , Umask 10H
+Cycles stalled due to re-order buffer full.
+.It Li RESOURCE_STALLS.FCSW
+.Pq Event A2H , Umask 20H
+Cycles stalled due to writing the FPU control word.
+.It Li RESOURCE_STALLS.MXCSR
+.Pq Event A2H , Umask 40H
+Cycles stalled due to the MXCSR register rename
+occurring to close to a previous MXCSR rename.
+.It Li RESOURCE_STALLS.OTHER
+.Pq Event A2H , Umask 80H
+Cycles stalled while execution was stalled due to
+other resource issues.
+.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
+.Pq Event A3H , Umask 01H
+Cycles with pending L2 miss loads. Set AnyThread
+to count per core.
+.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
+.Pq Event A3H , Umask 02H
+Cycles with pending L1 cache miss loads.Set
+AnyThread to count per core.
+.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH
+.Pq Event A3H , Umask 04H
+Cycles of dispatch stalls. Set AnyThread to count per
+core.
+.It Li DSB2MITE_SWITCHES.COUNT
+.Pq Event ABH , Umask 01H
+Number of DSB to MITE switches.
+.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
+.Pq Event ABH , Umask 02H
+Cycles DSB to MITE switches caused delay.
+.It Li DSB_FILL.OTHER_CANCEL
+.Pq Event ACH , Umask 02H
+Cases of cancelling valid DSB fill not because of
+exceeding way limit.
+.It Li DSB_FILL.EXCEED_DSB_LINES
+.Pq Event ACH , Umask 08H
+DSB Fill encountered > 3 DSB lines.
+.It Li DSB_FILL.ALL_CANCEL
+.Pq Event ACH , Umask 0AH
+Cases of cancelling valid Decode Stream Buffer
+(DSB) fill not because of exceeding way limit.
+.It Li ITLB.ITLB_FLUSH
+.Pq Event AEH , Umask 01H
+Counts the number of ITLB flushes, includes
+4k/2M/4M pages.
+.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
+.Pq Event B0H , Umask 01H
+Demand data read requests sent to uncore.
+.It Li OFFCORE_REQUESTS.DEMAND_RFO
+.Pq Event B0H , Umask 04H
+Demand RFO read requests sent to uncore, including
+regular RFOs, locks, ItoM.
+.It Li OFFCORE_REQUESTS.ALL_DATA_RD
+.Pq Event B0H , Umask 08H
+Data read requests sent to uncore (demand and
+prefetch).
+.It Li UOPS_DISPATCHED.THREAD
+.Pq Event B1H , Umask 01H
+Counts total number of uops to be dispatched per-
+thread each cycle. Set Cmask = 1, INV =1 to count
+stall cycles.
+.It Li UOPS_DISPATCHED.CORE
+.Pq Event B1H , Umask 02H
+Counts total number of uops to be dispatched per-
+core each cycle.
+.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL
+.Pq Event B2H , Umask 01H
+Offcore requests buffer cannot take more entries
+for this thread core.
+.It Li AGU_BYPASS_CANCEL.COUNT
+.Pq Event B6H , Umask 01H
+Counts executed load operations with all the
+following traits: 1. addressing of the format [base +
+offset], 2. the offset is between 1 and 2047, 3. the
+address specified in the base register is in one page
+and the address [base+offset] is in another page.
+.It Li OFF_CORE_RESPONSE_0
+.Pq Event B7H , Umask 01H
+(Event B7H, Umask 01H) Off-core Response Performance
+Monitoring; PMC0 only.  Requires programming MSR 01A6H
+.It Li OFF_CORE_RESPONSE_1
+.Pq Event BBH , Umask 01H
+(Event BBH, Umask 01H) Off-core Response Performance
+Monitoring; PMC3 only.  Requires programming MSR 01A7H
+.It Li TLB_FLUSH.DTLB_THREAD
+.Pq Event BDH , Umask 01H
+DTLB flush attempts of the thread-specific entries.
+.It Li TLB_FLUSH.STLB_ANY
+.Pq Event BDH , Umask 20H
+Count number of STLB flush attempts.
+.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES
+.Pq Event BFH , Umask 05H
+Cycles when dispatched loads are cancelled due to
+L1D bank conflicts with other load ports.
+.It Li INST_RETIRED.ANY_P
+.Pq Event C0H , Umask 00H
+Number of instructions at retirement.
+.It Li INST_RETIRED.ALL
+.Pq Event C0H , Umask 01H
+Precise instruction retired event with HW to reduce
+effect of PEBS shadow in IP distribution.
+.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED
+.Pq Event C1H , Umask 02H
+Instructions that experienced an ITLB miss.
+.It Li OTHER_ASSISTS.AVX_STORE
+.Pq Event C1H , Umask 08H
+Number of assists associated with 256-bit AVX
+store operations.
+.It Li OTHER_ASSISTS.AVX_TO_SSE
+.Pq Event C1H , Umask 10H
+Number of transitions from AVX-256 to legacy SSE
+when penalty applicable.
+.It Li OTHER_ASSISTS.SSE_TO_AVX
+.Pq Event C1H , Umask 20H
+Number of transitions from SSE to AVX-256 when
+penalty applicable.
+.It Li UOPS_RETIRED.ALL
+.Pq Event C2H , Umask 01H
+Counts the number of micro-ops retired, Use
+cmask=1 and invert to count active cycles or stalled
+cycles.
+.It Li UOPS_RETIRED.RETIRE_SLOTS
+.Pq Event C2H , Umask 02H
+Counts the number of retirement slots used each
+cycle.
+.It Li MACHINE_CLEARS.MEMORY_ORDERING
+.Pq Event C3H , Umask 02H
+Counts the number of machine clears due to
+memory order conflicts.
+.It Li MACHINE_CLEARS.SMC
+.Pq Event C3H , Umask 04H
+Counts the number of times that a program writes
+to a code section.
+.It Li MACHINE_CLEARS.MASKMOV
+.Pq Event C3H , Umask 20H
+Counts the number of executed AVX masked load
+operations that refer to an illegal address range
+with the mask bits set to 0.
+.It Li BR_INST_RETIRED.ALL_BRANCH
+.Pq Event C4H , Umask 00H
+Branch instructions at retirement.
+.It Li BR_INST_RETIRED.CONDITIONAL
+.Pq Event C4H , Umask 01H
+Counts the number of conditional branch
+instructions retired.
+.It Li BR_INST_RETIRED.NEAR_CALL
+.Pq Event C4H , Umask 02H
+Direct and indirect near call instructions retired.
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H , Umask 04H
+Counts the number of branch instructions retired.
+.It Li BR_INST_RETIRED.NEAR_RETURN
+.Pq Event C4H , Umask 08H
+Counts the number of near return instructions
+retired.
+.It Li BR_INST_RETIRED.NOT_TAKEN
+.Pq Event C4H , Umask 10H
+Counts the number of not taken branch instructions
+retired.
+.It Li BR_INST_RETIRED.NEAR_TAKEN
+.Pq Event C4H , Umask 20H
+Number of near taken branches retired.
+.It Li BR_INST_RETIRED.FAR_BRANCH
+.Pq Event C4H , Umask 40H
+Number of far branches retired.
+.It Li BR_MISP_RETIRED.ALL_BRANCHES
+.Pq Event C5H , Umask 00H
+Mispredicted branch instructions at retirement.
+.It Li BR_MISP_RETIRED.CONDITIONAL
+.Pq Event C5H , Umask 01H
+Mispredicted conditional branch instructions retired.
+.It Li BR_MISP_RETIRED.NEAR_CALL
+.Pq Event C5H , Umask 02H
+Direct and indirect mispredicted near call
+instructions retired.
+.It Li BR_MISP_RETIRED.ALL_BRANCHES
+.Pq Event C5H , Umask 04H
+Mispredicted macro branch instructions retired.
+.It Li BR_MISP_RETIRED.NOT_TAKEN
+.Pq Event C5H , Umask 10H
+Mispredicted not taken branch instructions retired.
+.It Li BR_MISP_RETIRED.TAKEN
+.Pq Event C5H , Umask 20H
+Mispredicted taken branch instructions retired.
+.It Li FP_ASSIST.X87_OUTPUT
+.Pq Event CAH , Umask 02H
+Number of X87 assists due to output value.
+.It Li FP_ASSIST.X87_INPUT
+.Pq Event CAH , Umask 04H
+Number of X87 assists due to input value.
+.It Li FP_ASSIST.SIMD_OUTPUT
+.Pq Event CAH , Umask 08H
+ Number of SIMD FP assists due to output values.
+.It Li FP_ASSIST.SIMD_INPUT
+.Pq Event CAH , Umask 10H
+Number of SIMD FP assists due to input values.
+.It Li FP_ASSIST.ANY 1EH
+.Pq Event CAH , Umask
+Cycles with any input/output SSE* or FP assists.
+.It Li ROB_MISC_EVENTS.LBR_INSERTS
+.Pq Event CCH , Umask 20H
+Count cases of saving new LBR records by
+hardware.
+.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
+.Pq Event CDH , Umask 01H
+Sample loads with specified latency threshold.
+PMC3 only.
+.It Li MEM_TRANS_RETIRED.PRECISE_STORE
+.Pq Event CDH , Umask 02H
+Sample stores and collect precise store operation
+via PEBS record. PMC3 only.
+.It Li MEM_UOP_RETIRED.LOADS
+.Pq Event D0H , Umask 10H
+Qualify retired memory uops that are loads.
+Combine with umask 10H, 20H, 40H, 80H.
+.It Li MEM_UOP_RETIRED.STORES
+.Pq Event D0H , Umask 02H
+Qualify retired memory uops that are stores.
+Combine with umask 10H, 20H, 40H, 80H.
+.It Li MEM_UOP_RETIRED.STLB_MISS
+.Pq Event D0H , Umask
+Qualify retired memory uops with STLB miss. Must
+combine with umask 01H, 02H, to produce counts.
+.It Li MEM_UOP_RETIRED.LOCK
+.Pq Event D0H , Umask
+Qualify retired memory uops with lock. Must
+combine with umask 01H, 02H, to produce counts.
+.It Li MEM_UOP_RETIRED.SPLIT
+.Pq Event D0H , Umask
+Qualify retired memory uops with line split. Must
+combine with umask 01H, 02H, to produce counts.
+.It Li MEM_UOP_RETIRED_ALL
+.Pq Event D0H , Umask
+Qualify any retired memory uops. Must combine
+with umask 01H, 02H, to produce counts.
+.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
+.Pq Event D1H , Umask 01H
+Retired load uops with L1 cache hits as data
+sources.
+.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
+.Pq Event D1H , Umask 02H
+Retired load uops with L2 cache hits as data
+sources.
+.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
+.Pq Event D1H , Umask 04H
+Retired load uops which data sources were data hits
+in LLC without snoops required.
+.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS
+.Pq Event D1H , Umask 20H
+Retired load uops which data sources were data
+missed LLC (excluding unknown data source).
+.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
+.Pq Event D1H , Umask 40H
+Retired load uops which data sources were load
+uops missed L1 but hit FB due to preceding miss to
+the same cache line with data not ready.
+.It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS
+.Pq Event D4H , Umask 02H
+Retired load uops with unknown information as data
+source in cache serviced the load.
+.It Li BACLEARS.ANY
+.Pq Event E6H , Umask 01H
+Counts the number of times the front end is re-
+steered, mainly when the BPU cannot provide a
+correct prediction and this is corrected by other
+branch handling mechanisms at the front end.
+.It Li L2_TRANS.DEMAND_DATA_RD
+.Pq Event F0H , Umask 01H
+Demand Data Read requests that access L2 cache.
+.It Li L2_TRANS.RFO
+.Pq Event F0H , Umask 02H
+RFO requests that access L2 cache.
+.It Li L2_TRANS.CODE_RD
+.Pq Event F0H , Umask 04H
+L2 cache accesses when fetching instructions.
+.It Li L2_TRANS.ALL_PF
+.Pq Event F0H , Umask 08H
+L2 or LLC HW prefetches that access L2 cache.
+.It Li L2_TRANS.L1D_WB
+.Pq Event F0H , Umask 10H
+L1D writebacks that access L2 cache.
+.It Li L2_TRANS.L2_FILL
+.Pq Event F0H , Umask 20H
+L2 fill requests that access L2 cache.
+.It Li L2_TRANS.L2_WB
+.Pq Event F0H , Umask 40H
+L2 writebacks that access L2 cache.
+.It Li L2_TRANS.ALL_REQUESTS
+.Pq Event F0H , Umask 80H
+Transactions accessing L2 pipe.
+.It Li L2_LINES_IN.I
+.Pq Event F1H , Umask 01H
+L2 cache lines in I state filling L2.
+.It Li L2_LINES_IN.S
+.Pq Event F1H , Umask 02H
+L2 cache lines in S state filling L2.
+.It Li L2_LINES_IN.E
+.Pq Event F1H , Umask 04H
+L2 cache lines in E state filling L2.
+.It Li L2_LINES-IN.ALL
+.Pq Event F1H , Umask 07H
+L2 cache lines filling L2.
+.It Li L2_LINES_OUT.DEMAND_CLEAN
+.Pq Event F2H , Umask 01H
+Clean L2 cache lines evicted by demand.
+.It Li L2_LINES_OUT.DEMAND_DIRTY
+.Pq Event F2H , Umask 02H
+Dirty L2 cache lines evicted by demand.
+.It Li L2_LINES_OUT.PF_CLEAN
+.Pq Event F2H , Umask 04H
+Clean L2 cache lines evicted by L2 prefetch.
+.It Li L2_LINES_OUT.PF_DIRTY
+.Pq Event F2H , Umask 08H
+Dirty L2 cache lines evicted by L2 prefetch.
+.It Li L2_LINES_OUT.DIRTY_ALL
+.Pq Event F2H , Umask 0AH
+Dirty L2 cache lines filling the L2.
+.It Li SQ_MISC.SPLIT_LOCK
+.Pq Event F4H , Umask 10H
+Split locks in SQ.
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.ucf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.corei7 3 ,
+.Xr pmc.corei7uc 3 ,
+.Xr pmc.ivybridge 3 ,
+.Xr pmc.sandybridge 3 ,
+.Xr pmc.sandybridgeuc 3 ,
+.Xr pmc.westmere 3 ,
+.Xr pmc.westmereuc 3 ,
+.Xr pmc.soft 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy@FreeBSD.org .
+The support for the Sandy Bridge Xeon
+microarchitecture was written by
+.An "Hiren Panchasara"
+.Aq hiren.panchasara@gmail.com .
diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c
index fe0c97a8aeda8..1fdfa98266518 100644
--- a/sys/dev/hwpmc/hwpmc_core.c
+++ b/sys/dev/hwpmc/hwpmc_core.c
@@ -558,7 +558,8 @@ struct iap_event_descr {
 #define	IAP_F_WM	(1 << 5)	/* CPU: Westmere */
 #define	IAP_F_SB	(1 << 6)	/* CPU: Sandy Bridge */
 #define	IAP_F_IB	(1 << 7)	/* CPU: Ivy Bridge */
-#define	IAP_F_FM	(1 << 8)	/* Fixed mask */
+#define	IAP_F_SBX	(1 << 8)	/* CPU: Sandy Bridge Xeon */
+#define	IAP_F_FM	(1 << 9)	/* Fixed mask */
 
 #define	IAP_F_ALLCPUSCORE2					\
     (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
@@ -598,12 +599,15 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
+    IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
+	IAP_F_SBX),
     IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 
-	IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
-    IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
-    IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
+    IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
+	IAP_F_SBX),
+    IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
+	IAP_F_SBX),
     IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
@@ -613,8 +617,10 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
@@ -627,24 +633,26 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
     IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
-    IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB),
+    IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB |
+	IAP_F_SBX),
 
     IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX),
     IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX),
     IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_WM | IAP_F_SB),
+	IAP_F_WM | IAP_F_SB | IAP_F_SBX),
     IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
     IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
     IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
     IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
-    IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
+	IAP_F_SBX),
     IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
@@ -666,10 +674,11 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
     IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
 
-    IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
 
-    IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB),
     IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB),
@@ -684,19 +693,24 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 
-	IAP_F_WM | IAP_F_SB),
+	IAP_F_WM | IAP_F_SB | IAP_F_SBX),
     IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
-    IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
-    IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
-    IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
+	IAP_F_SBX),
+    IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
+	IAP_F_SBX),
+    IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
+	IAP_F_SBX),
+    IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
+	IAP_F_SBX),
     IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
-    IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB),
-    IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB |
+	IAP_F_SBX),
+    IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
     IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
@@ -718,10 +732,11 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
     IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 
-	 IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
-    IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
+	IAP_F_SBX),
 
     IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -743,18 +758,29 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
-    IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
@@ -774,12 +800,16 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
-    IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
-    IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
+	IAP_F_SBX),
+    IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -788,11 +818,13 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
-    IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB),
-    IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB),
+    IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX),
+    IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX),
 
     IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
     IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
@@ -805,9 +837,9 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
     IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
     IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
     IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
 	IAP_F_ALLCPUSCORE2),
@@ -820,9 +852,9 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
@@ -863,17 +895,19 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-        IAP_F_SB | IAP_F_IB),
+        IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7),
     IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7),
@@ -886,14 +920,15 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
@@ -904,13 +939,13 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
 
     IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
 
     IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
@@ -921,30 +956,33 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB),
     IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB),
 
-    IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
 
-    IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
 
-    IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     
-    IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB),
 
     IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
     IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB),
     IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
     IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
     IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
@@ -956,9 +994,9 @@ static struct iap_event_descr iap_events[] = {
 	IAP_F_CA | IAP_F_CC2),
     IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
     IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
     IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
     IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
@@ -999,12 +1037,18 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
     IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
 
-    IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB),
     IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB),
     IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB),
@@ -1023,7 +1067,7 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
-	IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
 	IAP_F_WM),
     IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1044,12 +1088,13 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
@@ -1058,53 +1103,57 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
@@ -1119,46 +1168,55 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
-    IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), 
+    IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX), 
 
     IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     
     IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
+
+    IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX),
+    IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX),
+    IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX),
 
     IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1170,25 +1228,26 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
 
     IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
-    IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
 
     IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IB),
 
     IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB),
     IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
     IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1196,9 +1255,9 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1210,7 +1269,7 @@ static struct iap_event_descr iap_events[] = {
 	IAP_F_WM),
 
     IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
 
     IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
 	IAP_F_WM | IAP_F_I7O),
@@ -1232,10 +1291,10 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
     IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
 
-    IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
 
     IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
     IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1245,17 +1304,19 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
-    IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
-    IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
 
     IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
@@ -1264,17 +1325,20 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB),
-    IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
+    IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
@@ -1286,36 +1350,44 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
-    IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
-    IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
+	IAP_F_IB | IAP_F_SBX),
     IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB |
+	IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
@@ -1342,13 +1414,15 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
@@ -1369,31 +1443,42 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), 
+    IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX), 
 
     IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
-    IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
+    IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
  
-    IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
+	IAP_F_IB | IAP_F_SBX),
     IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX),
+    IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
 
     IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
@@ -1407,12 +1492,13 @@ static struct iap_event_descr iap_events[] = {
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
 
-    IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB),
+    IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX),
 
     IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
     IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
@@ -1464,7 +1550,7 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
     IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
-	IAP_F_WM),
+	IAP_F_WM | IAP_F_SBX),
     IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1475,39 +1561,40 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
-    IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
+    IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
+	IAP_F_SBX),
     IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
 
     IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
     IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB | IAP_F_IB),
-    IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB),
+	IAP_F_SB | IAP_F_IB | IAP_F_SBX),
+    IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
     IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
@@ -1522,7 +1609,7 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
     IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
-	IAP_F_SB),
+	IAP_F_SB | IAP_F_SBX),
 
     IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
@@ -1694,7 +1781,7 @@ iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
 }
 
 static int
-iap_event_sb_ib_ok_on_counter(enum pmc_event pe, int ri)
+iap_event_sb_sbx_ib_ok_on_counter(enum pmc_event pe, int ri)
 {
 	uint32_t mask;
 
@@ -1709,6 +1796,7 @@ iap_event_sb_ib_ok_on_counter(enum pmc_event pe, int ri)
 		break;
 		/* Events valid only on counter 2. */
 	case PMC_EV_IAP_EVENT_48H_01H:
+	case PMC_EV_IAP_EVENT_A2H_02H:
 		mask = 0x4;
 		break;
 		/* Events valid only on counter 3. */
@@ -1801,8 +1889,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 			return (EINVAL);
 		break;
 	case PMC_CPU_INTEL_SANDYBRIDGE:
+	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 	case PMC_CPU_INTEL_IVYBRIDGE:
-		if (iap_event_sb_ib_ok_on_counter(ev, ri) == 0)
+		if (iap_event_sb_sbx_ib_ok_on_counter(ev, ri) == 0)
 			return (EINVAL);
 		break;
 	case PMC_CPU_INTEL_WESTMERE:
@@ -1842,6 +1931,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	case PMC_CPU_INTEL_SANDYBRIDGE:	
 		cpuflag = IAP_F_SB;
 		break;
+	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:	
+		cpuflag = IAP_F_SBX;
+		break;
 	case PMC_CPU_INTEL_WESTMERE:
 		cpuflag = IAP_F_WM;
 		break;
@@ -1929,7 +2021,8 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
 	 */
 	if (core_cputype == PMC_CPU_INTEL_ATOM ||
-		core_cputype == PMC_CPU_INTEL_SANDYBRIDGE)
+		core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
+		core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON)
 		evsel |= (config & IAP_ANY);
 	else if (config & IAP_ANY)
 		return (EINVAL);
@@ -1949,7 +2042,8 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 		    a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
 			return (EINVAL);
 		else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
-		    core_cputype == PMC_CPU_INTEL_IVYBRIDGE) &&
+		    core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
+			core_cputype == PMC_CPU_INTEL_IVYBRIDGE) &&
 		    a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
 			return (EINVAL);
 		pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index 8b82298230c60..db7e63401004a 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -146,6 +146,10 @@ pmc_intel_initialize(void)
 			cputype = PMC_CPU_INTEL_SANDYBRIDGE;
 			nclasses = 5;
 			break;
+		case 0x2D:	/* Per Intel document 253669-044US 08/2012. */
+			cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
+			nclasses = 3;
+			break;
 		case 0x3A:	/* Per Intel document 253669-043US 05/2012. */
 			cputype = PMC_CPU_INTEL_IVYBRIDGE;
 			nclasses = 3;
@@ -191,6 +195,7 @@ pmc_intel_initialize(void)
 	case PMC_CPU_INTEL_IVYBRIDGE:
 	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
+	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 		error = pmc_core_initialize(pmc_mdep, ncpus);
 		break;
 
@@ -271,6 +276,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
 	case PMC_CPU_INTEL_IVYBRIDGE:
 	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
+	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 		pmc_core_finalize(md);
 		break;
 
diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h
index 899b264daebe2..d37c900daa3f5 100644
--- a/sys/dev/hwpmc/pmc_events.h
+++ b/sys/dev/hwpmc/pmc_events.h
@@ -858,6 +858,9 @@ __PMC_EV(IAP, EVENT_A2H_10H)			\
 __PMC_EV(IAP, EVENT_A2H_20H)			\
 __PMC_EV(IAP, EVENT_A2H_40H)			\
 __PMC_EV(IAP, EVENT_A2H_80H)			\
+__PMC_EV(IAP, EVENT_A3H_01H)                  	\
+__PMC_EV(IAP, EVENT_A3H_02H)                  	\
+__PMC_EV(IAP, EVENT_A3H_04H)                  	\
 __PMC_EV(IAP, EVENT_A6H_01H)			\
 __PMC_EV(IAP, EVENT_A7H_01H)			\
 __PMC_EV(IAP, EVENT_A8H_01H)			\
@@ -1008,6 +1011,7 @@ __PMC_EV(IAP, EVENT_D1H_01H)			\
 __PMC_EV(IAP, EVENT_D1H_02H)			\
 __PMC_EV(IAP, EVENT_D1H_04H)			\
 __PMC_EV(IAP, EVENT_D1H_08H)			\
+__PMC_EV(IAP, EVENT_D1H_20H)			\
 __PMC_EV(IAP, EVENT_D1H_40H)			\
 __PMC_EV(IAP, EVENT_D2H_01H)			\
 __PMC_EV(IAP, EVENT_D2H_02H)			\
@@ -1016,6 +1020,7 @@ __PMC_EV(IAP, EVENT_D2H_08H)			\
 __PMC_EV(IAP, EVENT_D2H_0FH)			\
 __PMC_EV(IAP, EVENT_D2H_10H)			\
 __PMC_EV(IAP, EVENT_D3H_01H)			\
+__PMC_EV(IAP, EVENT_D3H_04H)			\
 __PMC_EV(IAP, EVENT_D4H_01H)			\
 __PMC_EV(IAP, EVENT_D4H_02H)			\
 __PMC_EV(IAP, EVENT_D4H_04H)			\
@@ -2790,7 +2795,223 @@ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H)			\
 __PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH)			\
 __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)				
 
+/*
+ * Aliases for Sandy Bridge Xeon PMC events (253669-044US August 2012)
+ */
 
+#define __PMC_EV_ALIAS_SANDYBRIDGE_XEON()                                     	\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()                                          	\
+__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H)                   	\
+__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H)                  	\
+__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H)                          	\
+__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H)                      	\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H)                   	\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H)                  	\
+__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H)          	\
+__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H)          	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)      	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H)          	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H)           	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H)                	\
+__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H)                 	\
+__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H)                	\
+__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H)                          	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H)                      	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", IAP_EVENT_10H_10H)     	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", IAP_EVENT_10H_20H)     	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H)        	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H)        	\
+__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H)			\
+__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H)			\
+__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H)                     	\
+__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H)                  \
+__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H)              	\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H)              	\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H)				\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H)				\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH)                         	\
+__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H)                     	\
+__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H)                    	\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H)                     	\
+__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H)                          	\
+__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H)                         	\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H)                          	\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H)                 	\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H)			\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H)			\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH)                  	\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H)                     	\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_S", IAP_EVENT_28H_02H)                    	\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H)                    	\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H)                    	\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH)                      	\
+__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH)              	\
+__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H)                   	\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H)			\
+__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H)         	\
+__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H)                    	\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H)     	\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H)         	\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H)          	\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H)			\
+__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H)				\
+__PMC_EV_ALIAS("LOAD_HIT_PER.HW_PF", IAP_EVENT_4CH_02H)				\
+__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H)			\
+__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H)                          	\
+__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H)                         \
+__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H)                             	\
+__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H)                    	\
+__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H)         \
+__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H)         \
+__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H)          \
+__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH)            	\
+__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH)         	\
+__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H)                  \
+__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH)                  \
+__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H)                         	\
+__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H)                         \
+__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H)                   	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H)\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H)  	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H) 	\
+__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H)  	\
+__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H)          	\
+__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H)                                  \
+__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H)                            	\
+__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H)                             	\
+__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H)                          	\
+__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H)                         	\
+__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H)                              	\
+__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H)                            	\
+__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H)           	\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H)                 \
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H)                  \
+__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H)                     	\
+__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H)                            	\
+__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H)                          \
+__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H)                          \
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H)                  	\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H)   	\
+__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H)                 	\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H)            	\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H)          	\
+__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H)                    	\
+__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H)                         \
+__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH)                 	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H)                          \
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H)   	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H)                 	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H)            	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H)          	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H)                    	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H)                         \
+__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH)                  \
+__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H)              	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H)              	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H)              	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H)           	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H)          	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH)              	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H)           	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H)          	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H)              	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H)              	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H)              	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H)                      	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_02H)                      	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H)                         \
+__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H)                         \
+__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H)                      	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H)                     	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H)                    	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H)                    	\
+__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H)         	\
+__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_02H)          \
+__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", IAP_EVENT_A3H_04H)          \
+__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H)                  	\
+__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H)         	\
+__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H)                    	\
+__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H)                  \
+__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH)                      	\
+__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H)                          	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H)          	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H)              	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H)             	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H)                   	\
+__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H)                     	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H)          	\
+__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H)                  	\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H)                      	\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H)                      	\
+__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H)                    	\
+__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H)                         \
+__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H)          	\
+__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H)                         \
+__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H)                   	\
+__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H)          	\
+__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H)                  	\
+__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H)                 	\
+__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H)                 	\
+__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H)                         	\
+__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H)                  \
+__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H)           	\
+__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H)                         \
+__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H)                   	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H)                 \
+__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H)              	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H)                  \
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H)             	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H)              	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H)                  \
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H)                 \
+__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H)                 \
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H)             	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H)              	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H)                  \
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H)             	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H)                  \
+__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H)                    	\
+__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H)                     	\
+__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H)                      	\
+__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H)                    	\
+__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H)                     	\
+__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH)                            	\
+__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H)              	\
+__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H)           	\
+__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H)          	\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H)                    	\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H)                   	\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H)                  \
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H)                     	\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H)                    	\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED_ALL", IAP_EVENT_D0H_80H)                      	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H)             	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H)             	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H)            	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H)            	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H)            	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", IAP_EVENT_D3H_01H)	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", IAP_EVENT_D3H_04H)	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", IAP_EVENT_D4H_02H)   	\
+__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H)                             	\
+__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H)                  	\
+__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H)                             	\
+__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H)                         	\
+__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H)                          	\
+__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H)                          	\
+__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H)                         	\
+__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H)                           	\
+__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H)                    	\
+__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H)                            	\
+__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H)                            	\
+__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H)                            	\
+__PMC_EV_ALIAS("L2_LINES-IN.ALL", IAP_EVENT_F1H_07H)                          	\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H)                  \
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H)                  \
+__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H)                    	\
+__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H)                    	\
+__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH)                   	\
+__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)
 
 /* timestamp counters. */
 #define	__PMC_EV_TSC()							\
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
index 50a0735a7d906..571ebf2d03601 100644
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -88,6 +88,7 @@
 	__PMC_CPU(INTEL_WESTMERE, 0x8C,   "Intel Westmere")	\
 	__PMC_CPU(INTEL_SANDYBRIDGE, 0x8D,   "Intel Sandy Bridge")	\
 	__PMC_CPU(INTEL_IVYBRIDGE, 0x8E,   "Intel Ivy Bridge")	\
+	__PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F,   "Intel Sandy Bridge Xeon")	\
 	__PMC_CPU(INTEL_XSCALE,	0x100,	"Intel XScale")		\
 	__PMC_CPU(MIPS_24K,     0x200,  "MIPS 24K")		\
 	__PMC_CPU(PPC_7450,     0x300,  "PowerPC MPC7450")	\