diff options
| author | Emmanuel Vadot <manu@FreeBSD.org> | 2019-09-28 22:35:29 +0000 |
|---|---|---|
| committer | Emmanuel Vadot <manu@FreeBSD.org> | 2019-09-28 22:35:29 +0000 |
| commit | ddee9fd0fa975df750c12dd63cdf18715e51a634 (patch) | |
| tree | 3884661a8bed8a0e3100b1d6b5402b3860389b6f /Bindings/memory-controllers | |
| parent | 0db636cb5e9747c177d4fe9ae36c20987819a1b6 (diff) | |
Notes
Diffstat (limited to 'Bindings/memory-controllers')
| -rw-r--r-- | Bindings/memory-controllers/atmel,ebi.txt | 1 | ||||
| -rw-r--r-- | Bindings/memory-controllers/fsl/mmdc.txt | 35 |
2 files changed, 36 insertions, 0 deletions
diff --git a/Bindings/memory-controllers/atmel,ebi.txt b/Bindings/memory-controllers/atmel,ebi.txt index 9bb5f57e20662..94bf7896a688a 100644 --- a/Bindings/memory-controllers/atmel,ebi.txt +++ b/Bindings/memory-controllers/atmel,ebi.txt @@ -15,6 +15,7 @@ Required properties: "atmel,at91sam9g45-ebi" "atmel,at91sam9x5-ebi" "atmel,sama5d3-ebi" + "microchip,sam9x60-ebi" - reg: Contains offset/length value for EBI memory mapping. This property might contain several entries if the EBI diff --git a/Bindings/memory-controllers/fsl/mmdc.txt b/Bindings/memory-controllers/fsl/mmdc.txt new file mode 100644 index 0000000000000..bcc36c5b543c9 --- /dev/null +++ b/Bindings/memory-controllers/fsl/mmdc.txt @@ -0,0 +1,35 @@ +Freescale Multi Mode DDR controller (MMDC) + +Required properties : +- compatible : should be one of following: + for i.MX6Q/i.MX6DL: + - "fsl,imx6q-mmdc"; + for i.MX6QP: + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SL: + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SLL: + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SX: + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; + for i.MX6UL/i.MX6ULL/i.MX6ULZ: + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + for i.MX7ULP: + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; +- reg : address and size of MMDC DDR controller registers + +Optional properties : +- clocks : the clock provided by the SoC to access the MMDC registers + +Example : + mmdc0: memory-controller@21b0000 { /* MMDC0 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; + }; + + mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b4000 0x4000>; + status = "disabled"; + }; |