diff options
| author | cvs2svn <cvs2svn@FreeBSD.org> | 2000-05-13 19:21:46 +0000 |
|---|---|---|
| committer | cvs2svn <cvs2svn@FreeBSD.org> | 2000-05-13 19:21:46 +0000 |
| commit | b859770a9042cd3b80e48455257b170a33acc0e6 (patch) | |
| tree | 03821f271b530ebf1c52e16febd23d51c82abd08 /contrib/binutils/opcodes | |
| parent | 30565a54fcfe17393cf34d115abbdfb53c056c22 (diff) | |
Diffstat (limited to 'contrib/binutils/opcodes')
40 files changed, 0 insertions, 39410 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog deleted file mode 100644 index 4e2cd471a5e37..0000000000000 --- a/contrib/binutils/opcodes/ChangeLog +++ /dev/null @@ -1,5714 +0,0 @@ -2000-04-13 Michael Sokolov <msokolov@ivan.Harhan.ORG> - - * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, - avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, - disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, - i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, - m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, - mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, ppc-dis.c, - ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, tic80-dis.c, - tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, z8k-dis.c, - z8kgen.c: Everyone includes sysdep.h. Remove ansidecl.h as sysdep.h - includes it. - -2000-04-20 Alexandre Oliva <aoliva@cygnus.com> - - * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. - (disassemble): Use them. - -2000-04-04 Alan Modra <alan@linuxcare.com.au> - - * po/opcodes.pot: Regenerate. - - * Makefile.am (MKDEP): Use gcc -MM rather than mkdep. - (DEP): Quote when passing vars to sub-make. Add warning message - to end. - (DEP1): Rewrite for "gcc -MM". - (CLEANFILES): Add DEP2. - Update dependencies. - * Makefile.in: Regenerate. - -2000-04-03 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: Syntax cleanup. - (add0fff): Print the pc relative address as a signed number. - (add03f8): Likewise. - -2000-04-01 Ian Lance Taylor <ian@zembu.com> - - * disassemble.c (disassembler_usage): Don't use a prototype. Mark - the parameter ATTRIBUTE_UNUSED. - * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed. - -2000-04-01 Alexandre Oliva <aoliva@cygnus.com> - - * m10300-opc.c: SP-based offsets are always unsigned. - -2000-03-29 Thomas de Lellis <tdel@windriver.com> - - * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal" - [branch always] instead of "undefined". - -2000-03-27 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of - short instructions, from end of list of long instructions. - -2000-03-27 Ian Lance Taylor <ian@zembu.com> - - * Makefile.am (CFILES): Add avr-dis.c. - (ALL_MACHINES): Add avr-dis.lo. - -2000-03-27 Alan Modra <alan@linuxcare.com> - - * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to - truncate integers. - (print_insn_avr): Call function via pointer in K&R compatible way. - (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204, - add0fff, add03f8): Convert to old style function declaration and - add prototype. - (avrdis_opcode): Add prototype. - -2000-03-27 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: New file. AVR disassembler. - * configure.in (bfd_avr_arch): New architecture support. - * disassemble.c: Likewise. - * configure: Regenerate. - -Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk> - - * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement. - -2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand - flag to determine if operand is pc-relative. - * d30v-opc.c: - (d30v_format_table): - (REL6S3): Renamed from IMM6S3. - Added flag OPERAND_PCREL. - (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with - added flag OPERAND_PCREL. - (IMM12S3U): Replaced with REL12S3. - (SHORT_D2, LONG_D): Delay target is pc-relative. - (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r): - Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r, - using the REL* operands. - (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D. - (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B, - LONG_Db, using REL* operands. - (SHORT_U, SHORT_A5S): Removed stray alternatives. - (d30v_opcode_table): Use new *r formats. - -2000-02-28 Nick Clifton <nickc@cygnus.com> - - * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with - 'signed_overflow_ok_p'. - -2000-02-27 Eli Zaretskii <eliz@is.elta.co.il> - - * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the - name of the libtool directory. - * Makefile.in: Rebuild. - -2000-02-24 Nick Clifton <nickc@cygnus.com> - - * cgen-opc.c (cgen_set_signed_overflow_ok): New function. - (cgen_clear_signed_overflow_ok): New function. - (cgen_signed_overflow_ok_p): New function. - -2000-02-23 Andrew Haley <aph@cygnus.com> - - * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, - m32r-ibld.c,m32r-opc.h: Rebuild. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370-dis.c, i370-opc.c: New. - - * disassemble.c (ARCH_i370): Define. - (disassembler): Handle it. - - * Makefile.am: Add support for Linux/IBM 370. - * configure.in: Likewise. - - * Makefile.in: Regenerate. - * configure: Likewise. - -2000-02-22 Chandra Chavva <cchavva@cygnus.com> - - * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to - ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel - procedure. - -1999-12-30 Andrew Haley <aph@cygnus.com> - - * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: - force gp32 to zero. - * mips-opc.c (G6): New define. - (mips_builtin_op): Add "move" definition for -gp32. - -2000-02-22 Ian Lance Taylor <ian@zembu.com> - - From Grant Erickson <gerickso@Brocade.COM>: - * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2. - -2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * dis-buf.c (buffer_read_memory): Change `length' param and all int - vars to unsigned. - -Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk> - - * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. - (print_insn_ppi): Likewise. - (print_insn_shx): Use info->mach to select appropriate insn set. - Add support for sh-dsp. Remove FD_REG_N support. - * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. - (sh_arg_type): Likewise. Remove FD_REG_N. - (sh_dsp_reg_nums): New enum. - (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. - (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. - (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. - (arch_sh3_dsp_up): Likewise. - (sh_opcode_info): New field: arch. - (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and - D_REG_N. Fill in arch field. Add sh-dsp insns. - -2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com> - - * arm-dis.c: Change flavor name from atpcs-special to - special-atpcs to prevent name conflict in gdb. - (get_arm_regname_num_options, set_arm_regname_option, - get_arm_regnames): New functions. API to access the several - flavor of register names. Note: Used by gdb. - (print_insn_thumb): Use the register name entry from the currently - selected flavor for LR and PC. - -2000-02-10 Nick Clifton <nickc@cygnus.com> - - * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR - classes. - (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and - "mulsh.h" instructions. - * mcore-dis.c (imsk array): Add masks for MULSH and OPSR - classes. - (print_insn_mcore): Add support for little endian targets. - Add support for MULSH and OPSR classes. - -2000-02-07 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (parse_arm_diassembler_option): Rename again. - Previous delat did not take. - -2000-02-03 Timothy Wall <twall@redhat.com> - - * dis-buf.c (buffer_read_memory): Use octets_per_byte field - to adjust target address bounds checking and calculate the - appropriate octet offset into data. - -2000-01-27 Nick Clifton <nickc@redhat.com> - - * arm-dis.c: (parse_disassembler_option): Rename to - parse_arm_disassembler_option and allow to be exported. - - * disassemble.c (disassembler_usage): New function: Print out any - target specific disassembler options. - Call arm_disassembler_options() if the ARM architecture is being - supported. - - * arm-dis.c (NUM_ELEM): Define this macro if not already - defined. - (arm_regname): New struct type for ARM register names. - (arm_toggle_regnames): Delete. - (parse_disassembler_option): Use register name structure. - (print_insn): New function: Combines duplicate code found in - print_insn_big_arm and print_insn_little_arm. - (print_insn_big_arm): Call print_insn. - (print_insn_little_arm): Call print_insn. - (print_arm_disassembler_options): Display list of supported, - ARM specific disassembler options. - -2000-01-27 Thomas de Lellis <tdel@windriver.com> - - * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the - ARM_STT_16BIT flag as Thumb code symbols. - - * arm-dis.c (printf_insn_little_arm): Ditto. - -2000-01-25 Thomas de Lellis <tdel@windriver.com> - - * arm-dis.c (printf_insn_thumb): Prevent double dumping - of raw thumb instructions. - -2000-01-20 Nick Clifton <nickc@cygnus.com> - - * mcore-opc.h (mcore_table): Add "add" as an alias for "addu". - -2000-01-03 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (streq): New macro. - (strneq): New macro. - (force_thumb): ew local variable. - (parse_disassembler_option): New function: Parse a single, ARM - specific disassembler command line switch. - (parse_disassembler_option): Call parse_disassembler_option to - parse individual command line switches. - (print_insn_big_arm): Check force_thumb. - (print_insn_little_arm): Check force_thumb. - -1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall". - -Wed Dec 1 03:34:53 1999 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c, m10300-dis.c: Add am33 support. - -Wed Nov 24 20:29:58 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names. - (print_insn_hppa): Handle 'B' operand. - -1999-11-22 Nick Clifton <nickc@cygnus.com> - - * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction. - -1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (I5): New. - (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s - madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, - pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New. - -Mon Nov 15 19:34:58 1999 Donald Lindsay <dlindsay@cygnus.com> - - * arm-dis.c (print_insn_arm): Added general purpose 'X' format. - * arm-opc.h (print_insn_arm): Added comment documenting - the 'X' format just added to arm-dis.c. - -1999-11-15 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (la): Create a version that just uses addiu directly. - (dla): Expand to daddiu if possible. - -1999-11-11 Nick Clifton <nickc@cygnus.com> - - * mips-opc.c: Add ssnop pattern. - -1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER. - -1999-10-29 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA - (d30v_format_tab): Define the SHORT_AR format. - -1999-10-28 Nick Clifton <nickc@cygnus.com> - - * mcore-dis.c: Remove spurious code introduced in previous delta. - -1999-10-27 Scott Bambrough <scottb@netwinder.org> - - * arm-dis.c: Include sysdep.h to prevent compile time warnings. - -1999-10-18 Michael Meissner <meissner@cygnus.com> - - * alpha-opc.c (alpha_operands): Fill in missing initializer. - (alpha_num_operands): Convert to unsigned. - (alpha_num_opcodes): Ditto. - (insert_rba): Declare unused arguments ATTRIBUTE_UNUSED. - (insert_rca): Ditto. - (insert_za): Ditto. - (insert_zb): Ditto. - (insert_zc): Ditto. - (extract_bdisp): Ditto. - (extract_jhint): Ditto. - (extract_ev6hwjhint): Ditto. - -Sun Oct 10 01:48:01 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> - - * hppa-dis.c (print_insn_hppa): Add new codes 'cc', 'cd', 'cC', - 'co', '@'. - - * hppa-dis.c (print_insn_hppa): Removed unused args. Fix '?W'. - - * hppa-dis.c (print_insn_hppa): Implement codes "?N", "?Q". - -Thu Oct 7 00:12:43 MDT 1999 Diego Novillo <dnovillo@cygnus.com> - - * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for - rac/rachi instructions. - (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi, - slae, st and st2w. - -1999-10-04 Doug Evans <devans@casey.cygnus.com> - - * fr30-asm.c,fr30-desc.h: Rebuild. - * m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild. Add m32rx support. - * m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto. - -1999-09-29 Nick Clifton <nickc@cygnus.com> - - * sh-opc.h: Fix bit patterns for several load and store - instructions. - -Thu Sep 23 08:27:20 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org - - * hppa-dis.c (print_insn_hppa): Replace 'B', 'M', 'g' and 'l' with - cleaner code using completer prefixes. Add 'Y'. - -Sun Sep 19 10:41:27 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c: (print_insn_hppa): Correct 'cJ', 'cc'. - - * hppa-dis.c (extract_22): New function. - - * hppa-dis.c (print_insn_hppa): Handle 'J', 'K', and 'cc'. - - * hppa-dis.c (print_insn_hppa): Handle 'fe' and 'cJ'. - - * hppa-dis.c (print_insn_hppa): Handle '#', 'd', and 'cq'. - - * hppa-dis.c (print_insn_hppa): Handle 'm', 'h', '='. - - * hppa-dis.c (print_insn_hppa): Handle 'X' operand. - - * hppa-dis.c (print_insn_hppa): Handle 'B' operand. - - * hppa-dis.c (print_insn_hppa): Handle 'M' and 'L' operands. - - * hppa-dis.c (print_insn_hppa): Handle 'l' operand. - - * hppa-dis.c (print_insn_hppa): Handle 'g' operand. - -Sat Sep 18 11:36:12 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (print_insn_hppa): Output a space after 'X' completer. - - * hppa-dis.c: (print_insn_hppa): Do output a space before a 'v' - operand. - - * hppa-dis.c: (print_insn_hppa): Handle 'fX'. - - * hppa-dis.c: (print_insn_hppa): Add missing break after - FP register case. - - * hppa-dis.c: Finish constifying various completers, register - names, etc etc. - -1999-09-14 Michael Meissner <meissner@cygnus.com> - - * configure.in (Canonicalization of target names): Remove adding - ${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14 - generates $ac_config_sub with a ${CONFIG_SHELL} already. - * configure: Regenerate. - -Tue Sep 7 13:50:32 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (print_insn_hppa): Escape '%' in output strings. - - * hppa-dis.c (print_insn_hppa): Handle 'Z' argument. - -1999-09-07 Nick Clifton <nickc@cygnus.com> - - * sh-opc.h: Add mulu.w and muls.w patterns. These are the correct - names for the mulu and muls patterns. - -1999-09-04 Steve Chamberlain <sac@pobox.com> - - * pj-opc.c: New file. - * pj-dis.c: New file. - * disassemble.c (disassembler): Handle bfd_arch_pj. - * configure.in: Handle bfd_pj_arch. - * Makefile.am: Rebuild dependencies. - (CFILES): Add pj-dis.c and pj-opc.c. - (ALL_MACHINES): Add pj-dis.lo and pj-opc.lo. - * configure, Makefile.in: Rebuild. - -1999-09-04 H.J. Lu <hjl@gnu.org> - - * i386-dis.c (print_insn_i386): Set bytes_per_line to 7. - -Mon Aug 30 18:56:14 1999 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31. - -1999-08-04 Doug Evans <devans@casey.cygnus.com> - - * fr30-asm.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. - * m32r-asm.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. - * m32r-opinst.c: Rebuild. - -Sat Aug 28 00:27:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float - register args by 'f'. - - * hppa-dis.c (print_insn_hppa): Add args q, %, !, and |. - - * hppa-dis.c (MASK_10, read_write_names, add_compl_names, - extract_10U_store): New. - (print_insn_hppa): Add new completers. - - * hppa-dis.c (signed_unsigned_names,mix_half_names, - saturation_names): New. - (print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'. - - * hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. - - * hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!' - - * hppa-dis.c (print_insn_hppa): Look at next arg instead of bits - to decide to print a space. - -1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Add AMD athlon instruction support. - -1999-08-10 Ian Lance Taylor <ian@zembu.com> - - From Wally Iimura <iimura@microunity.com>: - * dis-buf.c (buffer_read_memory): Rewrite expression to avoid - overflow at end of address space. - (generic_print_address): Use sprintf_vma. - -1999-08-08 Ian Lance Taylor <ian@zembu.com> - - * Makefile.am: Rename .dep* files to DEP*. Change DEP variable to - MKDEP. Rebuild dependencies. - * Makefile.in: Rebuild. - -Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names, - add_cond_64_names, wide_add_cond_names, logical_cond_64_names, - unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New. - (print_insn_hppa): Add 64 bit condition completers. - -Thu Aug 5 16:59:58 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (print_insn_hppa): Change condition args to use - '?' prefix. - -Wed Jul 28 04:33:58 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E' - code. - -1999-07-21 Ian Lance Taylor <ian@zembu.com> - - From Mark Elbrecht: - * configure.bat: Remove; obsolete. - -1999-07-11 Ian Lance Taylor <ian@zembu.com> - - * dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate. - (generic_strcat_address): Add cast to avoid warning. - * i386-dis.c: Initialize all structure fields to avoid warnings. - Add ATTRIBUTE_UNUSED as appropriate. - -1999-07-08 Jakub Jelinek <jj@ultra.linux.cz> - - * sparc-dis.c (print_insn_sparc): Differentiate between - addition and oring when guessing symbol for comment. - -1999-07-05 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Display hex equivalent of rotated - constant. - -1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Mention intel mode specials in macro char comment. - -1999-06-21 Ian Lance Taylor <ian@zembu.com> - - * alpha-dis.c: Don't include <stdlib.h>. - * arm-dis.c: Include "sysdep.h". - * tic30-dis.c: Don't include <stdlib.h> or <string.h>. Include - "sysdep.h". - * Makefile.am: Rebuild dependencies. - * Makefile.in: Rebuild. - -1999-06-16 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange - SWIs. - -1999-06-14 Nick Clifton <nickc@cygnus.com> & Drew Mosley <dmoseley@cygnus.com> - - * arm-dis.c (arm_regnames): Turn into a pointer to a register - name set. - (arm_regnames_standard): New variable: Array of ARM register - names according to ARM instruction set nomenclature. - (arm_regnames_apcs): New variable: Array of ARM register names - according to ARM Procedure Call Standard. - (arm_regnames_raw): New variable: Array of ARM register names - using just 'r' and the register number. - (arm_toggle_regnames): New function: Toggle the chosen register set - naming scheme. - (parse_disassembler_options): New function: Parse any target - disassembler command line options. - (print_insn_big_arm): Call parse_disassembler_options if any - are defined. - (print_insn_little_arm): Call parse_disassembler_options if any - are defined. - -1999-06-13 Ian Lance Taylor <ian@zembu.com> - - * i386-dis.c (FWAIT_OPCODE): Define. - (used_prefixes): New static variable. - (fetch_data): Don't print an error message if we have already - fetched some bytes successfully. - (ckprefix): Clear used_prefixes. Use FWAIT_OPCODE, not 0x9b. - (prefix_name): New static function. - (print_insn_i386): If setjmp fails, indicating a data error, but - we have managed to fetch some bytes, print the first one as a - prefix or a .byte pseudo-op. If fwait is followed by a non - floating point instruction, print the first prefix. Set - used_prefixes when prefixes are used. If any prefixes were not - used after disassembling the instruction, print the first prefix - instead of printing the instruction. - (putop): Set used_prefixes when prefixes are used. - (append_seg, OP_E, OP_G, OP_REG, OP_I, OP_sI, OP_J): Likewise. - (OP_DIR, OP_SIMD_Suffix): Likewise. - -1999-06-07 Jakub Jelinek <jj@ultra.linux.cz> - - * sparc-opc.c: Fix up set, setsw, setuw operand kinds. - Support signx %reg, clruw %reg. - -1999-06-07 Jakub Jelinek <jj@ultra.linux.cz> - - * sparc-opc.c: Add aliases Solaris as supports. - -Mon Jun 7 12:04:52 1999 Andreas Schwab <schwab@issan.cs.uni-dortmund.de> - - * Makefile.am (CFILES): Add arc-{dis,opc}.c and v850-{dis,opc}.c. - * Makefile.in: Regenerated. - -1999-06-03 Philip Blundell <philb@gnu.org> - - * arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR - when target is PC-relative. - -1999-05-28 Linus Nordberg <linus.nordberg@canit.se> - - * m68k-opc.c: Rename MACL/MSACL to MAC/MSAC. Add MACM/MSACM. Add - MOVE MACSR,CCR. - - * m68k-dis.c (fetch_arg): Add places `n', `o'. - - * m68k-opc.c: Add MSAC, MACL, MOVE to/from ACC, MACSR, MASK. - Add mcf5206e to appropriate instructions. - Add alias for MAC, MSAC. - - * m68k-dis.c (print_insn_arg): Add formats `E', `G', `H' and place - `N'. - - * m68k-opc.c (m68k_opcodes): Add divsw, divsl, divuw, divul, macl, - macw, remsl, remul for mcf5307. Change mcf5200 --> mcf. - - * m68k-dis.c: Add format `u' and places `h', `m', `M'. - -1999-05-18 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (Ed): Define. - (dis386_twobyte_att, dis386_twobyte_intel): Use Ed for movd. - (Rw): Remove. - (OP_rm): Rename to OP_Rd. - (ONE): Remove. - (OP_ONE): Remove. - (putop): Add const to template and p. - (print_insn_x86): Delete. - (print_insn_i386): Merge old function print_insn_x86. Add const - to dp. - (struct dis386): Add const to name. - (dis386_att, dis386_intel): Add const. - (dis386_twobyte_att, dis386_twobyte_intel): Add const. - (names32, names16, names8, names_seg, index16): Add const. - (grps, prefix_user_table, float_reg): Add const. - (float_mem_att, float_mem_intel): Add const. - (oappend): Add const to s. - (OP_REG): Add const to s. - (ptr_reg): Add const to s. - (dofloat): Add const to dp. - (OP_C): Don't skip modrm, it's now done in OP_Rd. - (OP_D): Ditto. - (OP_T): Ditto. - (OP_Rd): Check for valid mod. Call Op_E to print. - (OP_E): Handle d_mode arg. Check for bad sfence,lea,lds etc. - (OP_MS): Check for valid mod. Call Op_EM to print. - (OP_3DNowSuffix): Set obufp and use oappend rather than - strcat. Call BadOp() for errors. - (OP_SIMD_Suffix): Likewise. - (BadOp): New function. - -1999-05-12 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (dis386_intel): Remove macro chars, except for - jEcxz. Change cWtR and cRtd to cW and cR. - (dis386_twobyte_intel): Remove macro chars here too. - (putop): Handle R and W macros for intel mode. - - * i386-dis.c (SIMD_Fixup): New function. - (dis386_twobyte_att): Use it on movlps and movhps, and change - Ev to EX on these insns. Change movmskps Ev, XM to Gv, EX. - (dis386_twobyte_intel): Same here. - - * i386-dis.c (Av): Remove. - (Ap): remove lptr. - (lptr): Remove. - (OPSIMD): Define. - (OP_SIMD_Suffix): New function. - (OP_DIR): Remove dead code. - (eAX_reg..eDI_reg): Renumber. - (onebyte_has_modrm): Table numbering comments. - (INTERNAL_DISASSEMBLER_ERROR): Move to before print_insn_x86. - (print_insn_x86): Move all prefix oappends to after uses_f3_prefix - checks. Print error on invalid dp->bytemode2. Remove simd_cmp, - and handle SIMD cmp insns in OP_SIMD_Suffix. - (info->bytes_per_line): Bump from 5 to 6. - (OP_None): Remove. - (OP_E): Use INTERNAL_DISASSEMBLER_ERROR. Handle sfence. - (OP_3DNowSuffix): Ensure mnemonic index unsigned. - - PIII SIMD support from Doug Ledford <dledford@redhat.com> - * i386-dis.c (XM, EX, None): Define. - (OP_XMM, OP_EX, OP_None): New functions. - (USE_GROUPS, USE_PREFIX_USER_TABLE): Define. - (GRP14): Rename to GRPAMD. - (GRP*): Add USE_GROUPS flag. - (PREGRP*): Define. - (dis386_twobyte_att, dis386_twobyte_intel): Add SIMD insns. - (twobyte_has_modrm): Add SIMD entries. - (twobyte_uses_f3_prefix, simd_cmp_op, prefix_user_table): New. - (grps): Add SIMD insns. - (print_insn_x86): New vars uses_f3_prefix and simd_cmp. Don't - oappend repz if uses_f3_prefix. Add code to handle new groups for - SIMD insns. - - From Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * i386-dis.c (dis386_att, dis386_intel): Change 0xE8 call insn - operand from Av to Jv. - -1999-05-07 Nick Clifton <nickc@cygnus.com> - - * mcore-dis.c (print_insn_mcore): Use .short to display - unidentified instructions, not .word. - -1999-04-26 Tom Tromey <tromey@cygnus.com> - - * aclocal.m4, configure: Updated for new version of libtool. - -1999-04-14 Doug Evans <devans@casey.cygnus.com> - - * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. - -Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (print_insn_hppa, case '3'): New case for PA2.0 - instructions. - -1999-04-10 Doug Evans <devans@casey.cygnus.com> - - * fr30-desc.c,fr30-desc.h,fr30-ibld.c: Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-opinst.c: Rebuild. - -1999-04-06 Ian Lance Taylor <ian@zembu.com> - - * opintl.h (LC_MESSAGES): Never define. - -1999-04-04 Ian Lance Taylor <ian@zembu.com> - - * i386-dis.c (intel_syntax, open_char, close_char): Make static. - (separator_char, scale_char): Likewise. - (print_insn_x86): Likewise. - (print_insn_i386): Likewise. Add declaration. - -1999-03-26 Doug Evans <devans@casey.cygnus.com> - - * fr30-dis.c: Rebuild. - * m32r-dis.c: Rebuild. - -1999-03-23 Ian Lance Taylor <ian@zembu.com> - - * m68k-opc.c: Change compare instructions to use "@s" rather than - ";s" when used with an immediate operand. - -1999-03-22 Doug Evans <devans@casey.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Delete. - (cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize. - * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c,fr30-opc.h: - Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h: - Rebuild. - * po/opcodes.pot: Rebuild. - -1999-03-16 Martin Hunt <hunt@cygnus.com> - - * d30v-opc.c (mvtsys): Remove FLAG_LKR. - -1999-03-11 Doug Evans <devans@casey.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): New arg `isa'. All callers updated. - (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns. - (cgen_get_insn_operands): Rewrite test for hardcoded/operand index. - * fr30-asm.c,fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c: Rebuild. - * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c: Rebuild. - * m32r-opinst.c: Rebuild. - -1999-02-25 Doug Evans <devans@casey.cygnus.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): Rewrite. - (cgen_hw_lookup_by_num): Rewrite. - * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. - * m32r-opinst.c: Rebuild. - -Sat Feb 13 14:06:19 1999 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c: Add sqrt+flags patterns. Add EV6 PALcode insns. - (insert_jhint): Fix insertion mask. - * alpha-dis.c (print_insn_alpha): Disassemble EV6 PALcode insns. - -1999-02-10 Doug Evans <devans@casey.cygnus.com> - - * Makefile.in: Rebuild. - -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * i960c-asm.c,i960c-dis.c,i960c-opc.c,i960c-opc.h: Delete. - * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. - * Makefile.am: Remove references to them. - (HFILES): Add fr30-desc.h,m32r-desc.h. - (CFILES): Add fr30-desc.c,fr30-ibld.c,m32r-desc.c,m32r-ibld.c, - m32r-opinst.c. - (ALL_MACHINES): Update. - * configure.in: Redo handling of cgen_files. - (bfd_i960_arch): Delete i960c-*.lo files. - * configure: Regenerate. - * cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (hash_insn_array): Rewrite. - * cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (hash_insn_array): Rewrite. - * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (cgen_lookup_insn,cgen_get_insn_operands): Define here. - (cgen_lookup_get_insn_operands): Ditto. - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. - * po/POTFILES.in: Rebuild. - * po/opcodes.pot: Rebuild. - -Fri Feb 5 00:04:24 1999 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am: Rebuild dependencies. - (HFILES): Add fr30-opc.h. - (CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c. - * Makefile.in: Rebuild. - - * configure.in: Change AC_PREREQ to 2.13. Remove AM_CYGWIN32. - Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to - AC_PROG_INSTALL. - * acconfig.h: Remove. - * configure: Rebuild with current autoconf/automake. - * aclocal.m4: Likewise. - * config.in: Likewise. - * Makefile.in: Likewise. - -Thu Feb 4 13:48:52 1999 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Correct move (not movew) to status word on 5200. - -Mon Feb 1 20:54:36 1999 Catherine Moore <clm@cygnus.com> - - * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax. - * i386-dis.c (x_mode): Define. - (dis386): Remove. - (dis386_att): New. - (dis386_intel): New. - (dis386_twobyte): Remove. - (dis386_twobyte_att): New. - (dis386_twobyte_intel): New. - (print_insn_x86): Use new arrays. - (float_mem): Remove. - (float_mem_intel): New. - (float_mem_att): New. - (dofloat): Use new float_mem arrays. - (print_insn_i386_att): New. - (print_insn_i386_intel): New. - (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax. - (putop): Handle intel syntax. - (OP_indirE): Handle intel syntax. - (OP_E): Handle intel syntax. - (OP_I): Handle intel syntax. - (OP_sI): Handle intel syntax. - (OP_OFF): Handle intel syntax. - - - -1999-01-27 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.h,fr30-opc.c: Rebuild. - * i960c-opc.h,i960c-opc.c: Rebuild. - * m32r-opc.c: Rebuild. - -Tue Jan 19 18:01:54 1999 David Taylor <taylor@texas.cygnus.com> - - * hppa-dis.c: revert HP merge changes until HP gives us - an updated file. - -1999-01-19 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Display ARM syntax for PC relative - offsets as well as symbloic address. - -Tue Jan 19 10:51:01 1999 David Taylor <taylor@texas.cygnus.com> - - * hppa-dis.c: fix comments and some indentation. - -1999-01-12 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.c,i960c-opc.c: Regenerate. - -1999-01-11 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.c: Regenerate. - -1999-01-06 Doug Evans <devans@casey.cygnus.com> - - * m32r-dis.c: Regenerate. - -1999-01-05 Doug Evans <devans@casey.cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate. - * i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate. - * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. - -1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) - - * configure.in: Require autoconf 2.12.1 or higher. - -1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> - - * mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH. - -Wed Dec 16 16:17:49 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - -1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111. - -1998-12-15 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c,fr30-opc.h: Regenerated. - -1998-12-14 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 10 12:49:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Tue Dec 8 13:56:18 1998 David Taylor <taylor@texas.cygnus.com> - - * dis-buf.c (generic_strcat_address): reformat to GNU coding - conventions. change sprintf call to an sprintf_vma call. - -Tue Dec 8 13:12:44 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Tue Dec 8 10:50:46 1998 David Taylor <taylor@texas.cygnus.com> - - The following changes were made by - Elena Zannoni <ezannoni@kwikemart.cygnus.com>, - David Taylor <taylor@texas.cygnus.com>, and - Edith Epstein <eepstein@sophia.cygnus.com> as part of a project to - merge in changes by HP; HP did not create ChangeLog entries. - - * dis-buf.c (generic_strcat_address): new function. - - * hppa-dis.c: Changes to improve hppa disassembly. - Changed formatting in : reg_names, fp_reg_names,control_reg, - New variables : sign_extension_names, deposit_names, conversion_names - float_test_names, compare_cond_names_double, add_cond_names_double, - logical_cond_names_double, unit_cond_names_double, - branch_push_pop_names, saturation_names, shift_names, mix_names, - New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG - Move some definitions to libhppa.h: GET_FIELD, GET_BIT - (fput_const): renamed as fput_hex_const - (print_insn_hppa): - - use the macros fputs_filtered and - fput_decimal_const whenever possible; calls to sign_extend require - 2 params -- add a missing second param of 0. - - Some new code ifdefed for LOCAL_ONLY, all related to figuring out - architecture version number of current machine. HP folks are - trying to handle situation where the target program was compiled - for PA 1.x (32-bit), but is running on a PA 2.0 machine and - visa versa. - - added new cases : 'g', 'B', 'm' - - added cases specifically for PA 2.0 - - changed the following cases : '"', 'n', 'N', 'p', 'Z', - - calls to fput_const become calls to fput_hex_const - -1998-12-07 James E Wilson <wilson@wilson-pc.cygnus.com> - - * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. - (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. - (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. - * Makefile.in: Rebuilt. - * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, - i960-dis.c to ta. - * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. - * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. - -Mon Dec 7 14:33:44 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Sun Dec 6 14:06:48 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2. - - * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions. - From Saitoh Masanobu <msaitoh@spa.is.uec.ac.jp>. - -Fri Dec 4 17:45:51 1998 Doug Evans <devans@canuck.cygnus.com> - - * fr30-opc.c: Regenerate. - -Fri Dec 4 17:08:08 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 3 14:26:20 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 3 00:09:17 1998 Doug Evans <devans@canuck.cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. - -1998-11-30 Doug Evans <devans@casey.cygnus.com> - - * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> - CGEN_INSN_BASE_VALUE. - * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. - * fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate. - -Thu Nov 26 11:26:32 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c: Regenerated. - -Tue Nov 24 11:20:54 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c: Regenerated. - -Mon Nov 23 18:28:48 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -1998-11-20 Doug Evans <devans@tobor.to.cygnus.com> - - * fr30-opc.c: Regenerated. - -Thu Nov 19 16:02:46 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Thu Nov 19 07:54:15 1998 Doug Evans <devans@charmed.cygnus.com> - - * mips-opc.c (sync.p,sync.l): Swap insn values. - -1998-11-19 Doug Evans <devans@tobor.to.cygnus.com> - - * fr30-opc.c: Regenerate. - -Wed Nov 18 21:36:37 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - -1998-11-18 Doug Evans <devans@casey.cygnus.com> - - * m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild. - * fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild. - -Wed Nov 18 11:30:04 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - -Mon Nov 16 19:21:48 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Thu Nov 12 19:24:18 1998 Dave Brolley <brolley@cygnus.com> - - * po/opcodes.pot: Regenerated. - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com> - - * disassemble.c (disassembler): Add support for FR30 target. - -Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild. - * fr30-dis.c,fr30-opc.c,fr30-opc.h: Rebuild. - -Mon Nov 9 18:22:55 1998 Dave Brolley <brolley@cygnus.com> - - * po/opcodes.pot: Regenerate. - * po/POTFILES.in: Regenerate. - * fr30-opc.c: Regenerate. - * fr30-opc.h: Regenerate. - -Fri Nov 6 17:21:38 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c: Regenerate. - -Wed Nov 4 18:46:47 1998 Dave Brolley <brolley@cygnus.com> - - * configure.in: Added case for bfd_fr30_arch. - * Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c. - (ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo. - (CLEANFILES): Added stamp-fr30. - (FR30_DEPS): Added. - * fr30-asm.c: New file. - * fr30-dis.c: New file. - * fr30-opc.c: New file. - * fr30-opc.h: New file. - * po/POTFILES.in: Regenerated - * po/opcodes.pot: Regenerated - -Mon Nov 2 15:05:33 1998 Geoffrey Noer <noer@cygnus.com> - - * configure.in: detect cygwin* instead of cygwin32* - * configure: regenerate - -Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (IS_M): Added. - -Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. - -Fri Oct 9 14:01:56 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h,m32r-opc.c: Regenerate. - -Sun Oct 4 21:01:44 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (OP_3DNowSuffix): New static function. - (OPSUF): Define. - (GRP14): Define. - (dis386_twobyte): Add GRP14, femms, and 3DNow entries. - (twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow. - (insn_codep): New static variable. - (print_insn_x86): Init insn_codep after prefixes. - (grps): Add GRP14 entries for prefetch, prefetchw. - (OP_REG): Reformat. - - From Jeff B Epler <jepler@usgs.gov> - * i386-dis.c (Suffix3DNow): New table. - -Wed Sep 30 10:17:50 1998 Nick Clifton <nickc@cygnus.com> - - * d10v-opc.c: Treat TRAP as if it were a branch type instruction. - -Mon Sep 28 14:35:43 1998 Martin M. Hunt <hunt@cygnus.com> - - * d10v-dis.c (print_operand): If num is nonzero, then - add OPERAND_ACC1, not OPERAND_ACC0. - -Thu Sep 24 09:20:03 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP - insns. - -Tue Sep 22 17:55:14 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit - class. - -Tue Sep 15 15:14:45 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h,m32r-opc.c: Add bbpc,bbpsw support. - -1998-09-09 Michael Meissner <meissner@cygnus.com> - - * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move - to/from SPRs. - -Fri Sep 4 19:42:59 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf - object files. - (print_insn_little_arm): Detect Thumb symbols in elf object - files. - -Sat Aug 29 22:24:09 1998 Richard Henderson <rth@cygnus.com> - - * alpha-dis.c (print_insn_alpha): Use the machine type to - decide which PALcode set to include. - -Sun Aug 23 02:16:18 1998 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case. - -Fri Aug 21 16:07:52 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS, - MSUB and MSUBS instructions. - -Thu Aug 13 16:23:04 1998 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (powerpc_operands): Omit parens around additions in - operand name macros. - -Wed Aug 12 14:00:38 1998 Ian Lance Taylor <ian@cygnus.com> - - From Peter Jeremy <peter.jeremy@auss2.alcatel.com.au>: - * m68k-opc.c: Correct mulsl and mulul to use q rather than D, a, - +, -, and d for ColdFire. - - From Peter Thiemann <thiemann@informatik.uni-tuebingen.de>: - * ppc-opc.c (insert_mbe): Handle wrapping bitmasks. - (extract_mbe): Likewise. - -Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. - - * m10300-opc.c: First cut at UDF instructions. - -Mon Aug 10 14:08:22 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate (remove semantic descriptions). - -Mon Aug 10 12:51:12 1998 Catherine Moore <clm@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Fix indentation. - (print_insn_little_arm): Likewise. - -Sun Aug 9 20:17:28 1998 Catherine Moore <clm@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Check for thumb symbol - attributes. - (print_insn_little_arm): Likewise. - -Mon Aug 3 12:43:16 1998 Doug Evans <devans@seba.cygnus.com> - - Move all global state data into opcode table struct, and treat - opcode table as something that is "opened/closed". - * cgen-asm.c (all fns): New first arg of opcode table descriptor. - (cgen_asm_init): Delete. - (cgen_set_parse_operand_fn): New function. - * cgen-dis.c (all fns): New first arg of opcode table descriptor. - (cgen_dis_init): Delete. - * cgen-opc.c (all fns): New first arg of opcode table descriptor. - (cgen_current_{opcode_table_mach,endian}): Delete. - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. - -Thu Jul 30 21:41:10 1998 Frank Ch. Eigler <fche@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some - instructions. - -Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Add entries for "no_match_operands" field in - the opcode table. - -Fri Jul 24 11:41:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups). - -Tue Jul 21 13:41:07 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. - -Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (ckprefix): Handle fwait specially only when it isn't - the first prefix. - (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather - than `fnstsw %eax'. - (OP_J): Remove unnecessary subtraction when 16-bit displacement - will be masked later. - -Thu Jul 2 17:11:27 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. - -Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. - -Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-dis.c: Only recognize instructions from the currently - selected machine. - * m10300-opc.c: Add field indicating the particular variant of - the mn10300 each instruction is available on. - -Fri Jun 26 12:04:21 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: For bfd_vax_arch, build vax-dis.lo. - * Makefile.am: Rebuild dependencies. - (CFILES): Add vax-dis.c. - (ALL_MACHINES): Add vax-dis.lo. - * aclocal.m4: Rebuild with current libtool. - * configure, Makefile.in: Rebuild. - -Fri Jun 26 12:03:20 1998 Klaus Kaempf <kkaempf@progis.de> - - * vax-dis.c: New file, from work by Pauline Middelink - <middelin@polyware.iaf.nl>. - * disassemble.c (ARCH_vax): Define if ARCH_all. - (disassembler): Add case for ARCH_vax. - * makefile.vms: Support compilation on vms/vax. - -Tue Jun 23 19:42:18 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities - related to sign extension and the size of ints. - -Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Support one operand "asr", "lsr" and "asl" - instructions. Support (sp) addressing mode by expanding it into - (0,sp). - -Sat Jun 20 14:46:20 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-dis.c (_print_insn_mips): Fix argument interchange typo. - -Fri Jun 19 09:16:42 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. - -1998-06-18 Ulrich Drepper <drepper@cygnus.com> - - * i386-dis.c: Add support for fxsave, fxrstor, sysenter and - sysexit. - -Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com> - - * mips-dis.c (print_insn_little_mips): Previously, instruction - printing references the symbol table to determine whether the - instruction resides in a block regular instructions or mips16 - instructions. However, when the disassembler gets used in other - environments where the symbol table is not present, we no longer - rely in the symbol table, rather, use the low bit of the - instructions address to guess. There should be no change for usage - of the disassembler in host based programs, gdb, objdump. - (print_insn_big_mips): ditto. - (print_insn_mips): ditto - -Wed Jun 17 21:19:01 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. - -Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". - -Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (index16): Add '%' to register names. Use ',' - instead of '+'. - -Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Don't print opcode suffix when we can figure out the - size (and gas can!) by register operands, or from the default - size. - (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' - macro to 'E'. - (dis386, dis386_twobyte, grps): Use new suffix macros. - (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be - consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse - order of cmps operands to agree with Intel docs. Correct operand - of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to - agree with Intel docs. - (print_insn_x86): Print orphan fwait before other prefixes. - Return correct byte count for orphan fwait with prefixes. Don't - print `bound' operands in reverse order. - (ckprefix): Stop accumulating prefixes if we get fwait. - (OP_DIR): Print `$' before Ap operands of ljmp, lcall. - -Fri Jun 12 13:40:38 1998 Tom Tromey <tromey@cygnus.com> - - * po/Make-in (all-yes): If maintainer mode, depend on .pot file. - ($(PACKAGE).pot): Unconditionally depend on POTFILES. - -Fri Jun 12 11:04:06 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - Fix problems when bfd_vma is wider than long. - * i386-dis.c: Make op_address and start_pc unsigned. - (set_op): Make parameter unsigned. - (print_insn_x86): Cast to bfd_vma when passing a value to - print_address_func. - * ns32k-dis.c (CORE_ADDR): Don't define. - (print_insn_ns32k): Change type of addr to bfd_vma. Use - bfd_scan_vma to read back address. - (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma - to format it. - * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. - (NEXTULONG): New definition. - (print_insn_m68k): Avoid overflow when computing third argument of - print_insn_arg. - (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. - Use disp instead of val to store offset values. - (print_indexed): Use base_disp instead of word to store base - displacement, to avoid overflow. - * m10300-dis.c (disassemble): Cast value to long when computing - pc-relative address, to get correct sign extension. - -Wed Jun 10 15:58:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Tue Jun 9 14:27:57 1998 Nick Clifton <nickc@cygnus.com> - - * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as - 'mov rX, rY'. Patch courtesy of Tony Thompson <Tony.Thompson@arm.com> - -Mon Jun 8 18:17:21 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. - -Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* - functions to void. - (OP_DSreg): Rename from OP_DSSI. - (OP_ESreg): Rename from OP_ESDI. - (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. - (DSBX): Define. - (append_seg): Rename from append_prefix. - (ptr_reg): New function. - (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. - Add DSBX for xlat. - (PREFIX_ADDR): Rename from PREFIX_ADR. - (float_reg): Add non-broken opcodes for people who don't want - UNIXWARE_COMPAT. - -Fri Jun 5 19:15:04 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on - 68000/68008/68010. - -Wed Jun 3 18:56:22 1998 H.J. Lu <hjl@gnu.org> - - * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". - -Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au> - - * ppc-opc.c (powerpc_macros): Support shifts and rotates of size - 0; produce error message for shifts of size 32 (or 64 for 64-bit - shifts), because the hardware doesn't support them. - -Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, - LONG_2, LONG_2b formats to use this new operand. - -Tue May 26 20:47:48 1998 Stan Cox <scox@cygnus.com> - - * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. - -Tue May 26 20:45:33 1998 Mark Alexander <marka@cygnus.com> - - * sparc-dis.c (print_insn_sparc): big endian instruction / little - endian data support. - -Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 - and SHORT_B3b formats to use Rb instead of Ra. - - Add FLAG_MUL16 to MUL2XH opcode. - - Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension - to existing 1.1.1 parallelisation prohibition procedure. - -Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c,m32r-dis.c: Regenerate. - -Tue May 19 17:36:08 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly - with a shift count of 0. - -Fri May 15 14:58:31 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. - (cgen_hw_lookup_by_num): New function. - -Wed May 13 17:03:59 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). - -Wed May 13 14:34:31 1998 Mark Alexander <marka@cygnus.com> - - * sparc-dis.c (print_insn_sparc): Always fetch instructions - as big-endian on SPARClite. - -Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com> - - * d30v-opc.c (pre_defined_register): Remove alias for r0. - -Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) - - * po/Make-in (install-info): New target. - -Thu May 7 17:15:59 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in (WIN32LIBADD): Add -lintl on cygwin32. - * configure: Rebuild. - -Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand - variety of ISA2 instructions to set bottom ten bits of trap code. - -Thu May 7 11:54:25 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (config.status): Add explicit target so that - config.status depends upon bfd/configure.in. - * Makefile.in: Rebuild. - -Thu May 7 09:33:02 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 - instructions to set bottom ten bits of break code. - * mips-dis.c (print_insn_arg): Implement 'q' operand format used - for above optional argument. - -Wed May 6 15:30:06 1998 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Run dec c with /nodebug. - -Mon May 4 10:19:57 1998 Tom Tromey <tromey@cygnus.com> - - * Makefile.in: Rebuilt. - * Makefile.am: Regenerated dependencies with mkdep. - - * opintl.h (_): Define as dgettext. - -Tue Apr 28 14:12:12 1998 Nick Clifton <nickc@cygnus.com> - - * cgen-asm.c: Internationalised. - * m32r-asm.c: Internationalised. - * m32r-dis.c: Internationalised. - * m32r-opc.c: Internationalised. - - * aclocal.m4: Regenerated. - * configure: Regenerated. - * Makefile.am (POTFILES): Remove inclusion of BFD_H. - * Makefile.in: Rebuild. - * po/POTFILES.in: Rebuilt using rule in Makefile.in. - * po/opcodes.pot: Rebuilt after changing POTFILES.in. - -Tue Apr 28 13:13:13 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT - after AC_PROG_CC. - * aclocal.m4, configure: Rebuild with current tools. - -Mon Apr 27 14:31:00 1998 Nick Clifton <nickc@cygnus.com> - - * opintl.h: New file - contains internationalisation macros used - by source files in this directory. - * po/: New subdirectory - contains internationalisation files. - * po/Make-in: New file - Makefile constructor. - * po/POTFILES.in: New file - list of files in opcodes directory - that should be scan for internationalisation macros. - * po/opcodes.pot: New file - list of internationisation strings - found in files mentioned in po/POTFILES.in. - * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS - entry. Add intl directory to include paths. - * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, - HAVE_STRCPY, HAVE_LC_MESSAGES - * configure.in: Add rule to build Makefile in po subdirectory. - * Makefile.in: Rebuilt. - * aclocal.m4: Rebuilt. - * config.in: Rebuilt. - * configure: Rebuilt. - * alpha-opc.c: Internationalised. - * arc-dis.c: Internationalised. - * arc-opc.c: Internationalised. - * arm-dis.c: Internationalised. - * cgen-asm.c: Internationalised. - * d30v-dis.c: Internationalised. - * dis-buf.c: Internationalised. - * h8300-dis.c: Internationalised. - * h8500-dis.c: Internationalised. - * i386-dis.c: Internationalised. - * m10200-dis.c: Internationalised. - * m10300-dis.c: Internationalised. - * m68k-dis.c: Internationalised. - * m88k-dis.c: Internationalised. - * mips-dis.c: Internationalised. - * ns32k-dis.c: Internationalised. - * opintl.h: Internationalised. - * ppc-opc.c: Internationalised. - * sparc-dis.c: Internationalised. - * v850-dis.c: Internationalised. - * v850-opc.c: Internationalised. - -Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. - (asm_hash_table_entries): New variable. - (cgen_asm_init): Free asm_hash_table_entries. - (hash_insn_array,hash_insn_list): New functions. - (build_asm_hash_table): Use them. Hash macro insns as well. - (cgen_asm_lookup_insn): Update. - * cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data. - (dis_hash_table_entries): New variable. - (cgen_dis_init): Free dis_hash_table_entries. - (hash_insn_array,hash_insn_list): New functions. - (build_dis_hash_table): Use them. Hash macro insns as well. - (cgen_dis_lookup_insn): Update. - * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. - (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. - (cgen_macro_insn_count): New function. - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. - -Fri Apr 24 16:07:57 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (OP_DSSI): Print segment override. - -Mon Apr 13 16:59:39 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' - operator. - -Mon Apr 13 16:50:27 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. - (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. - * configure.in: Define and substitute WIN32LDFLAGS and - WIN32LIBADD. - * aclocal.m4: Rebuild with new libtool. - * configure, Makefile.in: Rebuild. - -Fri Apr 10 18:14:31 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Sun Apr 5 16:04:39 1998 H.J. Lu <hjl@gnu.org> - - * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists - before trying to copy it. - * Makefile.in: Rebuild. - -Thu Apr 2 17:25:49 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Use signed immediate values for CMPUI instruction. - -Wed Apr 1 16:20:27 1998 Ian Dall <Ian.Dall@dsto.defence.gov.au> - - * ns32k-dis.c (bit_extract_simple): New function to extract bits - from an arbitrary valid buffer instead of fetching them on demand - using fetch_data(). - (invalid_float): use bit_extract_simple() instead of bit_extract(). - -Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com> - - From H.J. Lu <hjl@gnu.org>: - * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew - to Ev for both. - -Mon Mar 30 17:32:03 1998 Ian Lance Taylor <ian@cygnus.com> - - * Branched binutils 2.9. - -Mon Mar 30 15:18:00 1998 Ken Raeburn <raeburn@cygnus.com> - - * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when - disassembling last 4 bytes of a section. - -Fri Mar 27 18:08:13 1998 Ian Lance Taylor <ian@cygnus.com> - - Fix some gcc -Wall warnings: - * arc-dis.c (print_insn): Add casts to avoid warnings. - * cgen-opc.c (cgen_keyword_lookup_name): Likewise. - * d10v-dis.c (dis_long, dis_2_short): Likewise. - * m10200-dis.c (disassemble): Likewise. - * m10300-dis.c (disassemble): Likewise. - * ns32k-dis.c (print_insn_ns32k): Likewise. - * ppc-opc.c (insert_ral, insert_ram): Likewise. - * cgen-dis.c (build_dis_hash_table): Remove used local variables. - * cgen-opc.c (cgen_keyword_search_next): Likewise. - * d10v-dis.c (dis_long, dis_2_short): Likewise. - * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. - * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. - * tic80-dis.c (print_one_instruction): Likewise. - * w65-dis.c (print_operand): Likewise. - * z8k-dis.c (fetch_data): Likewise. - * a29k-dis.c: Add return type for find_byte_func_type. - * arc-opc.c: Include <stdio.h>. Remove declarations of - insert_multshift and extract_multshift. - * d30v-dis.c (lookup_opcode): Parenthesize assignments in - conditionals. - (extract_value): Fully parenthesize expression. - * h8500-dis.c (print_insn_h8500): Initialize local variables. - * h8500-opc.h (h8500_table): Fully bracket initializer. - * w65-opc.h (optable): Likewise. - * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. - * i386-dis.c (OP_E): Initialize local variables. - * m10200-dis.c (print_insn_mn10200): Likewise. - * mips-dis.c (print_insn_mips16): Likewise. - * sh-dis.c (print_insn_shx): Likewise. - * v850-dis.c (print_insn_v850): Likewise. - * ns32k-dis.c (print_insn_arg): Declare. - (get_displacement, invalid_float): Declare. - (list_search, sign_extend, flip_bytes): Declare return type. - (get_displacement): Likewise. - (print_insn_arg): Likewise. Make d int. Fix sprintf format - string. - (print_insn_ns32k): Make i unsigned. - (invalid_float): Make static. Declare type of val. - * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen - on each for iteration. - * tic30-dis.c (get_indirect_operand): Likewise. - * z8k-dis.c (print_insn_z8001): Declare return type. - (print_insn_z8002): Likewise. - (unparse_instr): Fix sprintf format strings. - -Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Add "sync.l" and "sync.p". - -Wed Mar 25 14:32:48 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Use info->mach to select the - default m68k variant to recognize. - - * i960-dis.c (pinsn): Change type of first argument to bfd_vma. - (ctrl, cobr, mem, ea): Likewise. - (print_addr): Likewise. Remove cast. - (ea): Cast argument of print_addr to bfd_vma. - - * cgen-asm.c (cgen_parse_signed_integer): Fix type of local - variable value. - (cgen_parse_unsigned_integer): Likewise. - (cgen_parse_address): Likewise. - -Wed Mar 25 14:31:31 1998 Ian Lance Taylor <ian@cygnus.com> - - * i960-dis.c (ctrl): Add full braces to structure initialization. - (cobr, mem, reg): Likewise. - (ea): Correct parenthesization in expression. - - * cgen-asm.c: Include <ctype.h>. - (build_asm_hash_table): Remove unused local variable i. - (cgen_parse_keyword): Add casts to avoid warnings. - - * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF - symbol. Fix indentation. - (print_insn_little_arm): Likewise. - -Fri Mar 20 18:55:18 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use AM_DISABLE_SHARED. - * aclocal.m4, configure: Rebuild with libtool 1.2. - -Thu Mar 19 15:46:53 1998 Nick Clifton <nickc@cygnus.com> - - These patches are courtesy of Jonathan Walton and Tony Thompson - (athompso@cambridge.arm.com). - - * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC - relative addresses. - - * arm-opc.h (thumb_opcodes): Annotate PC relative addresses with - both the offset and the label closest to the destination. - -Sat Mar 14 23:47:14 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h: Regenerate. - -Wed Mar 4 12:08:14 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. - -Sat Feb 28 16:02:34 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not - assume that info->symbols is non-empty. - -Sat Feb 28 12:19:05 1998 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (cvtqs) There is no such thing. - (cvttq): Missing most of the /*d variants. - -Thu Feb 26 15:53:09 1998 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Indicate which instructions are - delayed branches or jumps. - -Tue Feb 24 10:46:44 1998 Doug Evans <devans@canuck.cygnus.com> - - * arm-dis.c (print_insn_{big,little}_arm): info->symbol changed - to *info->symbols. - * mips-dis.c (print_insn_{big,little}_mips): Likewise. - * tic30-dis.c (print_branch): Likewise. - -Tue Feb 24 11:06:18 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove - saved_symbol code as it is no longer needed. - -Mon Feb 23 13:16:17 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c: Include symcat.h. - * cgen-dis.c,cgen-opc.c: Ditto. - * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. - -Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'. - -Thu Feb 19 16:51:13 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.[ch]: Regenerate. - -Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max - arguments. Don't perform validation here. - * m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate. - -Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Fri Feb 13 14:53:02 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (AUTOMAKE_OPTIONS): Define. - * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e. - -Fri Feb 13 10:21:09 1998 Mark Alexander <marka@cygnus.com> - - * m10300-dis.c (print_insn_mn10300): Recognize break instruction. - -Fri Feb 13 13:12:14 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Get the version number from BFD. - * configure: Rebuild. - - From H.J. Lu <hjl@gnu.org>: - * Makefile.am (libopcodes_la_LDFLAGS): Define. - * Makefile.in: Rebuild. - -Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. - -Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> - - Fix rac to accept only a0: - * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): - Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. - Introduce OPERAND_GPR. - * d10v-dis.c (print_operand): Likewise. - -Wed Feb 11 18:58:34 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. - (cgen_hw_lookup): Make result const. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Sat Feb 7 15:30:27 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure, aclocal.m4: Rebuild with new libtool. - -Thu Feb 5 17:56:10 1998 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (repeat{,i} instructions): Repeat/repeati - instructions use a PC relative branch, not absolute. - -Wed Feb 4 19:17:37 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set libtool_enable_shared rather than - libtool_shared. Remove diversion hack. - * configure, Makefile.in, aclocal.m4: Rebuild with new libtool. - -Tue Feb 3 17:19:40 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Initialize hardware table. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Mon Feb 2 19:22:15 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> - - * tic30-dis.c: New file. - * disassemble.c (disassembler): Add bfd_arch_tic30 case. - * configure.in: Handle bfd_tic30_arch. - * Makefile.am: Rebuild dependencies. - (CFILES): Add tic30-dis.c - (ALL_MACHINES): Add tic30-dis.lo. - * configure, Makefile.in: Rebuild. - -Thu Jan 29 13:02:56 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h (HAVE_CPU_M32R): Define. - -Wed Jan 28 09:55:03 1998 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (insertion routines): If both alignment and size is - wrong then report this. - -Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (_print_insn_mips): Set target_processor as appropriate. - Only recognize instructions for the current target_processor. - -Thu Jan 22 16:20:17 1998 Fred Fish <fnf@cygnus.com> - - * d10v-dis.c (PC_MASK): Correct value. - (print_operand): If there's a reloc, don't calculate the - address because they could be in different sections. - -Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu" - instruction after the 4650's "mul" instruction; nobody's using the - 4010 these days. If object files someday indicate which processor - variant they're intended for, we can do a better job at this. - -Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using - table provided entry size. Use CGEN_INSN_MNEMONIC. - (cgen_parse_keyword): Rewrite. - * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using - table provided entry size. Use CGEN_INSN_MASK_BITSIZE. - * cgen-opc.c: Clean up pass over `struct foo' usage. - (cgen_keyword_lookup_value): Handle "" entry. - (cgen_keyword_add): Likewise. - -Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add FP_D to s.d instruction flags. - -Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (halt, pulse): Enable them on the 68060. - -Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit - PC relative offset forms before the 15 bit forms. An assembler command - line option now chooses the default. - -Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Set new flags bits - FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions. - -1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com> - - * configure: Only build libopcodes shared if --enable-shared's value - was `yes', or was set to `*opcodes*'. - * aclocal.m4: Likewise. - * NOTE: this really needs to be fixed in libtool/libtool.m4, the - original source of this bit of code. It's not clear what the best fix - would be, though. - -Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change. - (tic80_opcodes): Reorder table entries to put the 32 bit PC relative - offset forms before the 15 bit forms, to default to the long forms. - -Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid. - -Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_little_arm): Prevent examination of stored - symbol if none is present. - (print_insn_big_arm): Prevent examination of stored symbol if - none is present. - -Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com> - - * d10v-opc.c (d10v_opcodes): Correct entry for RTE. - -Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com> - - * disassemble.c: Remove disasm_symaddr() function. - - * arm-dis.c: Use info->symbol instead of info->flags to determine - if disassmbly should be in Thumb or Arm mode. - -Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c: Add support for disassembling Thumb opcodes. - (print_insn_thumb): New function. - - * disassemble.c (disasm_symaddr): New function. - - * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly. - (thumb_opcodes): Table of Thumb opcodes. - -Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (btst): Change Dd@s to Dd;b. - - * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q', - and 'v' as operand types. - -Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add argument for lpstop. From Olivier Carmona - <olivier.carmona@di.epfl.ch>. - * m68k-dis.c (print_insn_m68k): Handle special case of lpstop, - which has a two word opcode with a one word argument. - -Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is - unsigned, not signed. - (d30v_format_table): Add SHORT_CMPU cases for cmpu. - -Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v-dis.c (print_operand): - Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG. - -Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v-opc.c (OPERAND_FLAG): Split into: - (OPERAND_FFLAG, OPERAND_CFLAG) . - (FSRC): Split into: - (FFSRC, CFSRC). - -Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Move the INSN_MACRO ISA value to the membership - field for all INSN_MACRO's. - * mips16-opc.c: same - -Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (sync,cache): These are 3900 insns. - -Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - sh-opc.h (sh_table): Remove ftst/nan. - -Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c (ffc, ffs): Fix mask. - -Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m - control registers. - -Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. - (WR_HILO, RD_HILO, MOD_HILO): New macros. - -Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. - (WR_HILO, RD_HILO, MOD_HILO): New macros. - -Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Replace // with /* ... */ - -Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c: Add wr & rd for v9a asr's. - * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's. - (v9a_asr_reg_names): New variable. - Patch from David Miller <davem@vger.rutgers.edu>. - -Wed Oct 22 17:18:02 1997 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c (v9notv9a): New insn type. - (IMPDEP): Move to the end to not conflict with edge8 et al. - Patch from David Miller <davem@vger.rutgers.edu>. - -Fri Oct 17 13:18:53 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (bnezl,beqzl): Mark these as also tx39. - -Thu Oct 16 11:55:20 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. - -Tue Oct 14 16:10:31 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Use new symbol_at_address_func() field - of disassemble_info structure to determine if an overlay address - has a matching symbol in low memory. - - * dis-buf.c (generic_symbol_at_address): New (dummy) function for - new symbol_at_address_func field in disassemble_info structure. - -Fri Oct 10 16:44:52 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (extract_d22): Use signed arithmatic. - -Tue Oct 7 23:40:43 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Three op mult is not an ISA insn. - -Tue Oct 7 23:37:21 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Fix formatting. - -Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather - than assuming that char is signed. Explicitly sign extend 16 bit - values, rather than assuming that short is 16 bits. - (OP_sI, OP_J, OP_DIR): Likewise. - -Thu Oct 2 13:36:45 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (v850_sreg_names): Use symbolic names for higher - system registers. - -Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Fix typo in comment. - - * v850-dis.c (disassemble): Add test of processor type when - determining opcodes. - -Wed Oct 1 14:10:20 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use a diversion to set enable_shared before the - arguments are parsed. - * configure: Rebuild. - -Thu Sep 25 13:04:59 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (TBL1): Use ! rather than `. - * m68k-dis.c (print_insn_arg): Remove ` operand specifier. - -Wed Sep 24 11:29:35 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. - - * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. - - * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr - for mcf5200. - - * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. - * aclocal.m4: Rebuild with new libtool. - * configure: Rebuild. - -Fri Sep 19 11:45:49 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2. - -Thu Sep 18 11:21:43 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. - -Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes): Further rearrangements. - -Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com> - - * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. - -Tue Sep 16 09:48:50 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes): Fields reordered to allow assembler - parser to work. - -Tue Sep 16 10:01:00 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. - -Mon Sep 15 18:31:52 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Initialise processors field of v850_opcode structure. - -Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com> - - Merge changes from Martin Hunt: - - * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values. - - * d30v-opc.c (pre_defined_registers): Add control registers from 0-63. - (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix - rot2h, sra2h, and srl2h to use new SHORT_A5S format. - - * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes. - - * d30v-dis.c (print_insn): First operand of d*i (delayed - branch) instructions is relative. - - * d30v-opc.c (d30v_opcode_table): Change form for repeati. - (d30v_operand_table): Add IMM6S3 type. - (d30v_format_table): Change SHORT_D2. Add LONG_Db. - - * d30v-dis.c: Fix bug with ".s" and ".l" extensions - and cmp instructions. - - * d30v-opc.c: Correct entries for repeat*, and sat*. - Make IMM5 unsigned. Create IMM6U and IMM12S3U operand - types. Correct several formats. - - * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. - - * d30v-opc.c (pre_defined_registers): Change control registers. - - * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and - SHORT_C2. Manual was incorrect. - - * d30v-dis.c (lookup_opcode): Return value now indicates - if an opcode has a short and a long form. Used for deciding - to append a ".s" or ".l". - (print_insn): Append a ".s" to an instruction if it is - the short form and ".l" if it is a long form. Do not append - anything if the instruction has only one possible size. - - * d30v-opc.c: Change mulx2h to require an even register. - New form: SHORT_A2; a SHORT_A form that needs an even - register as the first operand. - - * d30v-dis.c (print_insn_d30v): Fix problem where the last - instruction was not being disassembled if there were an odd - number of instructions. - - * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms. - -Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Improved display of register lists. - -Thu Sep 11 17:35:10 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix assembler args to - fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s, - fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s, - fandnot1s, fandnot2s. - -Tue Sep 9 10:03:49 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. - -Mon Sep 8 14:06:59 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-asm.c (cgen_parse_address): New argument resultp. - All callers updated. - * m32r-asm.c (parse_h_hi16): Right shift numbers by 16. - -Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c (disassemble): PC relative instructions are - relative to the next instruction, not the current instruction. - -Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Only signed extend values that are not - returned by extract functions. - Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag. - -Tue Sep 2 15:39:40 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Update comments. Remove use of - V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns. - -Tue Aug 26 09:42:28 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (MOVHI): Immediate parameter is unsigned. - -Mon Aug 25 15:58:07 1997 Christopher Provenzano <proven@cygnus.com> - - * configure: Rebuilt with latest devo autoconf for NT support. - -Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Use curly brace syntax for register - lists. - - * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases - where r0 is being used as a destination register. - -Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other. - -Tue Aug 19 10:59:59 1997 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage. - -Mon Aug 18 11:10:03 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes[]): Remove use of flag field. - * v850-opc.c (v850_opcodes[]): Add support for reversed short load - opcodes.. - -Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> - - * configure (cgen_files): Add support for v850e target. - * configure.in (cgen_files): Add support for v850e target. - -Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> - - * configure (cgen_files): Add support for v850ea target. - * configure.in (cgen_files): Add support for v850ea target. - -Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com> - - * configure.in (bfd_arc_arch): Add. - * configure: Rebuild. - * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo. - * Makefile.in: Rebuild. - * arc-dis.c, arc-opc.c: New files. - * disassemble.c (ARCH_all): Define ARCH_arc. - (disassembler): Add ARC support. - -Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Add support for v850EA instructions. - - * v850-opc.c (insert_i5div, extract_i5div): New Functions. - (v850_opcodes): Add v850EA instructions. - - * v850-dis.c (disassemble): Add support for v850E instructions. - - * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, - extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, - insert_spe, extract_spe): New Functions. - (v850_opcodes): Add v850E instructions. - - * v850-opc.c: Reorganised and re-layed out to improve readability - and portability. - -Tue Aug 5 23:09:31 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.12.1. - -Mon Aug 4 12:02:16 1997 Ian Lance Taylor <ian@cygnus.com> - - * aclocal.m4, configure: Rebuild with new automake patches. - -Fri Aug 1 13:02:04 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set enable_shared before AM_PROG_LIBTOOL. - * acinclude.m4: Just include acinclude.m4 from BFD. - * aclocal.m4, configure: Rebuild. - -Thu Jul 31 21:44:42 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am: New file, based on old Makefile.in. - * acconfig.h: New file. - * acinclude.m4: New file. - * stamp-h.in: New file. - * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL. - Removed shared library handling; now handled by libtool. Replace - AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE, - AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with - AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h - handling in AC_OUTPUT. - * dep-in.sed: Change .o to .lo. - * Makefile.in: Now built with automake. - * aclocal.m4: Now built with aclocal. - * config.in, configure: Rebuild. - -Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Fix typo/thinko in "eret" instruction. - -Thu Jul 24 13:03:26 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. - Make array const. - * sparc-dis.c (sorted_opcodes): New static local. - (struct opcode_hash): `opcode' is pointer to const element. - (build_hash): First arg is now table of sorted pointers. - (print_insn_sparc): Sort opcodes by sorting table of pointers. - (compare_opcodes): Update. - -Tue Jul 15 12:05:23 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-opc.c: #include <ctype.h>. - (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. - Handle case insensitive hashing. - (hash_keyword_value): Change type of `value' to unsigned int. - -Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (mips_builtin_opcodes): If an insn uses single - precision FP, mark it as such. Likewise for double precision - FP. Mark ISA1 insns. Consolidate duplicate opcodes where - possible. - -Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com> - - * ppc-opc.c (extract_nsi): make unsigned expression signed before - negating it. - (UNUSED): remove one level of parens, so MSVC doesn't choke on - nesting depth when all the macros are expanded. - -Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: The fcmp v9a instructions take an integer register - as a destination, not a floating point register. From Christian - Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>. - -Mon Jun 16 14:13:18 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() - syntax. From Roman Hodek - <rnhodek@faui22c.informatik.uni-erlangen.de>. - - * i386-dis.c (twobyte_has_modrm): Fix pand. - -Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu> - - * i386-dis.c (dis386_twobyte): Fix pand and pandn. - -Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * arm-dis.c: Add prototypes for arm_decode_shift and - print_insn_arm. - -Mon Jun 2 11:39:04 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Add r3900 insns. - -Tue May 27 15:55:44 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't - print delay slot instructions on the same line. When using a PC - relative load, add a comment with the value being loaded if it can - be obtained. - -Tue May 27 11:02:08 1997 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl - to pushS/popS for segment regs and byte constant so that - pushw/popw printed when in 16 bit data mode. - - * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to - print cbtw, cwtd in 16 bit data mode. - * i386-dis.c (putop): extra case W to support above. - - * i386-dis.c (print_insn_x86): print addr32 prefix when given - address size prefix in 16 bit address mode. - -Fri May 23 16:47:23 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c: Reindent. Rename local variable fprintf to - fprintf_fn. - -Thu May 22 14:06:02 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. - -Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new - field membership. - * mips16-opc.c (mip16_opcodes): same. - -Mon May 12 15:10:53 1997 Jim Wilson <wilson@cygnus.com> - - * m68k-opc.c (moveb): Change $d to %d. - -Mon May 5 14:28:41 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c: (dis386_twobyte): Add MMX instructions. - (twobyte_has_modrm): Likewise. - (grps): Likewise. - (OP_MMX, OP_EM, OP_MS): New static functions. - - * i386-dis.c: Revert patch of April 4. The output now matches - what gcc generates. - -Fri May 2 12:48:37 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead - of $simm16. - -Thu May 1 15:34:15 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. - -Tue Apr 15 12:40:08 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (install): Depend upon installdirs. - (installdirs): New target. - -Mon Apr 14 12:13:51 1997 Ian Lance Taylor <ian@cygnus.com> - - From Thomas Graichen <graichen@rzpd.de>: - * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. - * configure: Rebuild. - -Sun Apr 13 17:50:41 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. - Delete string{,s}.h support. - -Thu Apr 10 14:44:56 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-asm.c (cgen_parse_operand_fn): New global. - (cgen_parse_{{,un}signed_integer,address}): Update call to - cgen_parse_operand_fn. - (cgen_init_parse_operand): New function. - * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed - from cgen_asm_init_parse. - (m32r_cgen_assemble_insn): New operand `errmsg'. - Delete call to as_bad, return error message to caller. - (m32r_cgen_asm_hash_keywords): #if 0 out. - -Wed Apr 9 12:05:25 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, - not data register. - [case 'J']: Fix typo in register name. - -Mon Apr 7 16:48:22 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Substitute SHLIB_LIBS. - * configure: Rebuild. - * Makefile.in (SHLIB_LIBS): New variable. - ($(SHLIB)): Use $(SHLIB_LIBS). - -Mon Apr 7 11:45:44 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. - - * cgen-opc.c (hash_keyword_name): Improve algorithm. - - * disassemble.c (disassembler): Handle m32r. - -Fri Apr 4 12:29:38 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. - * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. - * Makefile.in (CFILES): Add them. - (ALL_MACHINES): Add them. - (dependencies): Regenerate. - * configure.in (cgen_files): New variable. - (bfd_m32r_arch): Add entry. - * configure: Regenerate. - -Fri Apr 4 14:04:16 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Correct file names for bfd_mn10[23]00_arch. - * configure: Rebuild. - - * Makefile.in: Rebuild dependencies. - - * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". - - * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and - fdivp. - -Thu Apr 3 13:22:45 1997 Ian Lance Taylor <ian@cygnus.com> - - * Branched binutils 2.8. - -Wed Apr 2 12:23:53 1997 Ian Lance Taylor <ian@cygnus.com> - - * m10200-dis.c: Rename from mn10200-dis.c. - * m10200-opc.c: Rename from mn10200-opc.c. - * m10300-dis.c: Rename from mn10300-dis.c - * m10300-opc.c: Rename from mn10300-opc.c. - * Makefile.in: Update accordingly. - - * mips16-opc.c: Add mul and dmul macros. - -Tue Apr 1 16:27:45 1997 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Update CFLAGS, add clean target. - -Fri Mar 28 12:10:09 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add "wait". From Ralf Baechle - <ralf@gnu.ai.mit.edu>. - - * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. - * configure, config.in: Rebuild. - * sysdep.h: Include <stdlib.h> if it exists. - * sparc-dis.c: Include <stdio.h> and "sysdep.h". Don't include - <string.h>. - * Makefile.in: Rebuild dependencies. - -Thu Mar 27 14:24:43 1997 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From - Andrew Bray <andy@madhouse.demon.co.uk>. - - * mips-opc.c: Add cast when setting mips_opcodes. - -Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com) - - * v850-dis.c (disassemble): Fix sign extension problem. - * v850-opc.c (extract_d*): Fix sign extension problems to make - disassembly calculate branch offsets correctly. - -Mon Mar 24 13:22:13 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. - - * mips-opc.c: Add dctr and dctw. - -Sun Mar 23 18:08:10 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v-dis.c (print_insn): Change the way signed constants - are displayed. - -Fri Mar 21 14:37:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (BFD_H): New variable. - (HFILES): New variable. - (CFILES): Add all C files. - (.dep, .dep1, dep.sed, dep, dep-in): New targets. - Delete old dependencies, and build new ones. - * dep-in.sed: New file. - -Thu Mar 20 19:03:30 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}. - -Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c: Change "trap" to "syscall". - * mn10300-opc.c: Add new "syscall" instruction. - -Mon Mar 17 08:48:03 1997 J.T. Conklin <jtc@beauty.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and - mulul insns on the coldfire. - -Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com> - - * arm-dis.c (print_insn_arm): Don't print instruction bytes. - (print_insn_big_arm): Set bytes_per_chunk and display_endian. - (print_insn_little_arm): Likewise. - -Fri Mar 14 15:08:59 1997 Ian Lance Taylor <ian@cygnus.com> - - Based on patches from H.J. Lu <hjl@lucon.org>: - * i386-dis.c (fetch_data): Add prototype. - * m68k-dis.c (fetch_data): Add prototype. - (dummy_print_address): Add prototype. Make static. - * ppc-opc.c (valid_bo): Add prototype. - * sparc-dis.c (build_hash_table): Add prototype. - (is_delayed_branch, compute_arch_mask): Add prototypes. - (print_insn_sparc): Make several local variables const. - (compare_opcodes): Change arguments to const PTR. Add prototype. - * sparc-opc.c (arg): Change name field to be const. - (lookup_name, lookup_value): Add prototypes. Change table and - name parameters to be const. - (sparc_encode_asi): Change name parameter to be const. - (sparc_encode_membar, sparc_encode_prefetch): Likewise. - (sparc_encode_sparclet_cpreg): Likewise. - (sparc_decode_asi): Change return type to be const. - (sparc_decode_membar, sparc_decode_prefetch): Likewise. - (sparc_decode_sparclet_cpreg): Likewise. - -Fri Mar 7 10:51:49 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since - Solaris doesn't like the combined options, and the -f is - unnecessary. - (stamp-tshlink, install): Likewise. - -Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these - as relaxable. - -Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. - -Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on - the mc68000. - -Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. - -Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8. - -Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Define r25 properly. - -Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use - floatformat_to_double to make portable. - (print_insn_arg): Use NEXTEXTEND macro when extracting extended - precision float. - -Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com> - - * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes, - and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes. - -Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to - d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. - -Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (LSI_SCALED): Renamed from this ... - (OFF_SL_BR_SCALED): ... to this, and added the flag - TIC80_OPERAND_BASEREL to the flags word. - (tic80_opcodes): Replace all occurances of LSI_SCALED with - OFF_SL_BR_SCALED. - -Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> - - * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, - and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table - dynamically. - -Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Revert change to - store BITNUM values in the table in one's complement form - to match behavior when assembler is given a raw numeric - value for a BITNUM operand. - * tic80-dis.c (print_operand_bitnum): Ditto. - -Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v-opc.c: Removed references to FLAG_X. - -Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in: Add dependencies on ../bfd/bfd.h as required. - -Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * Makefile.in: Added d30v object files. - * configure: (bfd_d30v_arch) Rebuilt. - * configure.in: (bfd_d30v_arch) Added new case. - * d30v-dis.c: New file. - * d30v-opc.c: New file. - * disassemble.c (disassembler) Add entry for d30v. - -Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Add symbolic - representations for the floating point BITNUM values. - -Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values - in the table in one's complement form, as they appear in the - actual instruction. - (tic80_symbol_to_value): Use macros to access predefined - symbol fields. - (tic80_value_to_symbol): Ditto. - (tic80_next_predefined_symbol): New function. - * tic80-dis.c (print_operand_bitnum): Remove code that did - one's complement for BITNUM values. - -Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Remove 8 bit characters. Update to latest - gcc release. - -Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction. - -Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (IMM16_PCREL): This is a signed operand. - (IMM24_PCREL): Likewise. - -Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base - address for an extended PC relative instruction that is not a - branch. - -Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and - bytes_per_line. - -Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. - (tic80_opcodes): Sort entries so that long immediate forms - come after short immediate forms, making it easier for - assembler to select the right one for a given operand. - -Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and - display_endian. - (print_insn_mips16): Likewise. - -Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_symbol_to_value): Changed to accept - a symbol class that restricts translation to just that - class (general register, condition code, etc). - -Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, - and REG_DEST_E for register operands that have to be - an even numbered register. Add REG_FPA for operands that - are one of the floating point accumulator registers. - Add TIC80_OPERAND_MASK to flags for ENDMASK operand. - (tic80_opcodes): Change entries that need even numbered - register operands to use the new operand table entries. - Add "or" entries that are identical to "or.tt" entries. - -Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Add new cases of exit instruction for - disassembler. - * mips-dis.c (print_mips16_insn_arg): Display floating point - registers in operands of exit instruction. Print `$' before - register names in operands of entry and exit instructions. - -Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Table of name/value - pairs for all predefined symbols recognized by the assembler. - Also used by the disassembling routines. - (tic80_symbol_to_value): New function. - (tic80_value_to_symbol): New function. - * tic80-dis.c (print_operand_control_register, - print_operand_condition_code, print_operand_bitnum): - Remove private tables and use tic80_value_to_symbol function. - -Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c (print_operand): Change address printing - to correctly handle PC wrapping. Fixes PR11490. - -Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative - branches relaxable. - -Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_mips16): Set insn_info information. - (print_mips16_insn_arg): Likewise. - - * mips-dis.c (print_insn_mips16): Better handling of an extend - opcode followed by an instruction which can not be extended. - -Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Changed operand specifier for the - coldfire moveb instruction to not allow an address register as - destination. Although the documentation does not indicate that - this is invalid, experiments uncovered unexpected behavior. - Added a comment explaining the situation. Thanks to Andreas - Schwab for pointing this out to me. - -Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_opcodes): Expand comment to note that the - entries are presorted so that entries with the same mnemonic are - adjacent to each other in the table. Sort the entries for each - instruction so that this is true. - -Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c: Include <libiberty.h>. - (print_insn_m68k): Sort the opcode table on the most significant - nibble of the opcode. - -Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", - "vsub", "vst", "xnor", and "xor" instructions. - (V_a1): Renamed from V_a, msb of accumulator reg number. - (V_a0): Add macro, lsb of accumulator reg number. - -Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Broke excessively long - function up into several smaller ones and arranged for - the instruction printing function to be callable recursively - to print vector instructions that have both a load and a - math instruction packed into a single opcode. - * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode - to explain why it comes after the other vector opcodes. - -Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com> - - * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire - move insns to handle immediate operands. - -Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". - fix operand mask in the "moveml" entries for the coldfire. - -Thu Jan 16 20:54:40 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): - New macros for building vector instruction opcodes. - (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and - FMT_LI, which were unused. The field is now a flags field. - Remove some opcodes that are possible, but illegal, such - as long immediate instructions with doubles for immediate - values. Add "vadd" and "vld" instructions. - -Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Reorder some table entries to make - the order more logical. Move the shift alias instructions ("rotl", - "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be - interspersed with the regular sr.x and sl.x instructions. Add - and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", - "sub", "subu", "swcr", and "trap". - -Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. - (OFF_SL_PC): Renamed from OFF_SL. - (OFF_SS_BR): New operand type for base relative operand. - (OFF_SL_BR): New operand type for base relative operand. - (REG_BASE): New operand type for base register operand. - (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", - "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", - "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" - instructions. - * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width - 10 char field, padded with spaces on rhs, rather than a string - followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather - than old TIC80_OPERAND_RELATIVE. Add support for new - TIC80_OPERAND_BASEREL flag bit. - -Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Print floating point operands - as floats. - * tic80-opc.c (SPFI): Add single precision floating point - immediate operand type. - (ROTATE): Add rotate operand type for shifts. - (ENDMASK): Add for shifts. - (n): Macro for the 'n' bit. - (i): Macro for the 'i' bit. - (PD): Macro for the 'PD' field. - (P2): Macro for the 'P2' field. - (P1): Macro for the 'P1' field. - (tic80_opcodes): Add entries for "exts", "extu", "fadd", - "fcmp", and "fdiv". - -Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c (disassemble): Mask off unwanted bits after - adding in current address for pc-relative operands. - -Mon Jan 6 10:56:25 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. - (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. - * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names - changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. - (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, - REG_BASE_M_SI, REG_BASE_M_LI respectively. - (REG_SCALED, LSI_SCALED): New operand types. - (E): New macro for 'E' bit at bit 27. - (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap - opcodes, including the various size flavors (b,h,w,d) for - the direct load and store instructions. - -Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit - in an instruction. - * tic80-dis.c (print_insn_tic80): Change comma and paren handling. - Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. - * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. - (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. - (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode - masks with "MASK_* & ~M_*" to get the M bit reset. - (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. - -Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE - correctly. Add support for printing TIC80_OPERAND_BITNUM and - TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic - form. - * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, - CC, SICR, and LICR table entries. - (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", - "bcnd", and "brcr" opcodes. - -Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com> - - * ppc-opc.c (powerpc_operands): Make comment match the - actual fields (no shift field). - * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". - * tic80-dis.c (print_insn_tic80): Replace abort stub with a - partial implementation, work in progress. - * tic80-opc.c (tic80_operands): Begin construction operands table. - (tic80_opcodes): Continue populating opcodes table and start - filling in the operand indices. - (tic80_num_opcodes): Add this. - -Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add #B case for moveq. - -Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Make sure all variables are initialized - before they are used. - -Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Put curly-braces around operands - for "breakpoint" instruction. - -Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. - (dep): Use ALL_CFLAGS rather than CFLAGS. - -Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY - flag. - -Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com> - - * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. - (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. - -Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Add "abs". - -Sun Dec 29 10:58:22 1996 Fred Fish <fnf@cygnus.com> - - * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. - * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. - (disassembler): Add bfd_arch_tic80 support to set disassemble - to print_insn_tic80. - * tic80-dis.c (print_insn_tic80): Add stub. - -Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com> - - * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. - * configure: Regenerate with autoconf. - * tic80-dis.c: Add file. - * tic80-opc.c: Add file. - -Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. - -Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_operands): Add SIMM16N. - (mn10200_opcodes): Use it for some logicals and btst insns. - Add "break" and "trap" instructions. - - * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. - - * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". - -Sat Dec 14 22:36:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): The base address of a PC - relative load or add now depends upon whether the instruction is - in a delay slot. - -Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c: Finish writing disassembler. - * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". - Fix mask for "jmp (an)". - - * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently - handle endianness issues for mn10300. - - * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". - -Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 - instruction. Fix opcode field for "movb (imm24),dn". - - * mn10200-opc.c (mn10200_operands): Fix insertion position - for DI operand. - -Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c: Create mn10200 opcode table. - * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, - but moving along nicely. - -Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * Makefile.in (ALL_MACHINES): Add mips16-opc.o. - -Fri Dec 6 16:47:40 1996 J.T. Conklin <jtc@rhino.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Revert change to use < and > - specifiers for fmovem* instructions. - -Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Remove '$' register prefixing. - -Fri Dec 6 17:34:39 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Change opcode for entry/exit to avoid conflicting - with dsrl. - -Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c: Add some comments explaining the various - operands and such. - - * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings. - -Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-dis.c (print_insn_arg): Handle new < and > operand - specifiers. - - * m68k-opc.c (m68k_opcodes): Simplify table by using < and > - operand specifiers in fmovm* instructions. - -Wed Dec 4 14:52:18 1996 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (insert_li): Give an error if the offset has the two - least significant bits set. - -Wed Nov 27 13:09:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_mips16): Separate the instruction from - the arguments with a tab, not a space. - -Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disasemble): Finish conversion to '$' as - register prefix. - - * mn10300-opc.c (mn10300_opcodes): Fix mask field for - mov am,(imm32,sp). - -Tue Nov 26 10:53:21 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.12. - - Add support for mips16 (16 bit MIPS implementation): - * mips16-opc.c: New file. - * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h". - (mips16_reg_names): New static array. - (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or - after seeing a 16 bit symbol. - (print_insn_little_mips): Likewise. - (print_insn_mips16): New static function. - (print_mips16_insn_arg): New static function. - * mips-opc.c: Add jalx instruction. - * Makefile.in (mips16-opc.o): New target. - * configure.in: Use mips16-opc.o for bfd_mips_arch. - * configure: Rebuild. - -Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Simplify table by using < and > - operand specifiers in *save, *restore and movem* instructions. - - * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for - the coldfire. - - * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use - register operands for immediate arithmetic, not, neg, negx, and - set according to condition instructions. - - * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage - specifier of the effective-address operand in immediate forms of - arithmetic instructions. The specifier for the immediate operand - notes how and where the constant will be stored. - -Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" - opcode. - - * mn10300-dis.c (disassemble): Use '$' instead of '%' for - register prefix. - - * mn10300-dis.c (disassemble): Prefix registers with '%'. - -Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Handle register lists. - - * mn10300-opc.c: Fix handling of register list operand for - "call", "ret", and "rets" instructions. - - * mn10300-dis.c (disassemble): Print PC-relative and memory - addresses symbolically if possible. - * mn10300-opc.c: Distinguish between absolute memory addresses, - pc-relative offsets & random immediates. - - * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte - in 7 byte insns. - (disassemble): Handle SPLIT and EXTENDED operands. - -Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c: Rough cut at printing some operands. - - * mn10300-dis.c: Start working on disassembler support. - * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. - - * mn10300-opc.c (mn10300_operands): Add "REGS" for a register - list. - (mn10300_opcodes): Use REGS for register list in "movm" instructions. - -Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Add3 sets the carry. - -Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Demand parens around - register argument is calls and jmp instructions. - -Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and - getx operand. Fix opcode for mulqu imm,dn. - -Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Hijack "bits" field - in MN10300_OPERAND_SPLIT operands for how many bits - appear in the basic insn word. Add IMM32_HIGH24, - IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. - (mn10300_opcodes): Use new operands as needed. - - * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 - for bset, bclr, btst instructions. - (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. - - * mn10300-opc.c (mn10300_operands): Remove many redundant - operands. Update opcode table as appropriate. - (IMM32): Add MN10300_OPERAND_SPLIT flag. - (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. - -Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 - operands (for indexed load/stores). Fix bitpos for DI - operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the - few instructions that insert immediates/displacements in the - middle of the instruction. Add IMM8E for 8 bit immediate in - the extended part of an instruction. - (mn10300_operands): Use new opcodes as appropriate. - -Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Declare the trap instruction - sequential so the assembler never parallelizes it with - other instructions. - -Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for - a data/address register that appears in register field 0 - and register field 1. - (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN - -Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> - - * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for - standard disassembly. - - * alpha-opc.c (alpha_operands): Rearrange flags slot. - (alpha_opcodes): Add new BWX, CIX, and MAX instructions. - Recategorize PALcode instructions. - -Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Add relaxing "jbr". - -Tue Oct 29 16:30:28 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Don't print a trailing tab if - there are no operand types. - -Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (D9_RELAX): Renamed from D9, all references - changed. - (v850_operands): Make sure D22 immediately follows D9_RELAX. - -Fri Oct 25 12:12:53 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. - -Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w - and sst.w instructions. - - * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for - "bCC"instructions). - -Thu Oct 24 17:21:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Use a tab between the instruction - and the arguments. - -Tue Oct 22 23:32:56 1996 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (PPCPWR2): Define. - (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating - it. - -Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode - field for movhu instruction. - - * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, - cast value to "long" not "signed long" to keep hpux10 - compiler quiet. - -Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field - for mov (abs16),DN. - - * mn10300-opc.c (FMT*): Remove definitions. - - * mn10300-opc.c (mn10300_opcodes): Fix destination register - for shift-by-register opcodes. - - * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM - into [AD][MN][01] for encoding the position of the register - in the opcode. - -Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, - "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". - -Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. - Fix various typos. Add "PAREN" operand. - (MEM, MEM2): Define. - (mn10300_opcodes): Surround all memory addresses with "PAREN" - operands. Fix several typos. - - * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's - changes. - -Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (FMT_XX): Renumber starting at one. - (mn10300_operands): Rough cut. Enough to parse "mov" instructions - at this time. - (mn10300_opcodes): Break opcode format out into its own field. - Update many operand fields to deal with signed vs unsigned - issues. Fix one or two typos in the "mov" instruction - opcode, mask and/or operand fields. - -Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (plusha): Prefer encoding for m68040up, in case - m68851 wasn't reset. - -Thu Oct 3 17:17:02 1996 Ian Lance Taylor <ian@cygnus.com> - - * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for - all opcodes. Very rough cut at operands for all opcodes. - - * mn10300-opc.c (mn10300_opcodes): Start fleshing out the - opcode table. - -Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c, mn10300-opc.c: New files. - * mn10200-dis.c, mn10300-dis.c: New files. - * mn10x00-opc.c, mn10x00-dis.c: Deleted. - * disassemble.c: Break mn10x00 support into 10200 and 10300 - support. - * configure.in: Likewise. - * configure: Rebuilt. - -Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. - -Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita - MN10x00 processors. - * disassemble (ARCH_mn10x00): Define. - (disassembler): Handle bfd_arch_mn10x00. - * configure.in: Recognize bfd_mn10x00_arch. - * configure: Rebuilt. - -Tue Oct 1 10:49:11 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses - accordingly. Don't declare functions using op_rtn. - -Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) - - * v850-dis.c (disassemble): Add memaddr argument. Re-arrange - params to be more standard. - * (disassemble): Print absolute addresses and symbolic names for - branch and jump targets. - * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 - bit operands. - * (v850_opcodes): Add breakpoint insn. - -Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Move the fmovemx data register cases before the - other cases, so that they get recognized before the data register - does gets treated as a degenerate register list. - -Tue Sep 17 12:06:51 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add a case for "div" and "divu" with two registers - and a destination of $0. - -Tue Sep 10 16:12:39 1996 Fred Fish <fnf@rtl.cygnus.com> - - * mips-dis.c (print_insn_arg): Add prototype. - (_print_insn_mips): Ditto. - -Mon Sep 9 14:26:26 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_arg): Print condition code registers as - $fccN. - -Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. - -Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) - - * v850-dis.c (disassemble): Make static. Provide prototype. - -Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (insert_d9, insert_d22): Fix boundary case - in range checks. - -Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) - - * v850-dis.c (disassemble): Handle insertion of ',', '[' and - ']' characters into the output stream. - * v850-opc.c (v850_opcodes: Remove size field from all opcodes. - Add "memop" field to all opcodes (for the disassembler). - Reorder opcodes so that "nop" comes before "mov" and "jr" - comes before "jarl". - - * v850-dis.c (print_insn_v850): Fix typo in last change. - - * v850-dis.c (print_insn_v850): Properly handle disassembling - a two byte insn at the end of a memory region when the memory - region's size is only two byte aligned. - - * v850-dis.c (v850_cc_names): Fix stupid thinkos. - - * v850-dis.c (v850_reg_names): Define. - (v850_sreg_names, v850_cc_names): Likewise. - (disassemble): Very rough cut at printing operands (unformatted). - - * v850-opc.c (BOP_MASK): Fix. - (v850_opcodes): Fix mask for jarl and jr. - - * v850-dis.c: New file. Skeleton for disassembler support. - * Makefile.in Remove v850 references, they're not needed here. - * configure.in: Add v850-dis.o when building v850 toolchains. - * configure: Rebuilt. - * disassemble.c (disassembler): Call v850 disassembler. - - * v850-opc.c (insert_d8_7, extract_d8_7): New functions. - (insert_d8_6, extract_d8_6): New functions. - (v850_operands): Rename D7S to D7; operand for D7 is unsigned. - Rename D8 to D8_7, use {insert,extract}_d8_7 routines. - Add D8_6. - (IF4A, IF4B): Use "D7" instead of "D7S". - (IF4C, IF4D): Use "D8_7" instead of "D8". - (IF4E, IF4F): New. Use "D8_6". - (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for - sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. - - * v850-opc.c (insert_d16_15, extract_d16_15): New functions. - (v850_operands): Change D16 to D16_15, use special insert/extract - routines. New new D16 that uses the generic insert/extract code. - (IF7A, IF7B): Use D16_15. - (IF7C, IF7D): New. Use D16. - (v850_opcodes): Use IF7C and IF7D for ld.b and st.b. - - * v850-opc.c (insert_d9, insert_d22): Slightly improve error - message. Issue an error if the branch offset is odd. - - * v850-opc.c: Add notes about needing special insert/extract - for all the load/store insns, except "ld.b" and "st.b". - - * v850-opc.c (insert_d22, extract_d22): New functions. - (v850_operands): Use insert_d22 and extract_d22 for - D22 operands. - (insert_d9): Fix range check. - -Fri Aug 30 18:01:02 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag - and set bits field to D9 and D22 operands. - -Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Define SR2 operand. - (v850_opcodes): "ldsr" uses R1,SR2. - - * v850-opc.c (v850_opcodes): Fix opcode specs for - sld.w, sst.b, sst.h, sst.w, and nop. - -Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Add null opcode to mark the - end of the opcode table. - -Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (pre_defined_registers): Added register pairs, - "r0-r1", "r2-r3", etc. - -Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Make I16 be a signed operand. - Create I16U for an unsigned 16bit mmediate operand. - (v850_opcodes): Use I16U for "ori", "andi" and "xori". - - * v850-opc.c (v850_operands): Define EP operand. - (IF4A, IF4B, IF4C, IF4D): Use EP. - - * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" - with immediate operand, "movhi". Tweak "ldsr". - - * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] - correct. Get sld.[bhw] and sst.[bhw] closer. - - * v850-opc.c (v850_operands): "not" is a two byte insn - - * v850-opc.c (v850_opcodes): Correct bit pattern for setf. - - * v850-opc.c (v850_operands): D16 inserts at offset 16! - - * v850-opc.c (two): Get order of words correct. - - * v850-opc.c (v850_operands): I16 inserts at offset 16! - - * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system - register source and destination operands. - (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". - - * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix - same thinko in "trap" opcode. - - * v850-opc.c (v850_opcodes): Add initializer for size field - on all opcodes. - - * v850-opc.c (v850_operands): D6 -> DS7. References changed. - Add D8 for 8-bit unsigned field in short load/store insns. - (IF4A, IF4D): These both need two registers. - (IF4C, IF4D): Define. Use 8-bit unsigned field. - (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use - IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand - for "ldsr" and "stsr". - * v850-opc.c (v850_operands): 3-bit immediate for bit insns - is unsigned. - - * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and - short store word (sst.w). - -Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850-opc.c (v850_operands): Added insert and extract fields, - pointers to functions that handle unusual operand encodings. - -Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Enable "trap". - - * v850-opc.c (v850_opcodes): Fix order of displacement - and register for "set1", "clr1", "not1", and "tst1". - -Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Add "B3" support. - (v850_opcodes): Fix and enable "set1", "clr1", "not1" - and "tst1". - - * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand. - - * v850-opc.c: Close unterminated comment. - -Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * v850-opc.c (v850_operands): Add flags field. - (v850_opcodes): add move opcodes. - -Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * Makefile.in (ALL_MACHINES): Add v850-opc.o. - * configure: (bfd_v850v_arch) Add new case. - * configure.in: (bfd_v850_arch) Add new case. - * v850-opc.c: New file. - -Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. - -Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c: Add additional information to the opcode - table to help determinine which instructions can be done - in parallel. - -Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-make.sed: Update editing of include pathnames to be - more general. - -Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> - - * arm-opc.h: Added "bx" instruction definition. - -Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> - - * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. - -Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l. - -Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER. - -Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Update for alpha-opc changes. - -Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_i386): Actually return the correct value. - (ONE, OP_ONE): #ifdef out; not used. - -Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions. - Changed subi operand type to treat 0 as 16. - -Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose - <rose@netcom.com>. - -Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> - - * arm-opc.h: (arm_opcodes): Added halfword and sign-extension - memory transfer instructions. Add new format string entries %h and %s. - * arm-dis.c: (print_insn_arm): Provide decoding of the new - formats %h and %s. - -Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. - (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S. - -Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com> - - * alpha-dis.c (print_insn_alpha_osf): Remove. - (print_insn_alpha_vms): Remove. - (print_insn_alpha): Make globally visible. Chose the register - names based on info->flavour. - * disassemble.c: Always return print_insn_alpha for the alpha. - -Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c (dis_long): Handle unknown opcodes. - -Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c: Changes to support signed and unsigned numbers. - All instructions with the same name that have long and short forms - now end in ".l" or ".s". Divs added. - * d10v-dis.c: Changes to support signed and unsigned numbers. - -Tue Jul 23 11:02:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c: Change all functions to use info->print_address_func. - -Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire - move ccr/sr insns more strict so that the disassembler only - selects them when the addressing mode is data register. - -Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - * d10v-opc.c (pre_defined_registers): Declare. - * d10v-dis.c (print_operand): Now uses pre_defined_registers - to pick a better name for the registers. - -Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix - operands for fexpand and fpmerge. From Christian Kuehnke - <Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>. - -Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> - - * alpha-dis.c (print_insn_alpha): No longer the user-visible - print routine. Take new regnames and cpumask arguments. - Kill the environment variable nonsense. - (print_insn_alpha_osf): New function. Do OSF/1 style regnames. - (print_insn_alpha_vms): New function. Do VMS style regnames. - * disassemble.c (disassembler): Test bfd flavour to pick - between OSF and VMS routines. Default to OSF. - -Thu Jul 18 17:19:34 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_SUBST (INSTALL_SHLIB). - * configure: Rebuild. - * Makefile.in (install): Use @INSTALL_SHLIB@. - -Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * configure: (bfd_d10v_arch) Add new case. - * configure.in: (bfd_d10v_arch) Add new case. - * d10v-dis.c: New file. - * d10v-opc.c: New file. - * disassemble.c (disassembler) Add entry for d10v. - -Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating - to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. - -Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) - - * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to - distinguish between variants of the instruction set. - * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to - distinguish between variants of the instruction set. - -Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) - - * i386-dis.c (print_insn_i8086): New routine to disassemble using - the 8086 instruction set. - * i386-dis.c: General cleanups. Make most things static. Add - prototypes. Get rid of static variables aflags and dflags. Pass - them as args (to almost everything). - -Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. - - * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". - - * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two - if the next arg is marked with SRC_IN_DST. Gross. - - * h8300-dis.c (bfd_h8_disassemble): Print "exr" when - we're looking for and find EXR. - - * h8300-dis.c (bfd_h8_disassemble): We don't have a match - if we're looking for KBIT and we don't find it. - - * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits - for L_3 and L_2. - - * h8300-dis.c (bfd_h8_disassemble): Don't set plen for - 3bit immediate operands. - -Tue Jul 9 10:55:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * Released binutils 2.7. - - * alpha-opc.c: Add new case of "mov". From Klaus Kaempf - <kkaempf@progis.ac-net.de>. - -Thu Jul 4 11:42:51 1996 Ian Lance Taylor <ian@cygnus.com> - - * alpha-opc.c: Correct second case of "mov" to use OPRL. - -Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) - - * sparc-dis.c (print_insn_sparclite): New routine to print - sparclite instructions. - -Wed Jul 3 14:21:18 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Add coldfire support. - -Fri Jun 28 15:53:51 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, - #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L - to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. - -Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): - Use autoconf-set values. - (docdir, oldincludedir): Removed. - * configure.in (AC_PREREQ): autoconf 2.5 or higher. - -Fri Jun 21 13:53:36 1996 Richard Henderson <rth@tamu.edu> - - * alpha-opc.c: New file. - * alpha-opc.h: Remove. - * alpha-dis.c: Complete rewrite to use new opcode table. - * configure.in: For bfd_alpha_arch, use alpha-opc.o. - * configure: Rebuild with autoconf 2.10. - * Makefile.in (ALL_MACHINES): Add alpha-opc.o. - (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not - alpha-opc.h. - (alpha-opc.o): New target. - -Wed Jun 19 15:55:12 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-dis.c (print_insn_sparc): Remove unused local variable i. - Set imm_added_to_rs1 even if the source and destination register - are not the same. - - * sparc-opc.c: Add some two operand forms of the wr instruction. - -Tue Jun 18 15:58:27 1996 Jeffrey A. Law <law@rtl.cygnus.com> - - * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument - to just "mode". - - * disassemble.c (disassembler): Handle H8/S. - * h8300-dis.c (print_insn_h8300s): New function for H8/S. - -Tue Jun 18 18:06:50 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Add beq/teq as aliases for be/te. - - * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko - <sergei@msil.sps.mot.com>. - -Tue Jun 18 15:08:54 1996 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: New file. - - * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. - -Mon Jun 10 18:50:38 1996 Ian Lance Taylor <ian@cygnus.com> - - * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, - regardless of plen. - -Tue Jun 4 09:15:53 1996 Doug Evans <dje@canuck.cygnus.com> - - * i386-dis.c (OP_OFF): Call append_prefix. - -Thu May 23 15:18:23 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (instruction encoding macros): Add explicit casts to - unsigned long to silence a warning from the Solaris PowerPC - compiler. - -Thu Apr 25 19:33:32 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions. - -Mon Apr 22 17:12:35 1996 Doug Evans <dje@blues.cygnus.com> - - * sparc-dis.c (X_IMM,X_SIMM): New macros. - (X_IMM13): Delete. - (print_insn_sparc): Merge cases i,I,j together. New cases X,Y. - * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants, - Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt, - cpush, cpusha, cpull sparclet insns. - -Wed Apr 17 14:20:22 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R. - -Thu Apr 11 17:30:02 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Set F_FBR on floating point branch instructions. - Set F_FLOAT on other floating point instructions. - -Mon Apr 8 17:02:48 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and - registers. - (powerpc_opcodes): Add 860/821 specific SPRs. - -Mon Apr 8 14:00:44 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Permit --enable-shared to specify a list of - directories. Set and substitute BFD_PICLIST. - * configure: Rebuild. - * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all - uses. Set to @BFD_PICLIST@. - -Fri Apr 5 17:12:27 1996 Jeffrey A Law (law@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates, - not "abs", which may be needed for the absolute in something - like btst #0,@10:8. Print L_3 immediates separately from other - immediates. Change ABSMOV reference to ABS8MEM. - -Wed Apr 3 10:40:45 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc. - (current_arch_mask): New static global. - (compute_arch_mask): New static function. - (print_insn_sparc): Delete sparc_v9_p. New static local - current_mach. Resort opcode table if current_mach changes. - Generalize "insn not supported" test. - (compare_opcodes): Prefer supported opcodes to nonsupported ones. - Delete test for v9/!v9. - * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. - (v6notlet): Define. - (brfc): Split into CBR and FBR for coprocessor/fp branches. - (brfcx): Renamed to FBRX. - (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard - coprocessor mnemonics are not supported on the sparclet). - (condf): Renamed to CONDF. - (SLCBCC2): Delete F_ALIAS flag. - -Sat Mar 30 21:45:59 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): rd must be 0 for - mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX. - -Fri Mar 29 13:02:40 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (config.status): Depend upon BFD VERSION file, so - that the shared library version number is set correctly. - -Tue Mar 26 15:47:14 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From - Miles Bader <miles@gnu.ai.mit.edu>. - * configure: Rebuild. - -Sat Mar 16 13:04:07 1996 Fred Fish <fnf@cygnus.com> - - * z8kgen.c (internal, gas): Call xmalloc rather than unchecked - malloc. - -Tue Mar 12 12:14:10 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.8. - -Thu Mar 7 15:11:10 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'. - * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'. - -Tue Mar 5 15:51:57 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Don't set SHLIB or SHLINK to an empty string, - since they appear as targets in Makefile.in. - * configure: Rebuild. - -Mon Feb 26 13:03:40 1996 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-make.sed: Edit out shared library support bits. - -Tue Feb 20 20:48:28 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET. - (sparc_opcode_archs): Add MASK_V8 to sparclet entry. - (sparc_opcodes): Add sparclet insns. - (sparclet_cpreg_table): New static local. - (sparc_{encode,decode}_sparclet_cpreg): New functions. - * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs. - -Tue Feb 20 11:02:44 1996 Alan Modra <alan@mullet.Levels.UniSA.Edu.Au> - - * i386-dis.c (index16): New static variable. - (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the - other way around. - (OP_indirE): Return result of OP_E. - (OP_E): Check for 16 bit addressing mode, and disassemble - correctly. Optimised 32 bit case a little. Don't print - "(base,index,scale)" when sib specifies only an offset. - -Mon Feb 19 12:32:17 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set and substitute SHLIB_DEP. - * configure: Rebuild. - * Makefile.in (SHLIB_DEP): New variable. - (LIBIBERTY_LISTS, BFD_LIST): New variables. - (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If - COMMON_SHLIB, add them to piclist with appropriate modifications. - ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB - here: just use piclist. - -Mon Feb 19 02:03:50 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define. - (print_insn_sparc): Rewrite v9/not-v9 tests. - (compare_opcodes): Likewise. - * sparc-opc.c (MASK_<ARCH>): Define. - (v6,v7,v8,sparclite,v9,v9a): Redefine. - (sparclet,v6notv9): Define. - (sparc_opcode_archs): Delete member `conflicts'. Add `supported'. - (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead. - -Thu Feb 15 14:45:05 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_PROG_CC before configure.host. - * configure: Rebuild. - - * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB). - -Wed Feb 14 19:01:27 1996 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (onebyte_has_modrm): New static array. - (twobyte_has_modrm): New static array. - (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed. - -Tue Feb 13 15:15:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not - $(SHLINK). - -Mon Feb 12 16:26:06 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (PPC): Undef, so default defination on Windows NT - doesn't conflict. - -Wed Feb 7 13:59:54 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on - m68010up, not just m68020up | cpu32. - - * Makefile.in (SONAME): New variable. - ($(SHLINK)): Make a link to the transformed name, as well. - (stamp-tshlink): New target. - (install): Skip stamp-tshlink during install. - -Tue Feb 6 12:28:54 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_ARG_PROGRAM. - * configure: Rebuild. - * Makefile.in (program_transform_name): New variable. - (install): Transform library name before installing it. - -Mon Feb 5 16:14:42 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960-dis.c (mem): Add HX dcinva instruction. - - Support for building as a shared library, based on patches from - Alan Modra <alan@spri.levels.unisa.edu.au>: - * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib. - New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC, - SHLIB_CFLAGS, COMMON_SHLIB, SHLINK. - * configure: Rebuild. - * Makefile.in (ALLLIBS): New variable. - (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables. - (COMMON_SHLIB, SHLINK): New variables. - (.c.o): If PICFLAG is set, compile twice, once PIC, once normal. - (STAGESTUFF): Remove variable. - (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB). - (stamp-piclist, piclist): New targets. - ($(SHLIB), $(SHLINK)): New targets. - ($(OFILES)): Depend upon stamp-picdir. - (disassemble.o): Build twice if PICFLAG is set. - (MOSTLYCLEAN): Add pic/*.o. - (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist. - (distclean): Remove pic and stamp-picdir. - (install): Install shared libraries. - (stamp-picdir): New target. - -Fri Feb 2 17:15:25 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support. - Print unknown instruction as "unknown", rather than in hex. - -Tue Jan 30 14:06:08 1996 Ian Lance Taylor <ian@cygnus.com> - - * dis-buf.c: Include "sysdep.h" before "dis-asm.h". - -Thu Jan 25 20:24:07 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting. - -Thu Jan 25 11:56:49 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte - when necessary. From Ulrich Drepper - <drepper@myware.rz.uni-karlsruhe.de>. - -Thu Jan 25 03:39:10 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with - sparc_num_opcodes. Update architecture enum values. - * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. - (sparc_opcode_lookup_arch): New function. - (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. - (sparc_opcodes): Add v9a shutdown insn. - -Mon Jan 22 08:29:59 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Renamed from print_insn. - If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode - architecture. - (print_insn_sparc64): Deleted. - * disassemble.c (disassembler, case bfd_arch_sparc): Always use - print_insn_sparc. - - * sparc-opc.c (architecture_pname): Add v9a. - -Fri Jan 12 14:35:58 1996 David Mosberger-Tang <davidm@AZStarNet.com> - - * alpha-opc.h (alpha_insn_set): VAX floating point opcode was - incorrectly defined as 0x16 when it should be 0x15. - (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits! - (alpha_insn_set): added cvtst and cvttq float ops. Also added - excb (exception barrier) which is defined in the Alpha - Architecture Handbook version 2. - * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for - OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be - disassembled as or, for example. - -Wed Jan 10 12:37:22 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex. - (_print_insn_mips): Change i from int to unsigned int. - -Thu Jan 4 17:21:10 1996 David Edelsohn <edelsohn@mhpcc.edu> - - * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different - from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli. - -Thu Dec 28 13:29:19 1995 John Hassey <hassey@rtp.dg.com> - - * i386-dis.c: Added Pentium Pro instructions. - -Tue Dec 19 22:56:35 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to - being for Power2. - -Fri Dec 15 14:14:15 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * sh-opc.h (sh_nibble_type): Added REG_B. - (sh_arg_type): Added A_REG_B. - (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc - and stc.l opcodes. - * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B. - -Fri Dec 15 16:44:31 1995 Ian Lance Taylor <ian@cygnus.com> - - * disassemble.c (disassembler): Use new bfd_big_endian macro. - -Tue Dec 12 12:22:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (distclean): Remove stamp-h. From Ronald - F. Guilmette <rfg@monkeys.com>. - -Tue Dec 5 13:42:44 1995 Stan Shebs <shebs@andros.cygnus.com> - - From David Mosberger-Tang <davidm@azstarnet.com>: - * alpha-dis.c (print_insn_alpha): fixed decoding of cpys - instruction. - -Mon Dec 4 12:29:05 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. - (sh_table): Added many SH3 opcodes. - * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC. - -Fri Dec 1 07:42:18 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC. - (subco,subco.): Mark this PPC, not PPCCOM. - -Mon Nov 27 13:09:52 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.7. - -Tue Nov 21 18:28:06 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.6. - -Wed Nov 15 19:02:53 1995 Ken Raeburn <raeburn@cygnus.com> - - * configure.in: Sort list of architectures. Accept but do nothing - for alliant, convex, pyramid, romp, and tahoe. - -Wed Nov 8 20:18:59 1995 Ian Lance Taylor <ian@cygnus.com> - - * a29k-dis.c (print_special): Change num to unsigned int. - -Wed Nov 8 20:10:35 1995 Eric Freudenthal <freudenthal@nyu.edu> - - * a29k-dis.c (print_insn): Cast insn24 to unsigned long when - shifting it. - -Tue Nov 7 15:21:06 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_CHECK_PROG to find and cache AR. - * configure: Rebuilt. - -Mon Nov 6 17:39:47 1995 Harry Dolan <dolan@ssd.intel.com> - - * configure.in: Add case for bfd_i860_arch. - * configure: Rebuild. - -Fri Nov 3 12:45:31 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Correct fmoveml operands. - * m68k-dis.c (NEXTSINGLE): Change i to unsigned int. - (NEXTDOUBLE): Likewise. - (print_insn_m68k): Don't match fmoveml if there is more than one - register in the list. - (print_insn_arg): Handle a place of '8' for a type of 'L'. - -Thu Nov 2 23:06:33 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Use #W rather than #w. - * m68k-dis.c (print_insn_arg): Handle new 'W' place. - -Wed Nov 1 13:30:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf, - and likewise for all the dbxx opcodes. - -Mon Oct 30 20:50:40 1995 Fred Fish <fnf@cygnus.com> - - * arc-dis.c: Include elf-bfd.h rather than libelf.h. - -Mon Oct 23 11:11:34 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> - - * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added - the VR4100 specific instructions to the mips_opcodes structure. - -Thu Oct 19 11:05:23 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in, mpw-make.sed: Remove ugly workaround for - ugly Metrowerks bug in CW6, is fixed in CW7. - -Mon Oct 16 12:59:01 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (whole file): Add flags for common/any support. - -Tue Oct 10 11:06:07 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (BISON): Remove macro. - (FLAGS_TO_PASS): Remove BISON. - -Fri Oct 6 16:26:45 1995 Ken Raeburn <raeburn@cygnus.com> - - Mon Sep 25 22:49:32 1995 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Recognize all two-word - instructions that take no args by looking at the match mask. - (print_insn_arg): Always print "%" before register names. - [case 'c']: Use "nc" for the no-cache case, as recognized by gas. - [case '_']: Don't print "@#" before address. - [case 'J']: Use "%s" as format string, not register name. - [case 'B']: Treat place == 'C' like 'l' and 'L'. - -Thu Oct 5 22:16:20 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode - name correctly. - -Tue Oct 3 08:30:20 1995 steve chamberlain <sac@slash.cygnus.com> - - From David Mosberger-Tang <davidm@azstarnet.com> - - * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added. - (alpha_insn_set): added definitions for VAX floating point - instructions (Unix compilers don't generate these, but handcoded - assembly might still use them). - - * alpha-dis.c (print_insn_alpha): added support for disassembling - the miscellaneous instructions in the Alpha instruction set. - -Tue Sep 26 18:47:20 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k, - no longer create sysdep.h, sed ppc-opc.c to work around a - serious Metrowerks C bug. - * mpw-make.in: Remove. - * mpw-make.sed: New file, used by mpw-configure to edit - Makefile.in into an MPW makefile. - -Wed Sep 20 12:55:28 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (maintainer-clean): New synonym for realclean. - -Tue Sep 19 15:28:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Split pmove patterns which use 'P' into patterns - which use '0', '1', and '2' instead. Specify the proper size for - a pmove immediate operand. Correct the pmovefd patterns to be - moves to a register, not from a register. - * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'. - -Thu Sep 14 11:58:22 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Mark all insns that reference - %psr, %wim, %tbr as F_NOTV9. - -Fri Sep 8 01:07:38 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (Makefile): Just rebuild Makefile when running - config.status. - (config.h, stamp-h): New targets. - * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM - earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when - rebuilding config.h. - * configure: Rebuild. - - * mips-opc.c: Change unaligned loads and stores with "t,A" - operands to use "t,A(b)". - -Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c (print_insn_shx): Add F_FR0 support. - -Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate - until 3 instead of until 2. - -Wed Sep 6 21:21:33 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (ALL_CFLAGS): Define. - (.c.o, disassemble.o): Use $(ALL_CFLAGS). - (MOSTLYCLEAN): Add config.log. - (distclean): Don't remove config.log. - * configure.in: Substitute HDEFINES. - * configure: Rebuild. - -Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_arg_type): Add F_FR0. - (sh_table, case fmac): Add F_FR0 as first argument. - -Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_opcode_info): Increase arg array size to 4. - -Tue Sep 5 18:28:10 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c: Remove all references to NO_V9. - -Tue Sep 5 20:03:26 1995 Ian Lance Taylor <ian@cygnus.com> - - * aclocal.m4: Just include ../bfd/aclocal.m4. - * configure: Rebuild. - -Tue Sep 5 16:09:59 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (X_DISP19): Define. - (print_insn, case 'G'): Use it. - (print_insn, case 'L'): Sign extend displacement. - -Mon Sep 4 14:28:46 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Run ../bfd/configure.host before AC_PROG_CC. - Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute - host_makefile_frag or frags. - * aclocal.m4: New file. - * configure: Rebuild. - * Makefile.in (INSTALL): Set to @INSTALL@. - (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@. - (INSTALL_DATA): Set to @INSTALL_DATA@. - (AR): Set to @AR@. - (AR_FLAGS): Set to rc rather than qc. - (CC): Define as @CC@. - (CFLAGS): Set to @CFLAGS@. - (@host_makefile_frag@): Remove. - (config.status): Remove dependency upon @frags@. - - * configure.in: ../bfd/config.bfd now just sets shell variables. - Use them rather than looking through target Makefile fragments. - * configure: Rebuild. - -Thu Aug 31 12:35:32 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (ftrc): Change FPUL_N to FPUL_M. - -Wed Aug 30 13:52:28 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn. - Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic - sparc64 insns. - - * sparc-opc.c (sparc_opcodes): Fix prefetcha insn. - (lookup_{name,value}): New functions. - (prefetch_table): New static local. - (sparc_{encode,decode}_prefetch): New functions. - * sparc-dis.c (print_insn): Handle '*' arg (prefetch function). - -Wed Aug 30 11:11:58 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h: Add blank lines to improve readabililty of sh3e - instructions. - -Wed Aug 30 11:09:38 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c: Correct comment on first line of file. - -Tue Aug 29 15:37:18 1995 Doug Evans <dje@canuck.cygnus.com> - - * disassemble.c (disassembler): Handle bfd_mach_sparc64. - - * sparc-opc.c (asi, membar): New static locals. - (sparc_{encode,decode}_{asi,membar}): New functions. - (sparc_opcodes, membar insn): Fix. - * sparc-dis.c (print_insn): Call sparc_decode_asi. - Support decoding of membar masks. - (X_MEMBAR): Define. - -Sat Aug 26 21:22:48 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl. - -Mon Aug 21 17:33:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis, - and likewise for the other branches. Add bhs as an alias for bcc, - and likewise for the size variants. Add dbhs as an alias for - dbcc. - -Fri Aug 11 13:40:24 1995 Jeff Law (law@snake.cs.utah.edu) - - * sh-opc.h (FP sts instructions): Update to match reality. - -Mon Aug 7 16:12:58 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-dis.c: (fpcr_names): Add % before all register names. - (reg_names): Likewise. - (print_insn_arg): Don't explicitly print % before register names. - Add % before register names in static array names. In case 'r', - print data registers as `@(Dn)', not `Dn@'. When printing a - memory address, don't print @# before it. - (print_indexed): Change base_disp and outer_disp from int to - bfd_vma. Print using MIT syntax, not mutant invalid Motorola - syntax. Sign extend 8 byte displacement correctly. - (print_base): Print using MIT syntax. Print zpc when appropriate. - Change parameter disp from int to bfd_vma. - - * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases - for jsr. - -Mon Aug 7 02:21:40 1995 Jeff Law (law@snake.cs.utah.edu) - - * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, - F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. - * sh-opc.h (sh_arg_type): Add new operand types. - (sh_table): Add new opcodes from SH3E Floating Point ISA. - -Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (distclean): Remove generated file config.h. - -Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (distclean): Remove generated file config.h. - -Wed Aug 2 18:33:40 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: New file, holding tables from include/opcode/m68k.h. - Clean up tables. - * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff. - (opcode): Remove. - (print_insn_m68k): Change d to be const. Use m68k_numopcodes - rather than numopcodes. Use m68k_opcodes rather than removed - opcode function. Don't check F_ALIAS. - (print_insn_arg): Change first parameter to be const char *. - * Makefile.in (ALL_MACHINES): Add m68k-opc.o. - (m68k-opc.o): New target. - * configure.in: Build m68k-opc.o for bfd_m68k_arch. - * configure: Rebuild. - -Wed Aug 2 08:23:38 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (HASH_SIZE, HASH_INSN): Define. - (opcode_bits, opcode_hash_table): New variables. - (opcodes_initialized): Renamed from opcodes_sorted. - (build_hash_table): New function. - (is_delayed_branch): Use hash table. - (print_insn): Renamed from print_insn_sparc, made static. - Build and use hash table. If !sparc64, ignore sparc64 insns, - and vice-versa if sparc64. - (print_insn_sparc, print_insn_sparc64): New functions. - (compare_opcodes): Move sparc64 opcodes to end. - Print commutative insns with constant second. - * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS. - -Tue Aug 1 00:12:49 1995 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c (print_insn_shx): Remove unused local dslot. Use - print_address_func for A_BDISP12 and A_BDISP8. Correct test which - avoids printing a delay slot in a delay slot. - * sh-opc.h (sh_table): Fully bracket last entry. - -Mon Jul 31 12:04:47 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sllx, srax, srlx): Fix disassembly. - -Wed Jul 12 00:59:34 1995 Ken Raeburn <raeburn@kr-pc.cygnus.com> - - * configure.in: Get host_makefile_frag from ${srcdir}. - - * configure.in: Autoconfiscated. Check for string[s].h. Create - config.h from config.in. Don't set up sysdep.h link. - * sysdep.h: New file. - * configure, config.in: New files, generated from configure.in. - * Makefile.in: Updated to be processed autoconf-style. - (distclean): Keep sysdep.h. Remove config.log and config.cache. - (Makefile): Depend on config.status. - (config.status): New rule. - * configure.bat: Update Makefile substitutions. - -Tue Jul 11 14:23:37 1995 Jeff Spiegel <jeffs@lsil.com> - - * mips-opc.c (L1): Define. - (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, - addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, - and wb. - -Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu - if ISA 3 and addu otherwise, replacing or, since some MIPS chips - have multiple add units but only a single logical unit. - - * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3, - shifted by 18, without any insertion or extraction function. - (insert_cr, extract_cr): Remove. - -Wed Jun 21 20:05:39 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before - register names. - -Thu Jun 15 17:23:31 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in: Add sh and i386 configs, remove sparc config. - * sh-opc.h: Add copyright. - -Mon Jun 5 03:30:43 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> - - * Makefile.in (crunch-m68k): Delete extra target accidentally - checked in a while ago. - -Wed May 24 16:22:13 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_table): Add SH3 support. - -Wed May 24 14:16:08 1995 Steve Chamberlain <sac@slash.cygnus.com> - - * sh-opc.h: Added bsrf and braf. - -Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) - - * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete - bogus [ls]fm{ea,fd} patterns. - - * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc. - * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and - initialize it from memory. Make function static. - (print_insn_{big,little}_arm): New functions. - * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for - the correct endianness. - -Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com> - - * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from - enum list. - -Wed Apr 19 14:07:03 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * m68k-dis.c (opcode): Finish change made by Kung Hsu on April - 17th, so that it builds again using GCC as the compiler. - -Tue Apr 18 12:14:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * mips-dis.c (print_insn_little_mips): Cast return value from - bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips - expects an unsigned long, and that might be fewer words of - argument storage (e.g., if bfd_vma is long long on a 32-bit - machine). - (print_insn_big_mips): Likewise with bfd_getb32 value. - (_print_insn_mips): Now static. - -Mon Apr 17 12:23:28 1995 Kung Hsu <kung@rtl.cygnus.com> - - * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because - gcc memory hog problem with initializer is fixed. - -Mon Apr 10 15:55:01 1995 Stan Shebs <shebs@andros.cygnus.com> - - Merge in support for Mac MPW as a host. - (Old change descriptions retained for informational value.) - - * mpw-config.in (archname): Compute from the config. - (BFD_MACHINES, ARCHDEFS): Put into mk.tmp. - - * mpw-config.in (target_arch): Compute from canonical target. - (m68k, mips, powerpc, sparc): Add architectures. - * mpw-make.in (disassemble.c.o): Add. - (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). - - * mpw-config.in (BFD_MACHINES): Set to a default value. - * mpw-make.in (BFD_MACHINES): Remove wired-in value. - - * mpw-make.in (CSEARCH): Add extra-include to search path. - - * mpw-config.in (varargs.h): Don't create. - (sysdep.h): Create using forward-include. - * mpw-make.in (CSEARCH): Add include/mpw to search path. - - * mpw-config.in: New file, MPW version of configure.in. - * mpw-make.in: New file, MPW version of Makefile.in. - -Fri Mar 31 14:23:38 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * alpha-dis.c (print_insn_alpha): Put empty statement after - default label. - -Tue Mar 21 10:51:40 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version. - (low_sign_extend): Likewise. - (get_field): Delete unused function. - (set_field, deposit_14, deposit_21): Likewise. - -Fri Mar 17 15:55:53 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386-dis.c: Support for more pentium opcodes. From Guy Harris - (guy@netapp.com). - -Tue Mar 14 00:52:57 1995 Ken Raeburn (raeburn@kr-pc.cygnus.com) - - Sat Feb 11 17:22:41 1995 Klaus Kaempf (kkaempf@didymus.rmi.de) - - * alpha-opc.h (OSF_ASMCODE): define - print pal-code names as defined in App C of the - Alpha Architecture Reference Manual - - * alpha-dis.c: cleaned up output - print stylized code forms as defined in App A.4.3 of the - Alpha Architecture Reference Manual - -Wed Mar 8 15:21:14 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for - `rfe'. - * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R', - 'N', and 'M'. - -Wed Mar 8 02:54:05 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k-dis.c (opcode): New function. Returns address of opcode - table entry given index, even if the opcode table was split to - work around gcc bugs. - (print_insn_m68k): Call opcode instead of referencing m68k_opcodes - directly. - (BREAK_UP_BIG_DECL): Make secondary array static and const. - (reg_names): Now const. - (print_insn_arg): Arrays cacheFieldName and names now const. - (print_indexed): Array scales now const. - -Tue Mar 7 16:41:21 1995 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Sort recently added instructions by minor opcode - number within major opcode number. - -Mon Mar 6 10:04:36 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c: Include libhppa.h. - -Fri Feb 24 19:15:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Change dli to use M_DLI, and add dla. - -Mon Feb 20 23:54:38 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * Makefile.in (ALL_MACHINES): Add w65-dis.o. - -Thu Feb 16 17:34:41 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add r4650 mul instruction. - -Wed Feb 15 15:45:20 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add uld and usd macros for unaligned double load and - store. - -Tue Feb 14 13:17:37 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci, - mfdcr, mtdcr, icbt, iccci. - -Thu Feb 9 12:28:13 1995 Stan Shebs <shebs@andros.cygnus.com> - - * i960-dis.c (struct tabent, struct sparse_tabent): Change the - signed char fields to shorts, more portable. - -Wed Feb 8 17:29:29 1995 Stan Shebs <shebs@andros.cygnus.com> - - * i960-dis.c (struct tabent, struct sparse_tabent): Declare the - char fields as signed chars, since they may have negative values. - -Mon Feb 6 10:52:06 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum - (mycroft@netbsd.org). - -Mon Jan 30 12:38:00 1995 Ian Lance Taylor <ian@cygnus.com> - - From "Logg, Ed" <elogg@ea.com>: - * ppc-opc.c (extract_bdm): Correct parenthezisation. - * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized - value. - -Thu Jan 26 18:32:08 1995 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Changes based on patch from David Edelsohn - <edelsohn@mhpcc.edu>. - (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of - SPR. - (FXM_MASK): Define. - (insert_tbr): New static function. - (extract_tbr): New static function. - (XFXFXM_MASK, XFXM): Define. - (XSPRBAT_MASK, XSPRG_MASK): Define. - (powerpc_opcodes): Add instructions to access special registers by - name. Add mtcr and mftbu. - -Tue Jan 17 10:56:43 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c (P3): Define. - (mips_opcodes): Add mad and madu. - -Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat> - - * configure.in: Add W65 support. - * disassemble.c: Likewise. - * w65-opc.h, w65-dis.c: New files. - -Wed Dec 28 22:15:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit - immediates. - -Tue Dec 20 11:25:12 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c: Add dli as a synonym for li. - -Thu Dec 8 18:23:31 1994 Ken Raeburn <raeburn@cujo.cygnus.com> - - * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and - print something for reserved opcode values, even if it won't - assemble again. - - * mips-dis.c (_print_insn_mips): When initializing, shift right - and mask, to avoid sign extension problems on the Alpha. - - * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr - control registers. - -Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * sh-opc.h (mov.l gbr): Get direction right. - * sh-dis.c (print_insn_shx): New function. - (print_insn_shl, print_insn_sh): Call print_insn_shx to - print opcodes with right byte order. - -Thu Nov 3 19:32:22 1994 Ken Raeburn <raeburn@cujo.cygnus.com> - - * ns32k-dis.c (struct ns32k_option): Renamed from struct option, - to avoid conflicts with getopt. - -Mon Oct 31 18:48:10 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * hppa-dis.c (print_insn_hppa): Read the instruction using - bfd_getb32, so that it works on a little endian or 64 bit host. - Remove unused local variable op. - -Tue Oct 25 17:07:57 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c: Use or instead of addu for pseudo-op move, since - addu does not work correctly if -mips3. - -Wed Oct 19 13:40:16 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * a29k-dis.c (print_special): Add special register names defined - on 29030, 29040 and 29050. - (print_insn): Handle new operand type 'I'. - -Wed Oct 12 11:59:55 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * Makefile.in (INSTALL): Use top level install.sh script. - -Wed Oct 5 19:16:29 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * sparc-dis.c: Rewrite to use bitfields, rather than a union, so - that it works on a little endian host. - -Tue Oct 4 12:14:21 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * configure.in: Use ${config_shell} when running config.bfd. - -Wed Sep 21 18:49:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3. - -Thu Sep 15 16:30:22 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * a29k-dis.c (print_insn): Print the opcode. - -Wed Sep 14 17:52:14 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. - -Sun Sep 11 22:32:17 1994 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3. - -Tue Sep 6 11:37:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions - which store a value into memory. - -Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) - - * configure.in, Makefile.in, disassemble.c: Add support for the ARM. - * arm-dis.c, arm-opc.h: New files. - -Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com) - - * Makefile.in (ns32k-dis.o): Add dependency. - * ns32k-dis.c (print_insn_arg): Declare initialized local as - string, not as array of chars. - -Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'. - - * sparc-opc.c: Added sparclite extended FP operations, and - versions of v9 impdep* instructions permitting specification of - the OPF field. - -Tue Jul 26 16:36:03 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i960-dis.c (reg_names): Now const. - (struct sparse_tabent): New type, copied from array type in mem - function. - (ctrl): Local static array ctrl_tab now const. - (cobr): Local static array cobr_tab now const. - (mem): Local variables reg1, reg2, reg3 now point to const. Local - static variable mem_tab no longer explicitly initialized. Changed - mem_init to const array of struct sparse_tabent. - (reg): Local static variable reg_tab no longer explicitly - initialized. Changed reg_init to const array of struct - sparse_tabent. - (ea): Local static array scale_tab now const. - - * i960-dis.c (reg): Added i960JX instructions to reg_init table. - (REG_MAX): Updated. - -Tue Jul 19 21:00:00 1994 DJ Delorie (dj@ctron.com) - - * configure.bat: the disassember needs to be enabled for - "objdump -d" to work in djgpp. - -Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * ns32k-dis.c: Deleted all code in "#ifdef GDB". - (invalid_float): Enabled general version, doesn't require running - on ns32k host. Changed to take char* argument, and test for - explicitly specified sizes, instead of using sizeof() on host CPU - types. - (INVALID_FLOAT): Cast first argument. - (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532, - list_P032, list_M032): Now const. - (optlist, list_search): Made appropriate arguments now point to - const. - (print_insn_arg): Changed static array of one-character-string - pointers into a static const array of characters; fixed sprintf - statement accordingly. - -Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) - - * opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped - from distribution. A ns32k-dis.c from a previous distribution has - been brought up to date and supports the new interface. - - * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k. - - * configure.in: add bfd_ns32k_arch target support. - - * Makefile.in: add ns32k-dis.o to ALL_MACHINES. - Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o. - -Wed Jun 29 22:10:37 1994 Steve Chamberlain (sac@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch - disassembly right. - -Tue Jun 28 13:22:06 1994 Stan Shebs (shebs@andros.cygnus.com) - - * h8300-dis.c, mips-dis.c: Don't use true and false. - -Thu Jun 23 12:53:19 1994 David J. Mackenzie (djm@rtl.cygnus.com) - - * configure.in: Change --with-targets to --enable-targets. - -Wed Jun 22 13:38:32 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-dis.c (_print_insn_mips): Build a static hash table mapping - opcodes to the first instruction with that opcode, to speed - disassembly of large files. From ralphc@pyramid.com (Ralph - Campbell). - -Tue Jun 7 12:49:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * Makefile.in (mostlyclean): Fix typo (was mostyclean). - -Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) - - * configure.bat: update to latest makefile.in - -Sat May 7 17:13:21 1994 Steve Chamberlain (sac@cygnus.com) - - * a29k-dis.c (print_insn): Print 'x' type operand in hex. - * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly. - * sh-dis.c (print_insn_sh): Don't recur endlessly if delay - slot insn is in a delay slot. - * z8k-opc.h: (resflg): Fix patterns. - * h8500-opc.h Fix CR insn patterns. - -Fri May 6 14:34:46 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and - "cmpl" before POWER versions, so that gas -many uses them. - -Thu Apr 28 18:32:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * disassemble.c: New file. - * Makefile.in (OFILES): Add disassemble.o. - (disassemble.o): Provide dependencies; compile with $(ARCHDEFS). - * configure.in: Define ARCHDEFS in Makefile. Code taken from - binutils/configure.in. - - * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the - opcode being examined. - -Thu Apr 21 17:08:40 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS. - (insert_ral, insert_ram, insert_ras): New functions. - (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and - RAS for store with update. - -Sat Apr 16 23:41:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn - (edelsohn@npac.syr.edu). - -Wed Apr 6 17:11:45 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c (mips_opcodes): Correct operands of "nor" with an - immediate argument. - -Mon Apr 4 16:30:46 1994 Doug Evans (dje@canuck.cygnus.com) - - * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0". - -Mon Apr 4 13:22:00 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): The signedp field has been - removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag - instead. Add new operand SISIGNOPT. - (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT. - Based on patch from David Edelsohn (edelsohn@npac.syr.edu). - * ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather - than signedp field. - -Wed Mar 30 00:31:49 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * i386-dis.c (struct private): Renamed to dis_private. `private' - is a reserved word for dynix cc. - -Mon Mar 28 13:00:15 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in: Change error message to refer to bfd/config.bfd - rather than bfd/configure.in. - -Mon Mar 28 12:28:30 1994 David Edelsohn (edelsohn@npac.syr.edu) - - * ppc-opc.c: Define POWER2 as short alias flag. - (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and - fsqrt. - -Wed Mar 23 12:23:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960-dis.c (print_insn_i960): Don't read a second word for - opcodes 0, 1, 2 and 3. - -Wed Mar 16 15:37:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in: Don't build m68881-ext.o for bfd_m68k_arch. - -Mon Mar 14 14:53:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68881-ext.c: Removed; no longer used. - * Makefile.in: Changed accordingly. - - * m68k-dis.c (ext_format_68881): Don't declare. - (print_insn_m68k): If an instruction uses place 'i', it uses at - least four fixed bytes. - (print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For - extended float, convert to double using floatformat_to_double, not - ieee_extended_to_double, and fetch the data before converting it. - -Tue Mar 8 18:12:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: It's sqrt.s, not sqrt.w. From - davidj@ICSI.Berkeley.EDU (David Johnson). - -Tue Feb 8 16:55:27 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the - PowerPC uses bdnz[l][a]. - -Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * dis-buf.c, i386-dis.c: Include sysdep.h. - -Mon Feb 7 19:22:23 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o. - - * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported - by Motorola PowerPC 601 with PPC_OPCODE_601. - * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): - Disassemble Motorola PowerPC 601 instructions as well as normal - PowerPC instructions. - -Sun Feb 6 07:45:17 1994 Jim Kingdon (kingdon@lioth.cygnus.com) - - * i960-dis.c (reg, mem): Just use a static array instead of - calling xmalloc. - -Sat Feb 5 00:04:02 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the - condition name index if this is for a negated condition. - - * hppa-dis.c (print_insn_hppa): No space before 'H' operand. - Floating point format for 'H' operand is backwards from normal - case (0 == double, 1 == single). For '4', '6', '7', '9', and '8' - operands (fmpyadd and fmpysub), handle bizarre register - translation correctly for single precision format. - - * hppa-dis.c (print_insn_hppa): Do not emit a space after 'F' - or 'I' operands if the next format specifier is 'M' (fcmp - condition completer). - -Feb 4 23:38:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): New operand type MBE to handle a - single number giving a bitmask for the MB and ME fields of an M - form instruction. Change NB to accept 32, and turn it into 0; - also turn 0 into 32 when disassembling. Seperated SH from NB. - (insert_mbe, extract_mbe): New functions. - (insert_nb, extract_nb): New functions. - (SC_MASK): Mask out SA and LK bits. - (powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT, - RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark - "bctr" and "bctrl" as accepted by POWER. Change "rlwimi", - "rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.", - "rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to - use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions. - (powerpc_macros): Define table of macro definitions. - (powerpc_num_macros): Define. - - * ppc-dis.c (print_insn_powerpc): Don't skip optional operands - if PPC_OPERAND_NEXT is set. - -Sat Jan 22 23:10:07 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of - char. Retrieve contents using bfd_getl32 instead of shifting. - -Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c: New file. Opcode table for PowerPC, including - opcodes for POWER (RS/6000). - * ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler. - * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o. - (CFILES): Add ppc-dis.c. - (ppc-dis.o, ppc-opc.o): New targets. - * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch. - -Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. - No space before 'u', 'f', or 'N'. - -Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) - - * i386-dis.c (print_insn_i386): Add FIXME comment regarding reading - farther than we should. - - * i386-dis.c (dis386): Use Yb and Yv for scasb and scasS. - -Thu Jan 6 12:38:05 1994 David J. Mackenzie (djm@thepub.cygnus.com) - - * sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments. - -Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) - - * i960-dis.c (print_insn_i960): Only read word2 if the instruction - needs it, to prevent reading past the end of a section. - -Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.h: Use macro for j instruction, to support SVR4 PIC. - Removed t,A case for la; always use t,A(b) case. - -Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - From Ted Lemen <mellon@pepper.ncd.com> - * mips-dis.c (print_insn_arg): Handle 'k'. - * mips-opc.c: Make cache use k, not t. - -Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add - FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct - FLOAT_FORMAT_CODE to put out floating point register names. - -Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Use macros for jal variants, to support SVR4 PIC. - -Thu Oct 28 17:42:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x. - -Wed Oct 27 11:48:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts - larger than 32. Moved dsxx32 variants first for disassembler. - -Mon Oct 25 11:33:14 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * z8kgen.c, z8k-opc.h: Add full lda information. - -Tue Oct 19 12:39:25 1993 Jeffrey A Law (law@cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Do not emit a space after - movb instructions. Any necessary space will be emitted by - the code to handle nullification completers. - -Wed Oct 13 16:19:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Moved l.d down so that it disassembles as ldc1. - -Fri Oct 8 02:34:21 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-opc.h: Add ldl_l, fix typo for ldq_u. - * alpha-dis.c (print_insn_alpha): Add code for PAL_FORMAT_CODE. - -Tue Oct 5 17:47:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Correct lwu opcode value (book had it wrong). - -Thu Sep 30 11:26:18 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * z8k-dis.c (FETCH_DATA): get just the right amount of data. - (unpack_instr): Cope with ARG_IMM4M1 type instructions. - -Wed Sep 29 16:24:49 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k-dis.c (m88kdis): comment change. Remove space after - printing mnemonic. - (printop): handle new arg types DEC and XREG for m88110. - -Tue Sep 28 19:20:16 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Handle 'z' operand - type for absolute branch addresses. Delete special - "ble" and "be" code in 'W' operand code. - -Fri Sep 24 14:08:33 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Set hazard information correctly for branch - likely instructions. - -Fri Sep 17 04:41:17 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use - info->fprintf_func for printing and info->print_address_func for - address output. - -Wed Sep 15 12:12:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Set INSN_TRAP for tXX instructions. - -Thu Sep 9 10:11:27 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): - Corrected second case of "b" for disassembler. - -Tue Sep 7 14:25:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-dis.c, m88k-dis.c: Don't include libbfd.h. Changed calls - to BFD swapping routines to correspond to BFD name changes. - -Thu Sep 2 10:35:25 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Change div machine instruction to be z,s,t rather - than s,t. Change div macro to be d,v,t rather than d,s,t. - Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu, - rem and remu which generates only the corresponding div - instruction. This is for compatibility with the MIPS assembler, - which only generates the simple machine instruction when an - explicit destination of $0 is used. - * mips-dis.c (print_insn_arg): Handle 'z' (always register zero). - -Thu Aug 26 17:41:44 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set - WR_31 hazard for bal, bgezal, bltzal. - -Thu Aug 26 17:20:02 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Use print function - from within the disassemble_info, not fprintf_filtered. - -Wed Aug 25 13:51:40 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Handle '|' like '>'. (From Jeff - Law, law@cs.utah.edu.) - -Mon Aug 23 12:44:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c ("absu"): Removed. - ("dabs"): Added. - -Fri Aug 20 10:52:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Added r6000 and r4000 instructions and macros. - Changed hazard information to distinguish between memory load - delays and coprocessor load delays. - -Wed Aug 18 15:39:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. - -Tue Aug 17 09:44:42 1993 David J. Mackenzie (djm@thepub.cygnus.com) - - * configure.in: Don't pass cpu to config.bfd. - -Tue Aug 17 12:23:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k-dis.c (m88kdis): Make class unsigned. - -Thu Aug 12 15:08:18 1993 Ian Lance Taylor (ian@cygnus.com) - - * alpha-dis.c (print_insn_alpha): One branch format case was - missing the instruction name. - -Wed Aug 11 19:29:39 1993 David J. Mackenzie (djm@thepub.cygnus.com) - - * Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS. - Add the arch-specific auxiliary files. - (OFILES): Remove the arch-specific auxiliary files - and use BFD_MACHINES instead of DIS_LIBS. - * configure.in: Set BFD_MACHINES based on --with-targets option. - -Thu Aug 12 12:04:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly - for swc1. - -Sun Aug 8 15:09:30 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc-opc.c: Change CONST to const to deal with gcc - -Dconst=__const -traditional. - -Fri Aug 6 10:58:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took - coprocessor instructions out of #if 0, and made them use new - argument type "C". - -Thu Aug 5 17:11:06 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc-dis.c: Include ansidecl.h before opcodes/sparc.h. - -Fri Jul 30 18:48:15 1993 John Gilmore (gnu@cygnus.com) - - * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch - instruction, for use by the disassembler. - - * sparc-dis.c (SEX): Add sign extension macro. Replace many - hand-coded sign extensions that depended on 32-bit host ints. - FIXME, we still depend on big-endian host bitfield ordering. - (sparc_print_insn): Set the insn_info_valid field, and the - other fields that describe the instruction being printed. - -Tue Jul 27 17:04:58 1993 Jim Wilson (wilson@sphagnum.cygnus.com) - - * sparc-opc.c (call): Accept all 6 addressing modes valid for - `jmp' instead of just one of them. - -Wed Jul 21 11:43:32 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. - (fput_fp_reg_r): Renamed from fput_reg_r. - (fput_fp_reg): New function. - (print_insn_hppa): Use fput_fp_reg{,_r} where appropriate. - - * hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards. - - * hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD. - -Mon Jul 19 13:52:21 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'. - - * hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n', - don't output a space. - - * hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad. - -Sun Jul 18 16:30:02 1993 Jim Kingdon (kingdon@rtl.cygnus.com) - - * mips-opc.c: New file, containing opcode table from - ../include/opcode/mips.h. - * Makefile.in: Add it. - -Thu Jul 15 12:37:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k-dis.c: New file, moved in from gdb and changed to use the - new dis-asm.h disassembler interface. - * Makefile.in (DIS_LIBS): Added m88k-dis.o. - (m88k-dis.o): New target. - -Tue Jul 13 10:04:16 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to - argument string const char * to correspond to opcode/mips.h. - -Tue Jul 6 15:18:37 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips-dis.c: Updated to account for name changes in new version - of opcode/mips.h. - * Makefile.in: Added header file dependencies. - -Sat Jul 3 23:47:56 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction. - -Thu Jul 1 12:23:38 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign - extend, rather than shifts. - -Sun Jun 20 20:56:56 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) - - * Makefile.in: Undo 15 June change. - -Fri Jun 18 14:15:15 1993 Per Bothner (bothner@deneb.cygnus.com) - - * m68k-dis.c (print_insn_arg): Change return value to byte count - or error code. - * m68k-dis.c: Re-write to detect invalid operands before - printing anything, so we can handle this the same way we - handle invalid opcodes. - -Thu Jun 17 15:01:36 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * sh-dis.c, sh-opc.h: Understand some more opcodes. - -Wed Jun 16 13:48:05 1993 Ian Lance Taylor (ian@cygnus.com) - - * hppa-dis.c: Include <ansidecl.h> and sysdep.h before other - header files. - -Tue Jun 15 21:45:26 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * sparc-dis.c: Don't declare qsort, since sysdep.h might. - - * configure.in: Do make sysdep.h link. - * Makefile.in: Search ../include. Don't search ../bfd. - -Tue Jun 15 13:36:10 1993 Stu Grossman (grossman@cygnus.com) - - Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c: Fix typo. 'a' and 'd' were reversed. - Do not print a space before the completers specified by - 'a' and 'd'. - -Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) - - * mips-dis.c: No longer need to bomb out if HOST_64_BIT is - defined, since gdb has been fixed. - - Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, - fput_reg_r, fput_creg, fput_const, and fputs_filtered should - be a *disassemble_info, not a *FILE. - * hppa-dis.c: Support 'd', '!', and 'a'. - * hppa-dis.c: Support 's' to extract a 2 bit space register. - * hppa-dis.c: Delete cases which are no longer needed. - -Fri Jun 11 07:53:48 1993 Jim Kingdon (kingdon@cygnus.com) - - * m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes. - -Tue Jun 8 12:25:01 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with - H8/300-H opcodes. - -Mon Jun 7 12:58:49 1993 Per Bothner (bothner@rtl.cygnus.com) - - * Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h. - * configure.in: No longer need to configure to get sysdep.h. - -Thu Jun 3 15:56:49 1993 Stu Grossman (grossman@cygnus.com) - - * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa-dis.c: Support 'I', 'J', and 'K' in output - templates for 1.1 FP computational instructions. - -Tue May 25 13:05:48 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * h8500-dis.c (print_insn_h8500): Address argument is type - bfd_vma. - * z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002): - Ditto. - - * h8500-opc.h (addr_class_type): No comma at end of enumerator. - * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto. - - * sparc-dis.c (compare_opcodes): Move static declaration to - top-level. - -Fri May 21 14:17:37 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp - instruction, remove unimp hack from 'l' argument. - -Wed May 19 15:35:54 1993 Stu Grossman (grossman@cygnus.com) - - * z8k-dis.c (fetch_data): Use unsigned char to make ancient gcc's - happy. - -Fri May 14 15:22:46 1993 Ian Lance Taylor (ian@cygnus.com) - - * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): - * mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor - instructions. - -Fri May 14 00:09:14 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c: Include dis-asm.h before sysdep.h. Changed some - arrays of string pointers to 2-d arrays of chars, to save - space. - -Thu May 6 20:51:17 1993 Fred Fish (fnf@cygnus.com) - - * a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c: - Cast second arg to read_memory_func to "bfd_byte *", as necessary. - -Tue May 4 20:31:10 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c: New file from Utah, adapted to new disassembler - calling interface. - * Makefile.in: Include it. - -Mon Apr 26 18:17:42 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * sh-dis.c, sh-opc.h: New files. - -Fri Apr 23 18:51:22 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * alpha-dis.c, alpha-opc.h: New files. - -Tue Apr 6 12:54:08 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed - value. - -Mon Apr 5 17:37:37 1993 John Gilmore (gnu@cygnus.com) - - * sparc-dis.c: Make "ta" the default trap instruction, "t" the alias. - -Fri Apr 2 07:24:27 1993 Ian Lance Taylor (ian@cygnus.com) - - * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than - const. - -Thu Apr 1 11:20:43 1993 Jim Kingdon (kingdon@cygnus.com) - - * sparc-dis.c: Use fprintf_func a few places where I forgot, - and double percent signs a few places. - - * a29k-dis.c, i960-dis.c: New, merged from gdb and binutils. - - * i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c: - Use info->print_address_func not print_address. - - * dis-buf.c (generic_print_address): New function. - -Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * Makefile.in: Add sparc-dis.c. - sparc-dis.c: New file, merges binutils and gdb versions as follows: - From GDB: - Add `add' instruction to the set that get checked - for a preceding `sethi' in order to print an absolute address. - * (print_insn): Disassembly prefers real instructions. - (is_delayed_branch): Speed up. - * sparc-opcode.h: Add ALIAS bit to aliases. Fix up opcode tables. - Still missing some float ops, and needs testing. - * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by - F_ALIAS. Use printf, not fprintf, when not passing a file - pointer... - (compare_opcodes): Check that identical instructions have - identical opcodes, complain otherwise. - From binutils: - * New 'm' arg. - * Include reg_names. - From neither: - Use dis-asm.h/read_memory_func interface. - -Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com) - - * h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data): - deliberately return non-zero to setjmp from longjmp. Otherwise - this code fails to compile. - -Wed Mar 31 17:04:31 1993 Stu Grossman (grossman@cygnus.com) - - * m68k-dis.c: Fix prototype for fetch_arg(). - -Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * dis-buf.c: New file, for new read_memory_func interface. - Makefile.in (OFILES): Include it. - m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c: - Use new read_memory_func interface. - -Mon Mar 29 14:02:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8500-dis.c (print_insn_h8500): Get sign of fp offsets right. - * h8500-opc.h: Fix couple of opcodes. - -Wed Mar 24 02:03:36 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) - - * Makefile.in: add dvi & installcheck targets - -Mon Mar 22 18:55:04 1993 John Gilmore (gnu@cygnus.com) - - * Makefile.in: Update for h8500-dis.c. - -Fri Mar 19 14:27:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8500-dis.c, h8500-opc.h: New files - -Thu Mar 18 14:12:37 1993 Per Bothner (bothner@rtl.cygnus.com) - - * mips-dis.c, z8k-dis.c: Converted to use interface defined in - ../include/dis-asm.h. - * m68k-dis.c: New file (merge of ../binutils/m68k-pinsn.c - and ../gdb/m68k-pinsn.c). - * i386-dis.c: New file (merge of ../binutils/i386-pinsn.c - and ../gdb/i386-pinsn.c). - * m68881-ext.c: New file. Moved definition of - ext_format ext_format_68881 from ../gdb/m68k-tdep.c. - * Makefile.in: Adjust for new files. - * i386-dis.c: Patches from John Hassey (hassey@dg-rtp.dg.com). - * m68k-dis.c: Recognize '9' placement code, so (say) pflush - can be dis-assembled. - -Wed Feb 17 09:19:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * mips-dis.c (print_insn_arg): Now returns void. - -Mon Jan 11 16:09:16 1993 Fred Fish (fnf@cygnus.com) - - * mips-dis.c (ansidecl.h): Include for benefit of sysdep.h - files that use the macros. - -Thu Jan 7 13:15:17 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-dis.c: New file, from gdb/mips-pinsn.c. - * Makefile.in (DIS_LIBS): Added mips-dis.o. - (CFILES): Added mips-dis.c. - -Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines - * z8kgen.c, z8k-opc.h: fix sizes of some shifts. - -Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com) - - * Makefile.in: Improve *clean rules. - * configure.in: Allow a default host. - -Tue Nov 17 19:53:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) - - * Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep - files include other sysdep files - -Thu Nov 12 16:10:37 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint - -Fri Oct 9 04:56:05 1992 John Gilmore (gnu@cygnus.com) - - * configure.in: For host support, use ../bfd/configure.host - so it stays in sync with the ../bfd/hosts database. - -Thu Oct 1 23:38:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) - - * configure.in: use cpu-vendor-os triple instead of nested cases - -Wed Sep 30 16:09:20 1992 Michael Werner (mtw@cygnus.com) - - * z8k-dis.c (unparse_instr): fix bug where opcode returned was - *always* the wrong one. - -Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8kgen.c: added copyright info - -Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c (unparse_instr): prettier tabs - * z8kgen.c -> z8k-opc.h: bug fixes in tables - -Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) - - * configure.in: Add ncr* configuration. - * z8k-dis.c (struct instr_data_s): Make instr_asmsrc char to make - picayune ANSI compilers happy. - -Sep 20 08:50:55 1992 Fred Fish (fnf@cygnus.com) - - * configure.in (i386): Make i386 and i486 synonymous for now. - * configure.in (i[34]86-*-sysv4): Add my_host definition. - -Fri Sep 18 17:01:23 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * Makefile.in (install): Fix typo. - -Fri Sep 18 02:04:24 1992 John Gilmore (gnu@cygnus.com) - - * Makefile.in (make): Remove obsolete crud. - (sparc-opc.o): Avoid Sun Make VPATH bug. - -Tue Sep 8 17:29:27 1992 K. Richard Pixley (rich@sendai.cygnus.com) - - * Makefile.in: since there are no SUBDIRS, remove rule and - references of subdir_do. - -Tue Sep 8 17:02:58 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * Makefile.in (install): Get the library name right here too. - Don't install bfd.h, since it's unrelated to this library. No - subdirs to recurse into, either. - (CFILES): The source file has a .c suffix, not .o. - - * sparc-opc.c: New file, moved from BFD. - * Makefile.in (OFILES): Build it. - -Thu Sep 3 16:59:20 1992 Michael Werner (mtw@cygnus.com) - - * z8k-dis.c: fixed forward refferences of some declarations. - -Mon Aug 31 16:09:45 1992 Michael Werner (mtw@cygnus.com) - - * Makefile.in: get the name of the library right - -Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c: knows how to disassemble z8k stuff - * z8k-opc.h: new file full of z8000 opcodes - - -Local Variables: -version-control: never -End: diff --git a/contrib/binutils/opcodes/Makefile.am b/contrib/binutils/opcodes/Makefile.am deleted file mode 100644 index 77beb4d61612b..0000000000000 --- a/contrib/binutils/opcodes/Makefile.am +++ /dev/null @@ -1,380 +0,0 @@ -## Process this file with automake to generate Makefile.in - -AUTOMAKE_OPTIONS = cygnus - -SUBDIRS = po - -INCDIR = $(srcdir)/../include -BFDDIR = $(srcdir)/../bfd -MKDEP = gcc -MM - -lib_LTLIBRARIES = libopcodes.la - -# This is where bfd.h lives. -BFD_H = ../bfd/bfd.h - -# Header files. -HFILES = \ - arm-opc.h \ - fr30-desc.h fr30-opc.h \ - h8500-opc.h \ - m32r-desc.h m32r-opc.h \ - mcore-opc.h \ - sh-opc.h \ - sysdep.h \ - w65-opc.h \ - z8k-opc.h - -# C source files that correspond to .o's. -CFILES = \ - a29k-dis.c \ - alpha-dis.c \ - alpha-opc.c \ - arc-dis.c \ - arc-opc.c \ - arm-dis.c \ - avr-dis.c \ - cgen-asm.c \ - cgen-dis.c \ - cgen-opc.c \ - d10v-dis.c \ - d10v-opc.c \ - d30v-dis.c \ - d30v-opc.c \ - dis-buf.c \ - disassemble.c \ - fr30-asm.c \ - fr30-desc.c \ - fr30-dis.c \ - fr30-ibld.c \ - fr30-opc.c \ - h8300-dis.c \ - h8500-dis.c \ - hppa-dis.c \ - i370-dis.c \ - i370-opc.c \ - i386-dis.c \ - i960-dis.c \ - m32r-asm.c \ - m32r-desc.c \ - m32r-dis.c \ - m32r-ibld.c \ - m32r-opc.c \ - m32r-opinst.c \ - m68k-dis.c \ - m68k-opc.c \ - m88k-dis.c \ - mcore-dis.c \ - mips-dis.c \ - mips-opc.c \ - mips16-opc.c \ - m10200-dis.c \ - m10200-opc.c \ - m10300-dis.c \ - m10300-opc.c \ - ns32k-dis.c \ - pj-dis.c \ - pj-opc.c \ - ppc-dis.c \ - ppc-opc.c \ - sh-dis.c \ - sparc-dis.c \ - sparc-opc.c \ - tic30-dis.c \ - tic80-dis.c \ - tic80-opc.c \ - v850-dis.c \ - v850-opc.c \ - vax-dis.c \ - w65-dis.c \ - z8k-dis.c \ - z8kgen.c - -ALL_MACHINES = \ - a29k-dis.lo \ - alpha-dis.lo \ - alpha-opc.lo \ - arc-dis.lo \ - arc-opc.lo \ - arm-dis.lo \ - avr-dis.lo \ - cgen-asm.lo \ - cgen-dis.lo \ - cgen-opc.lo \ - d10v-dis.lo \ - d10v-opc.lo \ - d30v-dis.lo \ - d30v-opc.lo \ - fr30-asm.lo \ - fr30-desc.lo \ - fr30-dis.lo \ - fr30-ibld.lo \ - fr30-opc.lo \ - h8300-dis.lo \ - h8500-dis.lo \ - hppa-dis.lo \ - i386-dis.lo \ - i370-dis.lo \ - i370-opc.lo \ - i960-dis.lo \ - m32r-asm.lo \ - m32r-desc.lo \ - m32r-dis.lo \ - m32r-ibld.lo \ - m32r-opc.lo \ - m32r-opinst.lo \ - m68k-dis.lo \ - m68k-opc.lo \ - m88k-dis.lo \ - m10200-dis.lo \ - m10200-opc.lo \ - m10300-dis.lo \ - m10300-opc.lo \ - mcore-dis.lo \ - mips-dis.lo \ - mips-opc.lo \ - mips16-opc.lo \ - pj-dis.lo \ - pj-opc.lo \ - ppc-dis.lo \ - ppc-opc.lo \ - ns32k-dis.lo \ - sh-dis.lo \ - sparc-dis.lo \ - sparc-opc.lo \ - tic30-dis.lo \ - tic80-dis.lo \ - tic80-opc.lo \ - v850-dis.lo \ - v850-opc.lo \ - vax-dis.lo \ - w65-dis.lo \ - z8k-dis.lo - -OFILES = @BFD_MACHINES@ - -INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl - -disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h - $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c - -libopcodes_la_SOURCES = dis-buf.c disassemble.c -libopcodes_la_DEPENDENCIES = $(OFILES) -libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ -libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ - -# libtool will build .libs/libopcodes.a. We create libopcodes.a in -# the build directory so that we don't have to convert all the -# programs that use libopcodes.a simultaneously. This is a hack which -# should be removed if everything else starts using libtool. FIXME. - -noinst_LIBRARIES = libopcodes.a - -stamp-lib: libopcodes.la - libtooldir=`$(LIBTOOL) --config | sed -n -e 's/^objdir=//p'`; \ - if [ -f $$libtooldir/libopcodes.a ]; then \ - cp $$libtooldir/libopcodes.a libopcodes.tmp; \ - $(SHELL) $(srcdir)/../move-if-change libopcodes.tmp libopcodes.a; \ - else true; fi - touch stamp-lib - -libopcodes.a: stamp-lib ; @true - -POTFILES = $(HFILES) $(CFILES) -po/POTFILES.in: @MAINT@ Makefile - for file in $(POTFILES); do echo $$file; done | sort > tmp \ - && mv tmp $(srcdir)/po/POTFILES.in - -# We should reconfigure whenever bfd/configure.in changes, because -# that's where the version number comes from. -config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in - $(SHELL) ./config.status --recheck - -CLEANFILES = \ - libopcodes.a stamp-lib dep.sed DEP DEP1 DEP2 - - - -# The start marker is written this way to pass through automake unscathed. - - - - -# This dependency stuff is copied from BFD. - -DEP: dep.sed $(CFILES) $(HFILES) config.h - rm -f DEP1 - $(MAKE) MKDEP="$(MKDEP)" DEP1 - sed -f dep.sed < DEP1 > $@ - echo '# IF YOU PUT ANYTHING HERE IT WILL GO AWAY' >> $@ - -DEP1: $(CFILES) - echo '# DO NOT DELETE THIS LINE -- mkdep uses it.' > DEP2 - echo '# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.' >> DEP2 - $(MKDEP) $(INCLUDES) $(CFLAGS) $? >> DEP2 - mv -f DEP2 $@ - -dep.sed: dep-in.sed config.status - sed <$(srcdir)/dep-in.sed >dep.sed \ - -e 's!@BFD_H@!$(BFD_H)!' \ - -e 's!@INCDIR@!$(INCDIR)!' \ - -e 's!@BFDDIR@!$(BFDDIR)!' \ - -e 's!@SRCDIR@!$(srcdir)!' - -dep: DEP - sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < Makefile > tmp-Makefile - cat DEP >> tmp-Makefile - $(srcdir)/../move-if-change tmp-Makefile Makefile - -dep-in: DEP - sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.in > tmp-Makefile.in - cat DEP >> tmp-Makefile.in - $(srcdir)/../move-if-change tmp-Makefile.in $(srcdir)/Makefile.in - -dep-am: DEP - sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.am > tmp-Makefile.am - cat DEP >> tmp-Makefile.am - $(srcdir)/../move-if-change tmp-Makefile.am $(srcdir)/Makefile.am - -.PHONY: dep dep-in dep-am - -# What appears below is generated by a hacked mkdep using gcc -MM. - -# DO NOT DELETE THIS LINE -- mkdep uses it. -# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. -a29k-dis.lo: a29k-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/a29k.h -alpha-dis.lo: alpha-dis.c $(INCDIR)/ansidecl.h sysdep.h \ - config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/alpha.h -alpha-opc.lo: alpha-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/alpha.h \ - $(BFD_H) opintl.h -arc-dis.lo: arc-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ - opintl.h -arc-opc.lo: arc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h \ - opintl.h -arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - 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See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/alpha.h" - -/* OSF register names. */ - -static const char * const osf_regnames[64] = -{ - "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", - "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", - "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", - "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", - "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", - "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", - "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", - "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" -}; - -/* VMS register names. */ - -static const char * const vms_regnames[64] = -{ - "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", - "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", - "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", - "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", - "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", - "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", - "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", - "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" -}; - -/* Disassemble Alpha instructions. */ - -int -print_insn_alpha (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; - const char * const * regnames; - const struct alpha_opcode *opcode, *opcode_end; - const unsigned char *opindex; - unsigned insn, op, isa_mask; - int need_comma; - - /* Initialize the majorop table the first time through */ - if (!opcode_index[0]) - { - opcode = alpha_opcodes; - opcode_end = opcode + alpha_num_opcodes; - - for (op = 0; op < AXP_NOPS; ++op) - { - opcode_index[op] = opcode; - while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) - ++opcode; - } - opcode_index[op] = opcode; - } - - if (info->flavour == bfd_target_evax_flavour) - regnames = vms_regnames; - else - regnames = osf_regnames; - - isa_mask = AXP_OPCODE_NOPAL; - switch (info->mach) - { - case bfd_mach_alpha_ev4: - isa_mask |= AXP_OPCODE_EV4; - break; - case bfd_mach_alpha_ev5: - isa_mask |= AXP_OPCODE_EV5; - break; - case bfd_mach_alpha_ev6: - isa_mask |= AXP_OPCODE_EV6; - break; - } - - /* Read the insn into a host word */ - { - bfd_byte buffer[4]; - int status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getl32 (buffer); - } - - /* Get the major opcode of the instruction. */ - op = AXP_OP (insn); - - /* Find the first match in the opcode table. */ - opcode_end = opcode_index[op+1]; - for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) - { - if ((insn & opcode->mask) != opcode->opcode) - continue; - - if (!(opcode->flags & isa_mask)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - { - int invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - const struct alpha_operand *operand = alpha_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, &invalid); - } - if (invalid) - continue; - } - - /* The instruction is valid. */ - goto found; - } - - /* No instruction found */ - (*info->fprintf_func) (info->stream, ".long %#08x", insn); - - return 4; - -found: - (*info->fprintf_func) (info->stream, "%s", opcode->name); - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "\t"); - - /* Now extract and print the operands. */ - need_comma = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - const struct alpha_operand *operand = alpha_operands + *opindex; - int value; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & AXP_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if (operand->flags & AXP_OPERAND_SIGNED) - { - int signbit = 1 << (operand->bits - 1); - value = (value ^ signbit) - signbit; - } - } - - if (need_comma && - ((operand->flags & (AXP_OPERAND_PARENS|AXP_OPERAND_COMMA)) - != AXP_OPERAND_PARENS)) - { - (*info->fprintf_func) (info->stream, ","); - } - if (operand->flags & AXP_OPERAND_PARENS) - (*info->fprintf_func) (info->stream, "("); - - /* Print the operand as directed by the flags. */ - if (operand->flags & AXP_OPERAND_IR) - (*info->fprintf_func) (info->stream, "%s", regnames[value]); - else if (operand->flags & AXP_OPERAND_FPR) - (*info->fprintf_func) (info->stream, "%s", regnames[value+32]); - else if (operand->flags & AXP_OPERAND_RELATIVE) - (*info->print_address_func) (memaddr + 4 + value, info); - else if (operand->flags & AXP_OPERAND_SIGNED) - (*info->fprintf_func) (info->stream, "%d", value); - else - (*info->fprintf_func) (info->stream, "%#x", value); - - if (operand->flags & AXP_OPERAND_PARENS) - (*info->fprintf_func) (info->stream, ")"); - need_comma = 1; - } - - return 4; -} diff --git a/contrib/binutils/opcodes/alpha-opc.c b/contrib/binutils/opcodes/alpha-opc.c deleted file mode 100644 index 99458916ad3bf..0000000000000 --- a/contrib/binutils/opcodes/alpha-opc.c +++ /dev/null @@ -1,1546 +0,0 @@ -/* alpha-opc.c -- Alpha AXP opcode list - Copyright (c) 1996, 1998, 1999 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@cygnus.com>, - patterned after the PPC opcode handling written by Ian Lance Taylor. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/alpha.h" -#include "bfd.h" -#include "opintl.h" - -/* This file holds the Alpha AXP opcode table. The opcode table includes - almost all of the extended instruction mnemonics. This permits the - disassembler to use them, and simplifies the assembler logic, at the - cost of increasing the table size. The table is strictly constant - data, so the compiler should be able to put it in the .text section. - - This file also holds the operand table. All knowledge about inserting - operands into instructions and vice-versa is kept in this file. - - The information for the base instruction set was compiled from the - _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, - version 2. - - The information for the post-ev5 architecture extensions BWX, CIX and - MAX came from version 3 of this same document, which is also available - on-line at http://ftp.digital.com/pub/Digital/info/semiconductor - /literature/alphahb2.pdf - - The information for the EV4 PALcode instructions was compiled from - _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware - Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary - revision dated June 1994. - - The information for the EV5 PALcode instructions was compiled from - _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital - Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ - -/* Local insertion and extraction functions */ - -static unsigned insert_rba PARAMS((unsigned, int, const char **)); -static unsigned insert_rca PARAMS((unsigned, int, const char **)); -static unsigned insert_za PARAMS((unsigned, int, const char **)); -static unsigned insert_zb PARAMS((unsigned, int, const char **)); -static unsigned insert_zc PARAMS((unsigned, int, const char **)); -static unsigned insert_bdisp PARAMS((unsigned, int, const char **)); -static unsigned insert_jhint PARAMS((unsigned, int, const char **)); -static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **)); - -static int extract_rba PARAMS((unsigned, int *)); -static int extract_rca PARAMS((unsigned, int *)); -static int extract_za PARAMS((unsigned, int *)); -static int extract_zb PARAMS((unsigned, int *)); -static int extract_zc PARAMS((unsigned, int *)); -static int extract_bdisp PARAMS((unsigned, int *)); -static int extract_jhint PARAMS((unsigned, int *)); -static int extract_ev6hwjhint PARAMS((unsigned, int *)); - - -/* The operands table */ - -const struct alpha_operand alpha_operands[] = -{ - /* The fields are bits, shift, insert, extract, flags */ - /* The zero index is used to indicate end-of-list */ -#define UNUSED 0 - { 0, 0, 0, 0, 0, 0 }, - - /* The plain integer register fields */ -#define RA (UNUSED + 1) - { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, -#define RB (RA + 1) - { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, -#define RC (RB + 1) - { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, - - /* The plain fp register fields */ -#define FA (RC + 1) - { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, -#define FB (FA + 1) - { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, -#define FC (FB + 1) - { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, - - /* The integer registers when they are ZERO */ -#define ZA (FC + 1) - { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, -#define ZB (ZA + 1) - { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, -#define ZC (ZB + 1) - { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, - - /* The RB field when it needs parentheses */ -#define PRB (ZC + 1) - { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, - - /* The RB field when it needs parentheses _and_ a preceding comma */ -#define CPRB (PRB + 1) - { 5, 16, 0, - AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, - - /* The RB field when it must be the same as the RA field */ -#define RBA (CPRB + 1) - { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, - - /* The RC field when it must be the same as the RB field */ -#define RCA (RBA + 1) - { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, - - /* The RC field when it can *default* to RA */ -#define DRC1 (RCA + 1) - { 5, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, - - /* The RC field when it can *default* to RB */ -#define DRC2 (DRC1 + 1) - { 5, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, - - /* The FC field when it can *default* to RA */ -#define DFC1 (DRC2 + 1) - { 5, 0, 0, - AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, - - /* The FC field when it can *default* to RB */ -#define DFC2 (DFC1 + 1) - { 5, 0, 0, - AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, - - /* The unsigned 8-bit literal of Operate format insns */ -#define LIT (DFC2 + 1) - { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The signed 16-bit displacement of Memory format insns. From here - we can't tell what relocation should be used, so don't use a default. */ -#define MDISP (LIT + 1) - { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, - - /* The signed "23-bit" aligned displacement of Branch format insns */ -#define BDISP (MDISP + 1) - { 21, 0, BFD_RELOC_23_PCREL_S2, - AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, - - /* The 26-bit PALcode function */ -#define PALFN (BDISP + 1) - { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ -#define JMPHINT (PALFN + 1) - { 14, 0, BFD_RELOC_ALPHA_HINT, - AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, - insert_jhint, extract_jhint }, - - /* The optional hint to RET/JSR_COROUTINE */ -#define RETHINT (JMPHINT + 1) - { 14, 0, -RETHINT, - AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, - - /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */ -#define EV4HWDISP (RETHINT + 1) -#define EV6HWDISP (EV4HWDISP) - { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, - - /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ -#define EV4HWINDEX (EV4HWDISP + 1) - { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns - that occur in DEC PALcode. */ -#define EV4EXTHWINDEX (EV4HWINDEX + 1) - { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ -#define EV5HWDISP (EV4EXTHWINDEX + 1) - { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, - - /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ -#define EV5HWINDEX (EV5HWDISP + 1) - { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 16-bit combined index/scoreboard mask for the ev6 - hw_m[ft]pr (pal19/pal1d) insns */ -#define EV6HWINDEX (EV5HWINDEX + 1) - { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */ -#define EV6HWJMPHINT (EV6HWINDEX+ 1) - { 8, 0, -EV6HWJMPHINT, - AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, - insert_ev6hwjhint, extract_ev6hwjhint } -}; - -const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); - -/* The RB field when it is the same as the RA field in the same insn. - This operand is marked fake. The insertion function just copies - the RA field into the RB field, and the extraction function just - checks that the fields are the same. */ - -/*ARGSUSED*/ -static unsigned -insert_rba(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static int -extract_rba(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - - -/* The same for the RC field */ - -/*ARGSUSED*/ -static unsigned -insert_rca(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((insn >> 21) & 0x1f); -} - -static int -extract_rca(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != (insn & 0x1f)) - *invalid = 1; - return 0; -} - - -/* Fake arguments in which the registers must be set to ZERO */ - -/*ARGSUSED*/ -static unsigned -insert_za(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (31 << 21); -} - -static int -extract_za(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -/*ARGSUSED*/ -static unsigned -insert_zb(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (31 << 16); -} - -static int -extract_zb(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -/*ARGSUSED*/ -static unsigned -insert_zc(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | 31; -} - -static int -extract_zc(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && (insn & 0x1f) != 31) - *invalid = 1; - return 0; -} - - -/* The displacement field of a Branch format insn. */ - -static unsigned -insert_bdisp(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("branch operand unaligned"); - return insn | ((value / 4) & 0x1FFFFF); -} - -/*ARGSUSED*/ -static int -extract_bdisp(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); -} - - -/* The hint field of a JMP/JSR insn. */ - -static unsigned -insert_jhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("jump hint unaligned"); - return insn | ((value / 4) & 0x3FFF); -} - -/*ARGSUSED*/ -static int -extract_jhint(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); -} - -/* The hint field of an EV6 HW_JMP/JSR insn. */ - -static unsigned -insert_ev6hwjhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("jump hint unaligned"); - return insn | ((value / 4) & 0x1FFF); -} - -/*ARGSUSED*/ -static int -extract_ev6hwjhint(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); -} - - -/* Macros used to form opcodes */ - -/* The main opcode */ -#define OP(x) (((x) & 0x3F) << 26) -#define OP_MASK 0xFC000000 - -/* Branch format instructions */ -#define BRA_(oo) OP(oo) -#define BRA_MASK OP_MASK -#define BRA(oo) BRA_(oo), BRA_MASK - -/* Floating point format instructions */ -#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) -#define FP_MASK (OP_MASK | 0xFFE0) -#define FP(oo,fff) FP_(oo,fff), FP_MASK - -/* Memory format instructions */ -#define MEM_(oo) OP(oo) -#define MEM_MASK OP_MASK -#define MEM(oo) MEM_(oo), MEM_MASK - -/* Memory/Func Code format instructions */ -#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) -#define MFC_MASK (OP_MASK | 0xFFFF) -#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK - -/* Memory/Branch format instructions */ -#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) -#define MBR_MASK (OP_MASK | 0xC000) -#define MBR(oo,h) MBR_(oo,h), MBR_MASK - -/* Operate format instructions. The OPRL variant specifies a - literal second argument. */ -#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) -#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) -#define OPR_MASK (OP_MASK | 0x1FE0) -#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK -#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK - -/* Generic PALcode format instructions */ -#define PCD_(oo) OP(oo) -#define PCD_MASK OP_MASK -#define PCD(oo) PCD_(oo), PCD_MASK - -/* Specific PALcode instructions */ -#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) -#define SPCD_MASK 0xFFFFFFFF -#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK - -/* Hardware memory (hw_{ld,st}) instructions */ -#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) -#define EV4HWMEM_MASK (OP_MASK | 0xF000) -#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK - -#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) -#define EV5HWMEM_MASK (OP_MASK | 0xF800) -#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK - -#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) -#define EV6HWMEM_MASK (OP_MASK | 0xF000) -#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK - -#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) -#define EV6HWMBR_MASK (OP_MASK | 0xE000) -#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK - -/* Abbreviations for instruction subsets. */ -#define BASE AXP_OPCODE_BASE -#define EV4 AXP_OPCODE_EV4 -#define EV5 AXP_OPCODE_EV5 -#define EV6 AXP_OPCODE_EV6 -#define BWX AXP_OPCODE_BWX -#define CIX AXP_OPCODE_CIX -#define MAX AXP_OPCODE_MAX - -/* Common combinations of arguments */ -#define ARG_NONE { 0 } -#define ARG_BRA { RA, BDISP } -#define ARG_FBRA { FA, BDISP } -#define ARG_FP { FA, FB, DFC1 } -#define ARG_FPZ1 { ZA, FB, DFC1 } -#define ARG_MEM { RA, MDISP, PRB } -#define ARG_FMEM { FA, MDISP, PRB } -#define ARG_OPR { RA, RB, DRC1 } -#define ARG_OPRL { RA, LIT, DRC1 } -#define ARG_OPRZ1 { ZA, RB, DRC1 } -#define ARG_OPRLZ1 { ZA, LIT, RC } -#define ARG_PCD { PALFN } -#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } -#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } -#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } -#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } - - NAME is the name of the instruction. - - OPCODE is the instruction opcode. - - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - - OPERANDS is the list of operands. - - The preceding macros merge the text of the OPCODE and MASK fields. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. - - Otherwise, it is sorted by major opcode and minor function code. - - There are three classes of not-really-instructions in this table: - - ALIAS is another name for another instruction. Some of - these come from the Architecture Handbook, some - come from the original gas opcode tables. In all - cases, the functionality of the opcode is unchanged. - - PSEUDO a stylized code form endorsed by Chapter A.4 of the - Architecture Handbook. - - EXTRA a stylized code form found in the original gas tables. - - And two annotations: - - EV56 BUT opcodes that are officially introduced as of the ev56, - but with defined results on previous implementations. - - EV56 UNA opcodes that were introduced as of the ev56 with - presumably undefined results on previous implementations - that were not assigned to a particular extension. -*/ - -const struct alpha_opcode alpha_opcodes[] = { - { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, - { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, - { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, - { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, - { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, - { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, - { "call_pal", PCD(0x00), BASE, ARG_PCD }, - { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ - - { "lda", MEM(0x08), BASE, ARG_MEM }, - { "ldah", MEM(0x09), BASE, ARG_MEM }, - { "ldbu", MEM(0x0A), BWX, ARG_MEM }, - { "unop", MEM(0x0B), BASE, { ZA } }, /* pseudo */ - { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, - { "ldwu", MEM(0x0C), BWX, ARG_MEM }, - { "stw", MEM(0x0D), BWX, ARG_MEM }, - { "stb", MEM(0x0E), BWX, ARG_MEM }, - { "stq_u", MEM(0x0F), BASE, ARG_MEM }, - - { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ - { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, - { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, - { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, - { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, - { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, - { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, - { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, - { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, - { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, - { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, - { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, - { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, - { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, - { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, - { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, - { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, - { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, - { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, - { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, - { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, - { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, - { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, - { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, - { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, - { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, - { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, - { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, - { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, - { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, - { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, - { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, - { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, - { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, - { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, - { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, - { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, - { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, - { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, - { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, - { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, - { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, - { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, - { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, - { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, - - { "and", OPR(0x11,0x00), BASE, ARG_OPR }, - { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, - { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ - { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ - { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, - { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, - { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, - { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, - { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, - { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, - { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ - { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ - { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ - { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ - { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ - { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ - { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ - { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, - { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, - { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, - { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, - { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, - { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, - { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ - { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, - { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, - { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, - { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, - { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, - { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, - { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, - { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, - { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, - { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, - { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ - { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ - { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ - { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ - { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, - { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, - { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, - { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, - { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), - 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ - - { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, - { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, - { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, - { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, - { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, - { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, - { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, - { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, - { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, - { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, - { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, - { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, - { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, - { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, - { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, - { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, - { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, - { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, - { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, - { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, - { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, - { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, - { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, - { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, - { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, - { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, - { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, - { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, - { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, - { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, - { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, - { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, - { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, - { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, - { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, - { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, - { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, - { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, - { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, - { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, - { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, - { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, - { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, - { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, - { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, - { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, - { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, - { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, - { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, - { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, - { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, - { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, - - { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, - { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, - { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, - { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, - { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, - { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, - { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, - { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, - { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, - { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, - - { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, - { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, - { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, - { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, - { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, - { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, - { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, - { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, - { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, - { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, - { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, - { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, - { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, - { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, - { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, - { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, - { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, - { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, - { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, - { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, - { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, - { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, - { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, - { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, - { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, - { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, - { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, - { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, - { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, - { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, - { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, - { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, - { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, - { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, - { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, - { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, - { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, - { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, - { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, - { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, - { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, - { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, - { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, - { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, - { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, - { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, - { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, - { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, - { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, - { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, - { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, - - { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, - { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, - { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, - { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, - { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, - { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, - { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, - { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, - { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, - { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, - { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, - { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, - { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, - { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, - { "addf", FP(0x15,0x080), BASE, ARG_FP }, - { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ - { "subf", FP(0x15,0x081), BASE, ARG_FP }, - { "mulf", FP(0x15,0x082), BASE, ARG_FP }, - { "divf", FP(0x15,0x083), BASE, ARG_FP }, - { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, - { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, - { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, - { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, - { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, - { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, - { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, - { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, - { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, - { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, - { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, - { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, - { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, - { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, - { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, - { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, - { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, - { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, - { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, - { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, - { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, - { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, - { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, - { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, - { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, - { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, - { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, - { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, - { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, - { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, - { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, - { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, - { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, - { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, - { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, - { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, - { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, - { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, - { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, - { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, - { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, - { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, - { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, - { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, - { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, - { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, - { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, - { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, - { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, - { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, - { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ - { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, - { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, - { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, - { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, - { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, - { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, - { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, - { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, - { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, - { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, - { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, - { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, - { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, - { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, - { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, - { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, - { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, - { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, - { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, - { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, - { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, - { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, - { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, - { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, - { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, - { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, - { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, - { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, - { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, - { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, - { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, - { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, - { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, - { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, - { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, - { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, - { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, - { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, - - { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, - { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, - { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, - { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, - { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, - { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, - { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, - { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, - { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, - { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, - { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, - { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, - { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, - { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, - { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, - { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, - { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, - { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, - { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, - { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, - { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, - { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, - { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, - { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, - { "adds", FP(0x16,0x080), BASE, ARG_FP }, - { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ - { "subs", FP(0x16,0x081), BASE, ARG_FP }, - { "muls", FP(0x16,0x082), BASE, ARG_FP }, - { "divs", FP(0x16,0x083), BASE, ARG_FP }, - { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, - { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, - { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, - { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, - { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, - { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, - { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, - { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, - { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, - { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, - { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, - { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, - { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, - { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, - { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, - { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, - { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, - { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, - { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, - { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, - { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, - { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, - { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, - { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, - { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, - { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, - { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, - { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, - { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, - { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, - { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, - { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, - { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, - { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, - { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, - { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, - { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, - { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, - { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, - { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, - { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, - { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, - { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, - { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, - { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, - { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, - { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, - { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, - { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, - { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, - { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, - { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, - { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, - { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, - { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, - { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, - { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, - { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, - { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, - { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, - { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, - { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, - { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, - { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, - { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, - { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, - { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, - { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, - { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, - { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, - { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, - { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, - { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, - { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, - { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, - { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, - { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, - { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, - { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, - { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, - { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, - { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, - { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, - { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, - { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, - { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, - { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ - { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, - { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, - { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, - { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, - { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, - { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, - { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, - { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, - { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, - { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, - { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, - { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, - { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, - { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, - { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, - { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, - { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, - { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, - { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, - { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, - { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, - { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, - { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, - { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, - { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, - { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, - { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, - { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, - { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, - { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, - { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, - { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, - { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, - { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, - { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, - { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, - { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, - { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, - { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, - { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, - { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, - { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, - { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, - { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, - { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, - { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, - { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, - { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, - { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, - { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ - { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, - { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, - { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, - { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, - { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, - { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, - { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, - { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, - { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, - { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, - { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, - { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, - { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, - { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, - { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, - { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, - { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, - { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, - { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, - { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, - { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, - { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, - { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, - - { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, - { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ - { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ - { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ - { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ - { "cpys", FP(0x17,0x020), BASE, ARG_FP }, - { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ - { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, - { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, - { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, - { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, - { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, - { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, - { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, - { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, - { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, - { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, - { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, - { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, - { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, - - { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, - { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ - { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, - { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, - { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, - { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, - { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, - { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, - { "rc", MFC(0x18,0xE000), BASE, { RA } }, - { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ - { "rs", MFC(0x18,0xF000), BASE, { RA } }, - { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ - - { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, - { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, - { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, - { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, - { "pal19", PCD(0x19), BASE, ARG_PCD }, - - { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, - { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, - { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, - { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ - { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, - - { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, - { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, - { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, - { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, - { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, - { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, - { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, - { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, - { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, - { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, - { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, - { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, - { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, - { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, - { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, - { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, - { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, - { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, - { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, - { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, - { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, - { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, - { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, - { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, - { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, - { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, - { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, - { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, - { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, - { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, - { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, - { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, - { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, - { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, - { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, - { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, - { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, - { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, - { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, - { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, - { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, - { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, - { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, - { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, - { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, - { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, - { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, - { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, - { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, - { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, - { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, - { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, - { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, - { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, - { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, - { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, - { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, - { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, - { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, - { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, - { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, - { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, - { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, - { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, - { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, - { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, - { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, - { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, - { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, - { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, - { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, - { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, - { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, - { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, - { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, - { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, - { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, - { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, - { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, - { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, - { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, - { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, - { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, - { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, - { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, - { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, - { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, - { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, - { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, - { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, - { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, - { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, - { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, - { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, - { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, - { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, - { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, - { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, - { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, - { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, - { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, - { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, - { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, - { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, - { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, - { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, - { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, - { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, - { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, - { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, - { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, - { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, - { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, - { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, - { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, - { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, - { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, - { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, - { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, - { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, - { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, - { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, - { "pal1b", PCD(0x1B), BASE, ARG_PCD }, - - { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, - { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, - { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, - { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, - { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, - { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, - { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, - { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, - { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, - { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, - { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, - { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, - { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, - { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, - { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, - { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, - { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, - { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, - { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, - { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, - { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, - { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, - { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, - { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, - { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, - { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, - { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, - { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, - - { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, - { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, - { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, - { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, - { "pal1d", PCD(0x1D), BASE, ARG_PCD }, - - { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, - { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, - { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, - { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, - { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ - { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, - { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, - { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ - { "pal1e", PCD(0x1E), BASE, ARG_PCD }, - - { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, - { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, - { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ - { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, - { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, - { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, - { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, - { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, - { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, - { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, - { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, - { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, - { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, - { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, - { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, - { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, - { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, - { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, - { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, - { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, - { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, - { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, - { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, - { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, - { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, - { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, - { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, - { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, - { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, - { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, - { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ - { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, - { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, - { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, - { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, - { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, - { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, - { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, - { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, - { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, - { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, - { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, - { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, - { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, - { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, - { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, - { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, - { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, - { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, - { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, - { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, - { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, - { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, - { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, - { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, - { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, - { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, - { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, - { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, - { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, - { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, - { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, - { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, - { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, - { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, - { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, - { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, - { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, - { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, - { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, - { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, - { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, - { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, - { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, - { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, - { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, - { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, - { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, - { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, - { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, - { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, - { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, - { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, - { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, - { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, - { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, - { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, - { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, - { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, - { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, - { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, - { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, - { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, - { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, - { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, - { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, - { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, - { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, - { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, - { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, - { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, - { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, - { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, - { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, - { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, - { "pal1f", PCD(0x1F), BASE, ARG_PCD }, - - { "ldf", MEM(0x20), BASE, ARG_FMEM }, - { "ldg", MEM(0x21), BASE, ARG_FMEM }, - { "lds", MEM(0x22), BASE, ARG_FMEM }, - { "ldt", MEM(0x23), BASE, ARG_FMEM }, - { "stf", MEM(0x24), BASE, ARG_FMEM }, - { "stg", MEM(0x25), BASE, ARG_FMEM }, - { "sts", MEM(0x26), BASE, ARG_FMEM }, - { "stt", MEM(0x27), BASE, ARG_FMEM }, - - { "ldl", MEM(0x28), BASE, ARG_MEM }, - { "ldq", MEM(0x29), BASE, ARG_MEM }, - { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, - { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, - { "stl", MEM(0x2C), BASE, ARG_MEM }, - { "stq", MEM(0x2D), BASE, ARG_MEM }, - { "stl_c", MEM(0x2E), BASE, ARG_MEM }, - { "stq_c", MEM(0x2F), BASE, ARG_MEM }, - - { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ - { "br", BRA(0x30), BASE, ARG_BRA }, - { "fbeq", BRA(0x31), BASE, ARG_FBRA }, - { "fblt", BRA(0x32), BASE, ARG_FBRA }, - { "fble", BRA(0x33), BASE, ARG_FBRA }, - { "bsr", BRA(0x34), BASE, ARG_BRA }, - { "fbne", BRA(0x35), BASE, ARG_FBRA }, - { "fbge", BRA(0x36), BASE, ARG_FBRA }, - { "fbgt", BRA(0x37), BASE, ARG_FBRA }, - { "blbc", BRA(0x38), BASE, ARG_BRA }, - { "beq", BRA(0x39), BASE, ARG_BRA }, - { "blt", BRA(0x3A), BASE, ARG_BRA }, - { "ble", BRA(0x3B), BASE, ARG_BRA }, - { "blbs", BRA(0x3C), BASE, ARG_BRA }, - { "bne", BRA(0x3D), BASE, ARG_BRA }, - { "bge", BRA(0x3E), BASE, ARG_BRA }, - { "bgt", BRA(0x3F), BASE, ARG_BRA }, -}; - -const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); diff --git a/contrib/binutils/opcodes/arc-dis.c b/contrib/binutils/opcodes/arc-dis.c deleted file mode 100644 index 03f13795275e6..0000000000000 --- a/contrib/binutils/opcodes/arc-dis.c +++ /dev/null @@ -1,268 +0,0 @@ -/* Instruction printing code for the ARC. - Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/arc.h" -#include "elf-bfd.h" -#include "elf/arc.h" -#include "opintl.h" - -static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *)); - -static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int)); - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (4 or 8 for the ARC). */ - -static int -print_insn (pc, info, mach, big_p) - bfd_vma pc; - disassemble_info *info; - int mach; - int big_p; -{ - const struct arc_opcode *opcode; - bfd_byte buffer[4]; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - int status; - /* First element is insn, second element is limm (if present). */ - arc_insn insn[2]; - int got_limm_p = 0; - static int initialized = 0; - static int current_mach = 0; - - if (!initialized || mach != current_mach) - { - initialized = 1; - current_mach = arc_get_opcode_mach (mach, big_p); - arc_opcode_init_tables (current_mach); - } - - status = (*info->read_memory_func) (pc, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - if (big_p) - insn[0] = bfd_getb32 (buffer); - else - insn[0] = bfd_getl32 (buffer); - - (*func) (stream, "%08lx\t", insn[0]); - - /* The instructions are stored in lists hashed by the insn code - (though we needn't care how they're hashed). */ - - opcode = arc_opcode_lookup_dis (insn[0]); - for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_DIS (opcode)) - { - char *syn; - int mods,invalid; - long value; - const struct arc_operand *operand; - const struct arc_operand_value *opval; - - /* Basic bit mask must be correct. */ - if ((insn[0] & opcode->mask) != opcode->value) - continue; - - /* Supported by this cpu? */ - if (! arc_opcode_supported (opcode)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - - arc_opcode_init_extract (); - invalid = 0; - - /* ??? Granted, this is slower than the `ppc' way. Maybe when this is - done it'll be clear what the right way to do this is. */ - /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets - printed first, but we don't know how to print it until we've processed - the regs. Since we're scanning all the args before printing the insn - anyways, it's actually quite easy. */ - - for (syn = opcode->syntax; *syn; ++syn) - { - int c; - - if (*syn != '%' || *++syn == '%') - continue; - mods = 0; - c = *syn; - while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags)) - { - mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS; - ++syn; - c = *syn; - } - operand = arc_operands + arc_operand_map[c]; - if (operand->extract) - (*operand->extract) (insn, operand, mods, - (const struct arc_operand_value **) NULL, - &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - - /* If we have an insn with a limm, fetch it now. Scanning the insns - twice lets us do this. */ - if (arc_opcode_limm_p (NULL)) - { - status = (*info->read_memory_func) (pc + 4, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - if (big_p) - insn[1] = bfd_getb32 (buffer); - else - insn[1] = bfd_getl32 (buffer); - got_limm_p = 1; - } - - for (syn = opcode->syntax; *syn; ++syn) - { - int c; - - if (*syn != '%' || *++syn == '%') - { - (*func) (stream, "%c", *syn); - continue; - } - - /* We have an operand. Fetch any special modifiers. */ - mods = 0; - c = *syn; - while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags)) - { - mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS; - ++syn; - c = *syn; - } - operand = arc_operands + arc_operand_map[c]; - - /* Extract the value from the instruction. */ - opval = NULL; - if (operand->extract) - { - value = (*operand->extract) (insn, operand, mods, - &opval, (int *) NULL); - } - else - { - value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & (1 << (operand->bits - 1)))) - value -= 1 << operand->bits; - - /* If this is a suffix operand, set `opval'. */ - if (operand->flags & ARC_OPERAND_SUFFIX) - opval = arc_opcode_lookup_suffix (operand, value); - } - - /* Print the operand as directed by the flags. */ - if (operand->flags & ARC_OPERAND_FAKE) - ; /* nothing to do (??? at least not yet) */ - else if (operand->flags & ARC_OPERAND_SUFFIX) - { - /* Default suffixes aren't printed. Fortunately, they all have - zero values. Also, zero values for boolean suffixes are - represented by the absence of text. */ - - if (value != 0) - { - /* ??? OPVAL should have a value. If it doesn't just cope - as we want disassembly to be reasonably robust. - Also remember that several condition code values (16-31) - aren't defined yet. For these cases just print the - number suitably decorated. */ - if (opval) - (*func) (stream, "%s%s", - mods & ARC_MOD_DOT ? "." : "", - opval->name); - else - (*func) (stream, "%s%c%d", - mods & ARC_MOD_DOT ? "." : "", - operand->fmt, value); - } - } - else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) - (*info->print_address_func) (pc + 4 + value, info); - /* ??? Not all cases of this are currently caught. */ - else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (operand->flags & ARC_OPERAND_ADDRESS) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (opval) - /* Note that this case catches both normal and auxiliary regs. */ - (*func) (stream, "%s", opval->name); - else - (*func) (stream, "%ld", value); - } - - /* We have found and printed an instruction; return. */ - return got_limm_p ? 8 : 4; - } - - (*func) (stream, _("*unknown*")); - return 4; -} - -/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use. - This does things a non-standard way (the "standard" way would be to copy - this code into disassemble.c). Since there are more than a couple of - variants, hiding all this crud here seems cleaner. */ - -disassembler_ftype -arc_get_disassembler (mach, big_p) - int mach; - int big_p; -{ - switch (mach) - { - case bfd_mach_arc_base: - return big_p ? print_insn_arc_base_big : print_insn_arc_base_little; - } - return print_insn_arc_base_little; -} - -static int -print_insn_arc_base_little (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_base, 0); -} - -static int -print_insn_arc_base_big (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_base, 1); -} diff --git a/contrib/binutils/opcodes/arc-opc.c b/contrib/binutils/opcodes/arc-opc.c deleted file mode 100644 index f17ffc086fe9b..0000000000000 --- a/contrib/binutils/opcodes/arc-opc.c +++ /dev/null @@ -1,1131 +0,0 @@ -/* Opcode table for the ARC. - Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/arc.h" -#include "opintl.h" - -#ifndef NULL -#define NULL 0 -#endif - -#define INSERT_FN(fn) \ -static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **)) -#define EXTRACT_FN(fn) \ -static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *)) - -INSERT_FN (insert_reg); -INSERT_FN (insert_shimmfinish); -INSERT_FN (insert_limmfinish); -INSERT_FN (insert_shimmoffset); -INSERT_FN (insert_shimmzero); -INSERT_FN (insert_flag); -INSERT_FN (insert_flagfinish); -INSERT_FN (insert_cond); -INSERT_FN (insert_forcelimm); -INSERT_FN (insert_reladdr); -INSERT_FN (insert_absaddr); -INSERT_FN (insert_unopmacro); - -EXTRACT_FN (extract_reg); -EXTRACT_FN (extract_flag); -EXTRACT_FN (extract_cond); -EXTRACT_FN (extract_reladdr); -EXTRACT_FN (extract_unopmacro); - -/* Various types of ARC operands, including insn suffixes. */ - -/* Insn format values: - - 'a' REGA register A field - 'b' REGB register B field - 'c' REGC register C field - 'S' SHIMMFINISH finish inserting a shimm value - 'L' LIMMFINISH finish inserting a limm value - 'd' SHIMMOFFSET shimm offset in ld,st insns - '0' SHIMMZERO 0 shimm value in ld,st insns - 'f' FLAG F flag - 'F' FLAGFINISH finish inserting the F flag - 'G' FLAGINSN insert F flag in "flag" insn - 'n' DELAY N field (nullify field) - 'q' COND condition code field - 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm - 'B' BRANCH branch address (22 bit pc relative) - 'J' JUMP jump address (26 bit absolute) - 'z' SIZE1 size field in ld a,[b,c] - 'Z' SIZE10 size field in ld a,[b,shimm] - 'y' SIZE22 size field in st c,[b,shimm] - 'x' SIGN0 sign extend field ld a,[b,c] - 'X' SIGN9 sign extend field ld a,[b,shimm] - 'w' ADDRESS3 write-back field in ld a,[b,c] - 'W' ADDRESS12 write-back field in ld a,[b,shimm] - 'v' ADDRESS24 write-back field in st c,[b,shimm] - 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] - 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] - 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] - 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros - - The following modifiers may appear between the % and char (eg: %.f): - - '.' MODDOT '.' prefix must be present - 'r' REG generic register value, for register table - 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] - - Fields are: - - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN -*/ - -const struct arc_operand arc_operands[] = -{ -/* place holder (??? not sure if needed) */ -#define UNUSED 0 - { 0 }, - -/* register A or shimm/limm indicator */ -#define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, - -/* register B or shimm/limm indicator */ -#define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, - -/* register C or shimm/limm indicator */ -#define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, - -/* fake operand used to insert shimm value into most instructions */ -#define SHIMMFINISH (REGC + 1) - { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, - -/* fake operand used to insert limm value into most instructions. */ -#define LIMMFINISH (SHIMMFINISH + 1) - { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, - -/* shimm operand when there is no reg indicator (ld,st) */ -#define SHIMMOFFSET (LIMMFINISH + 1) - { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 }, - -/* 0 shimm operand for ld,st insns */ -#define SHIMMZERO (SHIMMOFFSET + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 }, - -/* flag update bit (insertion is defered until we know how) */ -#define FLAG (SHIMMZERO + 1) - { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, - -/* fake utility operand to finish 'f' suffix handling */ -#define FLAGFINISH (FLAG + 1) - { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, - -/* fake utility operand to set the 'f' flag for the "flag" insn */ -#define FLAGINSN (FLAGFINISH + 1) - { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, - -/* branch delay types */ -#define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX }, - -/* conditions */ -#define COND (DELAY + 1) - { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, - -/* set `cond_p' to 1 to ensure a constant is treated as a limm */ -#define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm }, - -/* branch address; b, bl, and lp insns */ -#define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr }, - -/* jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2) */ -#define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr }, - -/* size field, stored in bit 1,2 */ -#define SIZE1 (JUMP + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX }, - -/* size field, stored in bit 10,11 */ -#define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, }, - -/* size field, stored in bit 22,23 */ -#define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, }, - -/* sign extend field, stored in bit 0 */ -#define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX }, - -/* sign extend field, stored in bit 9 */ -#define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 3 */ -#define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 12 */ -#define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 24 */ -#define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 5 */ -#define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 14 */ -#define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 26 */ -#define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX }, - -/* unop macro, used to copy REGB to REGC */ -#define UNOPMACRO (CACHEBYPASS26 + 1) - { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, - -/* '.' modifier ('.' required). */ -#define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT }, - -/* Dummy 'r' modifier for the register table. - It's called a "dummy" because there's no point in inserting an 'r' into all - the %a/%b/%c occurrences in the insn table. */ -#define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG }, - -/* Known auxiliary register modifier (stored in shimm field). */ -#define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG }, - -/* end of list place holder */ - { 0 } -}; - -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* ARC instructions. - - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). This isn't necessary for `ld' because of the trailing ']'. - - Instructions that are really macros based on other insns must appear - before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. - - This table is best viewed on a wide screen (161 columns). I'd prefer to - keep it this way. The rest of the file, however, should be viewable on an - 80 column terminal. */ - -/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has - a more general facility for dealing with macros which could be used if - we need to. */ - -/* This table can't be `const' because members `next_asm' and `next_dis' are - computed at run-time. We could split this into two, but that doesn't seem - worth it. */ - -struct arc_opcode arc_opcodes[] = { - - /* Macros appear first. */ - /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) }, - /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, - /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, - /* "nop" is really an "xor". */ - { "nop", 0xffffffff, 0x7fffffff }, - /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) }, - - /* The rest of these needn't be sorted, but it helps to find them if they are. */ - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) }, - { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH }, - { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) }, - { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) }, - /* %Q: force cond_p=1 --> no shimm values */ - /* ??? This insn allows an optional flags spec. */ - { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. */ - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) }, - { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) }, - { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) }, - { "lp%q%.n %B", I(-1), I(6), }, - { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) }, - { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) }, - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) }, - { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) } -}; -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); - -const struct arc_operand_value arc_reg_names[] = -{ - /* Sort this so that the first 61 entries are sequential. - IE: For each i (i<61), arc_reg_names[i].value == i. */ - - { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG }, - { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG }, - { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG }, - { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG }, - { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG }, - { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG }, - { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG }, - { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG }, - { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG }, - { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG }, - { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG }, - { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG }, - { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG }, - { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG }, - { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG }, - { "lp_count", 60, REG }, - - /* I'd prefer to output these as "fp" and "sp" by default, but we still need - to recognize the canonical values. */ - { "r27", 27, REG }, { "r28", 28, REG }, - - /* Someone may wish to refer to these in this way, and it's probably a - good idea to reserve them as such anyway. */ - { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG }, - - /* Standard auxiliary registers. */ - { "status", 0, AUXREG }, - { "semaphore", 1, AUXREG }, - { "lp_start", 2, AUXREG }, - { "lp_end", 3, AUXREG }, - { "identity", 4, AUXREG }, - { "debug", 5, AUXREG }, -}; -const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); - -/* The suffix table. - Operands with the same name must be stored together. */ - -const struct arc_operand_value arc_suffixes[] = -{ - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1 }, - { "al", 0, COND }, - { "ra", 0, COND }, - { "eq", 1, COND }, - { "z", 1, COND }, - { "ne", 2, COND }, - { "nz", 2, COND }, - { "p", 3, COND }, - { "pl", 3, COND }, - { "n", 4, COND }, - { "mi", 4, COND }, - { "c", 5, COND }, - { "cs", 5, COND }, - { "lo", 5, COND }, - { "nc", 6, COND }, - { "cc", 6, COND }, - { "hs", 6, COND }, - { "v", 7, COND }, - { "vs", 7, COND }, - { "nv", 8, COND }, - { "vc", 8, COND }, - { "gt", 9, COND }, - { "ge", 10, COND }, - { "lt", 11, COND }, - { "le", 12, COND }, - { "hi", 13, COND }, - { "ls", 14, COND }, - { "pnz", 15, COND }, - { "f", 1, FLAG }, - { "nd", ARC_DELAY_NONE, DELAY }, - { "d", ARC_DELAY_NORMAL, DELAY }, - { "jd", ARC_DELAY_JUMP, DELAY }, -/*{ "b", 7, SIZEEXT },*/ -/*{ "b", 5, SIZESEX },*/ - { "b", 1, SIZE1 }, - { "b", 1, SIZE10 }, - { "b", 1, SIZE22 }, -/*{ "w", 8, SIZEEXT },*/ -/*{ "w", 6, SIZESEX },*/ - { "w", 2, SIZE1 }, - { "w", 2, SIZE10 }, - { "w", 2, SIZE22 }, - { "x", 1, SIGN0 }, - { "x", 1, SIGN9 }, - { "a", 1, ADDRESS3 }, - { "a", 1, ADDRESS12 }, - { "a", 1, ADDRESS24 }, - { "di", 1, CACHEBYPASS5 }, - { "di", 1, CACHEBYPASS14 }, - { "di", 1, CACHEBYPASS26 }, -}; -const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Indexed by first letter of opcode. Points to chain of opcodes with same - first letter. */ -static struct arc_opcode *opcode_map[26 + 1]; - -/* Indexed by insn code. Points to chain of opcodes with same insn code. */ -static struct arc_opcode *icode_map[32]; - -/* Configuration flags. */ - -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; - -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ - -int -arc_get_opcode_mach (bfd_mach, big_p) - int bfd_mach, big_p; -{ - static int mach_type_map[] = - { - ARC_MACH_BASE - }; - - return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); -} - -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). - - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ - -void -arc_opcode_init_tables (flags) - int flags; -{ - static int init_p = 0; - - cpu_type = flags; - - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). These tables only need to be init'd - once though. */ - /* ??? We can remove the need for arc_opcode_supported by taking it into - account here, but I'm not sure I want to do that yet (if ever). */ - if (!init_p) - { - register int i,n; - - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; ++i) - arc_operand_map[arc_operands[i].fmt] = i; - - memset (opcode_map, 0, sizeof (opcode_map)); - memset (icode_map, 0, sizeof (icode_map)); - /* Scan the table backwards so macros appear at the front. */ - for (i = arc_opcodes_count - 1; i >= 0; --i) - { - int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); - int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); - - arc_opcodes[i].next_asm = opcode_map[opcode_hash]; - opcode_map[opcode_hash] = &arc_opcodes[i]; - - arc_opcodes[i].next_dis = icode_map[icode_hash]; - icode_map[icode_hash] = &arc_opcodes[i]; - } - - init_p = 1; - } -} - -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opcode_supported (opcode) - const struct arc_opcode *opcode; -{ - if (ARC_OPCODE_CPU (opcode->flags) == 0) - return 1; - if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Return non-zero if OPVAL is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opval_supported (opval) - const struct arc_operand_value *opval; -{ - if (ARC_OPVAL_CPU (opval->flags) == 0) - return 1; - if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Return the first insn in the chain for assembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_asm (insn) - const char *insn; -{ - return opcode_map[ARC_HASH_OPCODE (insn)]; -} - -/* Return the first insn in the chain for disassembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_dis (insn) - unsigned int insn; -{ - return icode_map[ARC_HASH_ICODE (insn)]; -} - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times. */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -/* Insertion functions. */ - -/* Called by the assembler before parsing an instruction. */ - -void -arc_opcode_init_insert () -{ - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - shimm_p = 0; - limm_p = 0; -} - -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ - -int -arc_opcode_limm_p (limmp) - long *limmp; -{ - if (limmp) - *limmp = limm; - return limm_p; -} - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - static char buf[100]; - - if (reg == NULL) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - flagshimm_handled_p = 1; - shimm_p = 1; - shimm = value; - insn |= marker << operand->shift; - /* insn |= value & 511; - done later */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - { - *errmsg = _("unable to fit different valued constants into instruction"); - } - } - else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = _("auxiliary register not allowed here"); - else - { - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - /* xgettext:c-format */ - sprintf (buf, _("invalid register number `%d'"), reg->value); - *errmsg = buf; - } - else - insn |= reg->value << operand->shift; - } - } - - return insn; -} - -/* Called when we see an 'f' flag. */ - -static arc_insn -insert_flag (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - - return insn; -} - -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; -} - -/* Called when we see a conditional flag (eg: .eq). */ - -static arc_insn -insert_cond (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - cond_p = 1; - return insn; -} - -/* Used in ld/st insns to handle the shimm offset field. */ - -static arc_insn -insert_shimmoffset (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - long minval, maxval; - static char buf[100]; - - if (reg != NULL) - { - *errmsg = "register appears where shimm value expected"; - } - else - { - /* This is *way* more general than necessary, but maybe some day it'll - be useful. */ - if (operand->flags & ARC_OPERAND_SIGNED) - { - minval = -(1 << (operand->bits - 1)); - maxval = (1 << (operand->bits - 1)) - 1; - } - else - { - minval = 0; - maxval = (1 << operand->bits) - 1; - } - if (value < minval || value > maxval) - { - /* xgettext:c-format */ - sprintf (buf, _("value won't fit in range %ld - %ld"), - minval, maxval); - *errmsg = buf; - } - else - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - } - return insn; -} - -/* Used in ld/st insns when the shimm offset is 0. */ - -static arc_insn -insert_shimmzero (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - shimm_p = 1; - shimm = 0; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a shimm - value (if present) into the insn. */ - -static arc_insn -insert_shimmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a limm - value (if present) into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_limmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (limm_p) - ; /* nothing to do, gas does it */ - return insn; -} - -/* Called at the end of unary operand macros to copy the B field to C. */ - -static arc_insn -insert_unopmacro (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; - return insn; -} - -/* Insert a relative address for a branch insn (b, bl, or lp). */ - -static arc_insn -insert_reladdr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Insert a limm value as a 26 bit address right shifted 2 into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_absaddr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (limm_p) - ; /* nothing to do */ - return insn; -} - -/* Extraction functions. - - The suffix extraction functions' return value is redundant since it can be - obtained from (*OPVAL)->value. However, the boolean suffixes don't have - a suffix table entry for the "false" case, so values of zero must be - obtained from the return value (*OPVAL == NULL). */ - -static const struct arc_operand_value *lookup_register (int type, long regno); - -/* Called by the disassembler before printing an instruction. */ - -void -arc_opcode_init_extract () -{ - flag_p = 0; - flagshimm_handled_p = 0; - shimm_p = 0; - limm_p = 0; -} - -/* As we're extracting registers, keep an eye out for the 'f' indicator - (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, - like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. - - We must also handle auxiliary registers for lr/sr insns. They are just - constants with special names. */ - -static long -extract_reg (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int regno; - long value; - - /* Get the register number. */ - regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - - /* Is it a constant marker? */ - if (regno == ARC_REG_SHIMM) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_SHIMM_UPDATE) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flag_p = 1; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_LIMM) - { - value = insn[1]; - limm_p = 1; - } - /* It's a register, set OPVAL (that's the only way we distinguish registers - from constants here). */ - else - { - const struct arc_operand_value *reg = lookup_register (REG, regno); - - if (reg == NULL) - abort (); - if (opval != NULL) - *opval = reg; - value = regno; - } - - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); - - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg != NULL && opval != NULL) - *opval = reg; - } - - return value; -} - -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ - -static long -extract_flag (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int f; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (insn[0] & (1 << operand->shift)) != 0; - - /* There is no text for zero values. */ - if (f == 0) - return 0; - - val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; - return val->value; -} - -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ - -static long -extract_cond (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - long cond; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - return 0; - - cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); - - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; - return cond; -} - -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ - -static long -extract_reladdr (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - long addr; - - addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - - return addr << 2; -} - -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ - -static long -extract_unopmacro (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - /* This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; - - return 0; -} - -/* Utility for the extraction functions to return the index into - `arc_suffixes'. */ - -const struct arc_operand_value * -arc_opcode_lookup_suffix (type, value) - const struct arc_operand *type; - int value; -{ - register const struct arc_operand_value *v,*end; - - /* ??? This is a little slow and can be speeded up. */ - - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; -} - -static const struct arc_operand_value * -lookup_register (type, regno) - int type; - long regno; -{ - register const struct arc_operand_value *r,*end; - - if (type == REG) - return &arc_reg_names[regno]; - - /* ??? This is a little slow and can be speeded up. */ - - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; -} diff --git a/contrib/binutils/opcodes/arm-dis.c b/contrib/binutils/opcodes/arm-dis.c deleted file mode 100644 index f131adafebfbb..0000000000000 --- a/contrib/binutils/opcodes/arm-dis.c +++ /dev/null @@ -1,1065 +0,0 @@ -/* Instruction printing code for the ARM - Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc. - Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) - Modification by James G. Smith (jsmith@cygnus.co.uk) - -This file is part of libopcodes. - -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2 of the License, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#define DEFINE_TABLE -#include "arm-opc.h" -#include "coff/internal.h" -#include "libcoff.h" -#include "opintl.h" - -/* FIXME: This shouldn't be done here */ -#include "elf-bfd.h" -#include "elf/internal.h" -#include "elf/arm.h" - -#ifndef streq -#define streq(a,b) (strcmp ((a), (b)) == 0) -#endif - -#ifndef strneq -#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) -#endif - -#ifndef NUM_ELEM -#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) -#endif - -static char * arm_conditional[] = -{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; - -typedef struct -{ - const char * name; - const char * description; - const char * reg_names[16]; -} -arm_regname; - -static arm_regname regnames[] = -{ - { "raw" , "Select raw register names", - { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, - { "std", "Select register names used in ARM's ISA documentation", - { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, - { "apcs", "Select register names used in the APCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, - { "atpcs", "Select register names used in the ATPCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, - { "special-atpcs", "Select special register names used in the ATPCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} -}; - -/* Default to standard register name set. */ -static unsigned int regname_selected = 1; - -#define NUM_ARM_REGNAMES NUM_ELEM (regnames) -#define arm_regnames regnames[regname_selected].reg_names - -static boolean force_thumb = false; - -static char * arm_fp_const[] = -{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; - -static char * arm_shift[] = -{"lsl", "lsr", "asr", "ror"}; - -/* Forward declarations. */ -static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); -static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); -static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); -static void parse_disassembler_options PARAMS ((char *)); -static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); -int get_arm_regname_num_options (void); -int set_arm_regname_option (int option); -int get_arm_regnames (int option, const char **setname, - const char **setdescription, - const char ***register_names); - -/* Functions. */ -int -get_arm_regname_num_options (void) -{ - return NUM_ARM_REGNAMES; -} - -int -set_arm_regname_option (int option) -{ - int old = regname_selected; - regname_selected = option; - return old; -} - -int -get_arm_regnames (int option, const char **setname, - const char **setdescription, - const char ***register_names) -{ - *setname = regnames[option].name; - *setdescription = regnames[option].description; - *register_names = regnames[option].reg_names; - return 16; -} - -static void -arm_decode_shift (given, func, stream) - long given; - fprintf_ftype func; - void * stream; -{ - func (stream, "%s", arm_regnames[given & 0xf]); - - if ((given & 0xff0) != 0) - { - if ((given & 0x10) == 0) - { - int amount = (given & 0xf80) >> 7; - int shift = (given & 0x60) >> 5; - - if (amount == 0) - { - if (shift == 3) - { - func (stream, ", rrx"); - return; - } - - amount = 32; - } - - func (stream, ", %s #%d", arm_shift[shift], amount); - } - else - func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], - arm_regnames[(given & 0xf00) >> 8]); - } -} - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (always 4 on ARM). */ -static int -print_insn_arm (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; -{ - struct arm_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; - - for (insn = arm_opcodes; insn->assembler; insn++) - { - if ((given & insn->mask) == insn->value) - { - char * c; - - for (c = insn->assembler; *c; c++) - { - if (*c == '%') - { - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'a': - if (((given & 0x000f0000) == 0x000f0000) - && ((given & 0x02000000) == 0)) - { - int offset = given & 0xfff; - - func (stream, "[pc"); - - if (given & 0x01000000) - { - if ((given & 0x00800000) == 0) - offset = - offset; - - /* pre-indexed */ - func (stream, ", #%x]", offset); - - offset += pc + 8; - - /* Cope with the possibility of write-back - being used. Probably a very dangerous thing - for the programmer to do, but who are we to - argue ? */ - if (given & 0x00200000) - func (stream, "!"); - } - else - { - /* Post indexed. */ - func (stream, "], #%x", offset); - - offset = pc + 8; /* ie ignore the offset. */ - } - - func (stream, "\t; "); - info->print_address_func (offset, info); - } - else - { - func (stream, "[%s", - arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - if ((given & 0x02000000) == 0) - { - int offset = given & 0xfff; - if (offset) - func (stream, ", %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - } - else - { - func (stream, ", %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream); - } - - func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); - } - else - { - if ((given & 0x02000000) == 0) - { - int offset = given & 0xfff; - if (offset) - func (stream, "], %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); - } - else - { - func (stream, "], %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream); - } - } - } - break; - - case 's': - if ((given & 0x004f0000) == 0x004f0000) - { - /* PC relative with immediate offset. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - - if ((given & 0x00800000) == 0) - offset = -offset; - - func (stream, "[pc, #%x]\t; ", offset); - - (*info->print_address_func) - (offset + pc + 8, info); - } - else - { - func (stream, "[%s", - arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - /* Pre-indexed. */ - if ((given & 0x00400000) == 0x00400000) - { - /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, ", %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - } - else - { - /* Register. */ - func (stream, ", %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); - } - - func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); - } - else - { - /* Post-indexed. */ - if ((given & 0x00400000) == 0x00400000) - { - /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, "], %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); - } - else - { - /* Register. */ - func (stream, "], %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); - } - } - } - break; - - case 'b': - (*info->print_address_func) - (BDISP (given) * 4 + pc + 8, info); - break; - - case 'c': - func (stream, "%s", - arm_conditional [(given >> 28) & 0xf]); - break; - - case 'm': - { - int started = 0; - int reg; - - func (stream, "{"); - for (reg = 0; reg < 16; reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - func (stream, "}"); - } - break; - - case 'o': - if ((given & 0x02000000) != 0) - { - int rotate = (given & 0xf00) >> 7; - int immed = (given & 0xff); - immed = (((immed << (32 - rotate)) - | (immed >> rotate)) & 0xffffffff); - func (stream, "#%d\t; 0x%x", immed, immed); - } - else - arm_decode_shift (given, func, stream); - break; - - case 'p': - if ((given & 0x0000f000) == 0x0000f000) - func (stream, "p"); - break; - - case 't': - if ((given & 0x01200000) == 0x00200000) - func (stream, "t"); - break; - - case 'h': - if ((given & 0x00000020) == 0x00000020) - func (stream, "h"); - else - func (stream, "b"); - break; - - case 'A': - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - int offset = given & 0xff; - if (offset) - func (stream, ", %s#%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "]"); - } - else - { - int offset = given & 0xff; - if (offset) - func (stream, "], %s#%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); - else - func (stream, "]"); - } - break; - - case 'C': - switch (given & 0x00090000) - { - default: - func (stream, "_???"); - break; - case 0x90000: - func (stream, "_all"); - break; - case 0x10000: - func (stream, "_ctl"); - break; - case 0x80000: - func (stream, "_flg"); - break; - } - break; - - case 'F': - switch (given & 0x00408000) - { - case 0: - func (stream, "4"); - break; - case 0x8000: - func (stream, "1"); - break; - case 0x00400000: - func (stream, "2"); - break; - default: - func (stream, "3"); - } - break; - - case 'P': - switch (given & 0x00080080) - { - case 0: - func (stream, "s"); - break; - case 0x80: - func (stream, "d"); - break; - case 0x00080000: - func (stream, "e"); - break; - default: - func (stream, _("<illegal precision>")); - break; - } - break; - case 'Q': - switch (given & 0x00408000) - { - case 0: - func (stream, "s"); - break; - case 0x8000: - func (stream, "d"); - break; - case 0x00400000: - func (stream, "e"); - break; - default: - func (stream, "p"); - break; - } - break; - case 'R': - switch (given & 0x60) - { - case 0: - break; - case 0x20: - func (stream, "p"); - break; - case 0x40: - func (stream, "m"); - break; - default: - func (stream, "z"); - break; - } - break; - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - c++; - - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - - if (!bitend) - abort (); - - switch (*c) - { - case 'r': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%s", arm_regnames[reg]); - } - break; - case 'd': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%d", reg); - } - break; - case 'x': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "0x%08x", reg); - - /* Some SWI instructions have special - meanings. */ - if ((given & 0x0fffffff) == 0x0FF00000) - func (stream, "\t; IMB"); - else if ((given & 0x0fffffff) == 0x0FF00001) - func (stream, "\t; IMBRange"); - } - break; - case 'X': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%01x", reg & 0xf); - } - break; - case 'f': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - if (reg > 7) - func (stream, "#%s", - arm_fp_const[reg & 7]); - else - func (stream, "f%d", reg); - } - break; - default: - abort (); - } - break; - - case '`': - c++; - if ((given & (1 << bitstart)) == 0) - func (stream, "%c", *c); - break; - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - default: - abort (); - } - break; - - default: - abort (); - } - } - } - else - func (stream, "%c", *c); - } - return 4; - } - } - abort (); -} - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction. */ -static int -print_insn_thumb (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; -{ - struct thumb_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; - - for (insn = thumb_opcodes; insn->assembler; insn++) - { - if ((given & insn->mask) == insn->value) - { - char * c = insn->assembler; - - /* Special processing for Thumb 2 instruction BL sequence: */ - if (!*c) /* Check for empty (not NULL) assembler string. */ - { - info->bytes_per_chunk = 4; - info->bytes_per_line = 4; - - func (stream, "bl\t"); - - info->print_address_func (BDISP23 (given) * 2 + pc + 4, info); - return 4; - } - else - { - info->bytes_per_chunk = 2; - info->bytes_per_line = 4; - - given &= 0xffff; - - for (; *c; c++) - { - if (*c == '%') - { - int domaskpc = 0; - int domasklr = 0; - - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'S': - { - long reg; - - reg = (given >> 3) & 0x7; - if (given & (1 << 6)) - reg += 8; - - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'D': - { - long reg; - - reg = given & 0x7; - if (given & (1 << 7)) - reg += 8; - - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'T': - func (stream, "%s", - arm_conditional [(given >> 8) & 0xf]); - break; - - case 'N': - if (given & (1 << 8)) - domasklr = 1; - /* Fall through. */ - case 'O': - if (*c == 'O' && (given & (1 << 8))) - domaskpc = 1; - /* Fall through. */ - case 'M': - { - int started = 0; - int reg; - - func (stream, "{"); - - /* It would be nice if we could spot - ranges, and generate the rS-rE format: */ - for (reg = 0; (reg < 8); reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - - if (domasklr) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, arm_regnames[14] /* "lr" */); - } - - if (domaskpc) - { - if (started) - func (stream, ", "); - func (stream, arm_regnames[15] /* "pc" */); - } - - func (stream, "}"); - } - break; - - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - { - long reg; - - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - switch (*c) - { - case 'r': - func (stream, "%s", arm_regnames[reg]); - break; - - case 'd': - func (stream, "%d", reg); - break; - - case 'H': - func (stream, "%d", reg << 1); - break; - - case 'W': - func (stream, "%d", reg << 2); - break; - - case 'a': - /* PC-relative address -- the bottom two - bits of the address are dropped - before the calculation. */ - info->print_address_func - (((pc + 4) & ~3) + (reg << 2), info); - break; - - case 'x': - func (stream, "0x%04x", reg); - break; - - case 'I': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - func (stream, "%d", reg); - break; - - case 'B': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - (*info->print_address_func) - (reg * 2 + pc + 4, info); - break; - - default: - abort (); - } - } - break; - - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - - default: - abort (); - } - } - break; - - default: - abort (); - } - } - else - func (stream, "%c", *c); - } - } - return 2; - } - } - - /* No match. */ - abort (); -} - -/* Parse an individual disassembler option. */ -void -parse_arm_disassembler_option (option) - char * option; -{ - if (option == NULL) - return; - - if (strneq (option, "reg-names-", 10)) - { - int i; - - option += 10; - - for (i = NUM_ARM_REGNAMES; i--;) - if (streq (option, regnames[i].name)) - { - regname_selected = i; - break; - } - - if (i < 0) - fprintf (stderr, _("Unrecognised register name set: %s\n"), option); - } - else if (streq (option, "force-thumb")) - force_thumb = 1; - else if (streq (option, "no-force-thumb")) - force_thumb = 0; - else - fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); - - return; -} - -/* Parse the string of disassembler options, spliting it at whitespaces. */ -static void -parse_disassembler_options (options) - char * options; -{ - char * space; - - if (options == NULL) - return; - - do - { - space = strchr (options, ' '); - - if (space) - { - * space = '\0'; - parse_arm_disassembler_option (options); - * space = ' '; - options = space + 1; - } - else - parse_arm_disassembler_option (options); - } - while (space); -} - -/* NOTE: There are no checks in these routines that - the relevant number of data bytes exist. */ -static int -print_insn (pc, info, little) - bfd_vma pc; - struct disassemble_info * info; - boolean little; -{ - unsigned char b[4]; - long given; - int status; - int is_thumb; - - if (info->disassembler_options) - { - parse_disassembler_options (info->disassembler_options); - - /* To avoid repeated parsing of these options, we remove them here. */ - info->disassembler_options = NULL; - } - - is_thumb = force_thumb; - - if (!is_thumb && info->symbols != NULL) - { - if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) - { - coff_symbol_type * cs; - - cs = coffsymbol (*info->symbols); - is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT - || cs->native->u.syment.n_sclass == C_THUMBSTAT - || cs->native->u.syment.n_sclass == C_THUMBLABEL - || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC - || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); - } - else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) - { - elf_symbol_type * es; - unsigned int type; - - es = *(elf_symbol_type **)(info->symbols); - type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - - is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); - } - } - - info->bytes_per_chunk = 4; - info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; - - if (little) - { - status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); - if (status != 0 && is_thumb) - { - info->bytes_per_chunk = 2; - - status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); - b[3] = b[2] = 0; - } - - if (status != 0) - { - info->memory_error_func (status, pc, info); - return -1; - } - - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); - } - else - { - status = info->read_memory_func - (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); - if (status != 0) - { - info->memory_error_func (status, pc, info); - return -1; - } - - if (is_thumb) - { - if (pc & 0x2) - { - given = (b[2] << 8) | b[3]; - - status = info->read_memory_func - ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); - if (status != 0) - { - info->memory_error_func (status, pc + 4, info); - return -1; - } - - given |= (b[0] << 24) | (b[1] << 16); - } - else - given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); - } - else - given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); - } - - if (is_thumb) - status = print_insn_thumb (pc, info, given); - else - status = print_insn_arm (pc, info, given); - - return status; -} - -int -print_insn_big_arm (pc, info) - bfd_vma pc; - struct disassemble_info * info; -{ - return print_insn (pc, info, false); -} - -int -print_insn_little_arm (pc, info) - bfd_vma pc; - struct disassemble_info * info; -{ - return print_insn (pc, info, true); -} - -void -print_arm_disassembler_options (FILE * stream) -{ - int i; - - fprintf (stream, _("\n\ -The following ARM specific disassembler options are supported for use with\n\ -the -M switch:\n")); - - for (i = NUM_ARM_REGNAMES; i--;) - fprintf (stream, " reg-names-%s %*c%s\n", - regnames[i].name, - 14 - strlen (regnames[i].name), ' ', - regnames[i].description); - - fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); - fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); -} diff --git a/contrib/binutils/opcodes/arm-opc.h b/contrib/binutils/opcodes/arm-opc.h deleted file mode 100644 index 44a16a425f02b..0000000000000 --- a/contrib/binutils/opcodes/arm-opc.h +++ /dev/null @@ -1,284 +0,0 @@ -/* Opcode table for the ARM. - - Copyright 1994, 1995, 1996, 1997 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -struct arm_opcode { - unsigned long value, mask; /* recognise instruction if (op&mask)==value */ - char *assembler; /* how to disassemble this instruction */ -}; - -struct thumb_opcode -{ - unsigned short value, mask; /* recognise instruction if (op&mask)==value */ - char * assembler; /* how to disassemble this instruction */ -}; - -/* format of the assembler string : - - %% % - %<bitfield>d print the bitfield in decimal - %<bitfield>x print the bitfield in hex - %<bitfield>X print the bitfield as 1 hex digit without leading "0x" - %<bitfield>r print as an ARM register - %<bitfield>f print a floating point constant if >7 else a - floating point register - %c print condition code (always bits 28-31) - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b - %p print 'p' iff bits 12-15 are 15 - %t print 't' iff bit 21 set and bit 24 clear - %h print 'h' iff bit 5 set, else print 'b' - %o print operand2 (immediate or register + shift) - %a print address for ldr/str instruction - %s print address for ldr/str halfword/signextend instruction - %b print branch destination - %A print address for ldc/stc/ldf/stf instruction - %m print register mask for ldm/stm instruction - %C print the PSR sub type. - %F print the COUNT field of a LFM/SFM instruction. -Thumb specific format options: - %D print Thumb register (bits 0..2 as high number if bit 7 set) - %S print Thumb register (bits 3..5 as high number if bit 6 set) - %<bitfield>I print bitfield as a signed decimal - (top bit of range being the sign bit) - %M print Thumb register mask - %N print Thumb register mask (with LR) - %O print Thumb register mask (with PC) - %T print Thumb condition code (always bits 8-11) - %<bitfield>B print Thumb branch destination (signed displacement) - %<bitfield>W print (bitfield * 4) as a decimal - %<bitfield>H print (bitfield * 2) as a decimal - %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol -*/ - -/* Note: There is a partial ordering in this table - it must be searched from - the top to obtain a correct match. */ - -static struct arm_opcode arm_opcodes[] = -{ - /* ARM instructions */ - {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, - {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, - {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, - {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, - {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, - {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, - {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, - {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, - {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, - {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, - {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, - {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, - {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, - {0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"}, - {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"}, - {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, - {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, - {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, - {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, - {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, - {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, - {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, - {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, - {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, - {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, - {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, - {0x06000010, 0x0e000010, "undefined"}, - {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, - {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, - {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, - - /* Floating point coprocessor instructions */ - {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, - {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, - {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, - {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, - {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, - {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, - {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, - {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, - {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, - {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, - {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, - {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, - {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, - {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, - {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, - {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, - {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, - {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, - {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, - {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, - {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, - {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, - {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, - {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, - {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, - {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, - {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, - {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, - - /* Generic coprocessor instructions */ - {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, - {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, - - /* The rest. */ - {0x00000000, 0x00000000, "undefined instruction %0-31x"}, - {0x00000000, 0x00000000, 0} -}; - -#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ - -static struct thumb_opcode thumb_opcodes[] = -{ - /* Thumb instructions */ - {0x46C0, 0xFFFF, "nop\t\t\t(mov r8,r8)"}, /* format 5 instructions do not update the PSR */ - {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, - /* format 4 */ - {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, - {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, - {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, - {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, - {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, - {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, - {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, - {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, - {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, - {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, - {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, - {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, - {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, - {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, - {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, - {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, - /* format 13 */ - {0xB000, 0xFF80, "add\tsp, #%0-6W"}, - {0xB080, 0xFF80, "sub\tsp, #%0-6W"}, - /* format 5 */ - {0x4700, 0xFF80, "bx\t%S"}, - {0x4400, 0xFF00, "add\t%D, %S"}, - {0x4500, 0xFF00, "cmp\t%D, %S"}, - {0x4600, 0xFF00, "mov\t%D, %S"}, - /* format 14 */ - {0xB400, 0xFE00, "push\t%N"}, - {0xBC00, 0xFE00, "pop\t%O"}, - /* format 2 */ - {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, - {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, - {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, - {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, - /* format 8 */ - {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, - {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, - {0x5600, 0xF600, "lds%11?hb\t%0-2r, [%3-5r, %6-8r]"}, - /* format 7 */ - {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, - {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, - /* format 1 */ - {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, - {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, - {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, - /* format 3 */ - {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, - {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, - {0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, - {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, - /* format 6 */ - {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ - /* format 9 */ - {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* format 10 */ - {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, - {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, - /* format 11 */ - {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, - {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, - /* format 12 */ - {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, - {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, - /* format 15 */ - {0xC000, 0xF800, "stmia\t%8-10r!,%M"}, - {0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, - /* format 18 */ - {0xE000, 0xF800, "b\t%0-10B"}, - {0xE800, 0xF800, "undefined"}, - /* format 19 */ - {0xF000, 0xF800, ""}, /* special processing required in disassembler */ - {0xF800, 0xF800, "second half of BL instruction %0-15x"}, - /* format 16 */ - {0xD000, 0xFF00, "beq\t%0-7B"}, - {0xD100, 0xFF00, "bne\t%0-7B"}, - {0xD200, 0xFF00, "bcs\t%0-7B"}, - {0xD300, 0xFF00, "bcc\t%0-7B"}, - {0xD400, 0xFF00, "bmi\t%0-7B"}, - {0xD500, 0xFF00, "bpl\t%0-7B"}, - {0xD600, 0xFF00, "bvs\t%0-7B"}, - {0xD700, 0xFF00, "bvc\t%0-7B"}, - {0xD800, 0xFF00, "bhi\t%0-7B"}, - {0xD900, 0xFF00, "bls\t%0-7B"}, - {0xDA00, 0xFF00, "bge\t%0-7B"}, - {0xDB00, 0xFF00, "blt\t%0-7B"}, - {0xDC00, 0xFF00, "bgt\t%0-7B"}, - {0xDD00, 0xFF00, "ble\t%0-7B"}, - /* format 17 */ - {0xDE00, 0xFF00, "bal\t%0-7B"}, - {0xDF00, 0xFF00, "swi\t%0-7d"}, - /* format 9 */ - {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* the rest */ - {0x0000, 0x0000, "undefined instruction %0-15x"}, - {0x0000, 0x0000, 0} -}; - -#define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \ - ^ 0x200000) - 0x200000) /* 23bit */ - diff --git a/contrib/binutils/opcodes/cgen-asm.c b/contrib/binutils/opcodes/cgen-asm.c deleted file mode 100644 index 4ed69363a9db4..0000000000000 --- a/contrib/binutils/opcodes/cgen-asm.c +++ /dev/null @@ -1,359 +0,0 @@ -/* CGEN generic assembler support code. - - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include <ctype.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" -#include "opintl.h" - -/* Set the cgen_parse_operand_fn callback. */ - -void -cgen_set_parse_operand_fn (cd, fn) - CGEN_CPU_DESC cd; - cgen_parse_operand_fn fn; -{ - cd->parse_operand_fn = fn; -} - -/* Called whenever starting to parse an insn. */ - -void -cgen_init_parse_operand (cd) - CGEN_CPU_DESC cd; -{ - /* This tells the callback to re-initialize. */ - (void) (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, NULL, NULL); -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_IBASE) for the target. - ??? No longer used but leave in for now. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN *insns; - int count; - int entsize; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; -{ - int i; - - for (i = count - 1; i >= 0; --i, ++hentbuf) - { - unsigned int hash; - const CGEN_INSN *insn = &insns[i]; - - if (! (* cd->asm_hash_p) (insn)) - continue; - hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; -{ - const CGEN_INSN_LIST *ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - - if (! (* cd->asm_hash_p) (ilist->insn)) - continue; - hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (ilist->insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = ilist->insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Build the assembler instruction hash table. */ - -static void -build_asm_hash_table (cd) - CGEN_CPU_DESC cd; -{ - int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); - CGEN_INSN_TABLE *insn_table = &cd->insn_table; - CGEN_INSN_TABLE *macro_insn_table = &cd->macro_insn_table; - unsigned int hash_size = cd->asm_hash_size; - CGEN_INSN_LIST *hash_entry_buf; - CGEN_INSN_LIST **asm_hash_table; - CGEN_INSN_LIST *asm_hash_table_entries; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - asm_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (asm_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - asm_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "invalid insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array (cd, - insn_table->init_entries + 1, - insn_table->num_init_entries - 1, - insn_table->entry_size, - asm_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - asm_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, - asm_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (cd, macro_insn_table->new_entries, - asm_hash_table, hash_entry_buf); - - cd->asm_hash_table = asm_hash_table; - cd->asm_hash_table_entries = asm_hash_table_entries; -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_asm_lookup_insn (cd, insn) - CGEN_CPU_DESC cd; - const char *insn; -{ - unsigned int hash; - - if (cd->asm_hash_table == NULL) - build_asm_hash_table (cd); - - hash = (* cd->asm_hash) (insn); - return cd->asm_hash_table[hash]; -} - -/* Keyword parser. - The result is NULL upon success or an error message. - If successful, *STRP is updated to point passed the keyword. - - ??? At present we have a static notion of how to pick out a keyword. - Later we can allow a target to customize this if necessary [say by - recording something in the keyword table]. */ - -const char * -cgen_parse_keyword (cd, strp, keyword_table, valuep) - CGEN_CPU_DESC cd; - const char **strp; - CGEN_KEYWORD *keyword_table; - long *valuep; -{ - const CGEN_KEYWORD_ENTRY *ke; - char buf[256]; - const char *p,*start; - - p = start = *strp; - - /* Allow any first character. - Note that this allows recognizing ",a" for the annul flag in sparc - even though "," is subsequently not a valid keyword char. */ - if (*p) - ++p; - - /* Now allow letters, digits, and _. */ - while (((p - start) < (int) sizeof (buf)) - && (isalnum ((unsigned char) *p) || *p == '_')) - ++p; - - if (p - start >= (int) sizeof (buf)) - return _("unrecognized keyword/register name"); - - memcpy (buf, start, p - start); - buf[p - start] = 0; - - ke = cgen_keyword_lookup_name (keyword_table, buf); - - if (ke != NULL) - { - *valuep = ke->value; - /* Don't advance pointer if we recognized the null keyword. */ - if (ke->name[0] != 0) - *strp = p; - return NULL; - } - - return "unrecognized keyword/register name"; -} - -/* Parse a small signed integer parser. - ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. - Note that if the caller expects a bfd_vma result, it should call - cgen_parse_address. */ - -const char * -cgen_parse_signed_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Parse a small unsigned integer parser. - ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. - Note that if the caller expects a bfd_vma result, it should call - cgen_parse_address. */ - -const char * -cgen_parse_unsigned_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Address parser. */ - -const char * -cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - int opinfo; - enum cgen_parse_operand_result *resultp; - bfd_vma *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result_type; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_ADDRESS, strp, opindex, opinfo, - &result_type, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - { - if (resultp != NULL) - *resultp = result_type; - *valuep = value; - } - return errmsg; -} - -/* Signed integer validation routine. */ - -const char * -cgen_validate_signed_integer (value, min, max) - long value, min, max; -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%ld not between %ld and %ld)"), - value, min, max); - return buf; - } - - return NULL; -} - -/* Unsigned integer validation routine. - Supplying `min' here may seem unnecessary, but we also want to handle - cases where min != 0 (and max > LONG_MAX). */ - -const char * -cgen_validate_unsigned_integer (value, min, max) - unsigned long value, min, max; -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%lu not between %lu and %lu)"), - value, min, max); - return buf; - } - - return NULL; -} diff --git a/contrib/binutils/opcodes/cgen-dis.c b/contrib/binutils/opcodes/cgen-dis.c deleted file mode 100644 index 78b1cd90ed918..0000000000000 --- a/contrib/binutils/opcodes/cgen-dis.c +++ /dev/null @@ -1,226 +0,0 @@ -/* CGEN generic disassembler support code. - - Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -/* Subroutine of build_dis_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_IBASE) for the target. - ??? No longer used but leave in for now. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN * insns; - int count; - int entsize; - CGEN_INSN_LIST ** htable; - CGEN_INSN_LIST * hentbuf; -{ - int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; - int i; - - for (i = count - 1; i >= 0; --i, ++hentbuf) - { - unsigned int hash; - char buf [4]; - unsigned long value; - const CGEN_INSN *insn = &insns[i]; - - if (! (* cd->dis_hash_p) (insn)) - continue; - - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - - value = CGEN_INSN_BASE_VALUE (insn); - switch (CGEN_INSN_MASK_BITSIZE (insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - - hash = (* cd->dis_hash) (buf, value); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Subroutine of build_dis_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; -{ - int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; - const CGEN_INSN_LIST *ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - char buf[4]; - unsigned long value; - - if (! (* cd->dis_hash_p) (ilist->insn)) - continue; - - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - - value = CGEN_INSN_BASE_VALUE (ilist->insn); - switch (CGEN_INSN_MASK_BITSIZE (ilist->insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - - hash = (* cd->dis_hash) (buf, value); - hentbuf->next = htable [hash]; - hentbuf->insn = ilist->insn; - htable [hash] = hentbuf; - } - - return hentbuf; -} - -/* Build the disassembler instruction hash table. */ - -static void -build_dis_hash_table (cd) - CGEN_CPU_DESC cd; -{ - int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); - CGEN_INSN_TABLE *insn_table = & cd->insn_table; - CGEN_INSN_TABLE *macro_insn_table = & cd->macro_insn_table; - unsigned int hash_size = cd->dis_hash_size; - CGEN_INSN_LIST *hash_entry_buf; - CGEN_INSN_LIST **dis_hash_table; - CGEN_INSN_LIST *dis_hash_table_entries; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - dis_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (dis_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - dis_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "invalid insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array (cd, - insn_table->init_entries + 1, - insn_table->num_init_entries - 1, - insn_table->entry_size, - dis_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - dis_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, - dis_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (cd, macro_insn_table->new_entries, - dis_hash_table, hash_entry_buf); - - cd->dis_hash_table = dis_hash_table; - cd->dis_hash_table_entries = dis_hash_table_entries; -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_dis_lookup_insn (cd, buf, value) - CGEN_CPU_DESC cd; - const char * buf; - CGEN_INSN_INT value; -{ - unsigned int hash; - - if (cd->dis_hash_table == NULL) - build_dis_hash_table (cd); - - hash = (* cd->dis_hash) (buf, value); - - return cd->dis_hash_table[hash]; -} diff --git a/contrib/binutils/opcodes/cgen-opc.c b/contrib/binutils/opcodes/cgen-opc.c deleted file mode 100644 index ede3adde11531..0000000000000 --- a/contrib/binutils/opcodes/cgen-opc.c +++ /dev/null @@ -1,621 +0,0 @@ -/* CGEN generic opcode support. - - Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <ctype.h> -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -static unsigned int hash_keyword_name - PARAMS ((const CGEN_KEYWORD *, const char *, int)); -static unsigned int hash_keyword_value - PARAMS ((const CGEN_KEYWORD *, unsigned int)); -static void build_keyword_hash_tables - PARAMS ((CGEN_KEYWORD *)); - -/* Return number of hash table entries to use for N elements. */ -#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) - -/* Look up *NAMEP in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_name (kt, name) - CGEN_KEYWORD *kt; - const char *name; -{ - const CGEN_KEYWORD_ENTRY *ke; - const char *p,*n; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)]; - - /* We do case insensitive comparisons. - If that ever becomes a problem, add an attribute that denotes - "do case sensitive comparisons". */ - - while (ke != NULL) - { - n = name; - p = ke->name; - - while (*p - && (*p == *n - || (isalpha ((unsigned char) *p) - && (tolower ((unsigned char) *p) - == tolower ((unsigned char) *n))))) - ++n, ++p; - - if (!*p && !*n) - return ke; - - ke = ke->next_name; - } - - if (kt->null_entry) - return kt->null_entry; - return NULL; -} - -/* Look up VALUE in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_value (kt, value) - CGEN_KEYWORD *kt; - int value; -{ - const CGEN_KEYWORD_ENTRY *ke; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->value_hash_table[hash_keyword_value (kt, value)]; - - while (ke != NULL) - { - if (value == ke->value) - return ke; - ke = ke->next_value; - } - - return NULL; -} - -/* Add an entry to a keyword table. */ - -void -cgen_keyword_add (kt, ke) - CGEN_KEYWORD *kt; - CGEN_KEYWORD_ENTRY *ke; -{ - unsigned int hash; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - hash = hash_keyword_name (kt, ke->name, 0); - ke->next_name = kt->name_hash_table[hash]; - kt->name_hash_table[hash] = ke; - - hash = hash_keyword_value (kt, ke->value); - ke->next_value = kt->value_hash_table[hash]; - kt->value_hash_table[hash] = ke; - - if (ke->name[0] == 0) - kt->null_entry = ke; -} - -/* FIXME: Need function to return count of keywords. */ - -/* Initialize a keyword table search. - SPEC is a specification of what to search for. - A value of NULL means to find every keyword. - Currently NULL is the only acceptable value [further specification - deferred]. - The result is an opaque data item used to record the search status. - It is passed to each call to cgen_keyword_search_next. */ - -CGEN_KEYWORD_SEARCH -cgen_keyword_search_init (kt, spec) - CGEN_KEYWORD *kt; - const char *spec; -{ - CGEN_KEYWORD_SEARCH search; - - /* FIXME: Need to specify format of PARAMS. */ - if (spec != NULL) - abort (); - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - search.table = kt; - search.spec = spec; - search.current_hash = 0; - search.current_entry = NULL; - return search; -} - -/* Return the next keyword specified by SEARCH. - The result is the next entry or NULL if there are no more. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_search_next (search) - CGEN_KEYWORD_SEARCH *search; -{ - /* Has search finished? */ - if (search->current_hash == search->table->hash_table_size) - return NULL; - - /* Search in progress? */ - if (search->current_entry != NULL - /* Anything left on this hash chain? */ - && search->current_entry->next_name != NULL) - { - search->current_entry = search->current_entry->next_name; - return search->current_entry; - } - - /* Move to next hash chain [unless we haven't started yet]. */ - if (search->current_entry != NULL) - ++search->current_hash; - - while (search->current_hash < search->table->hash_table_size) - { - search->current_entry = search->table->name_hash_table[search->current_hash]; - if (search->current_entry != NULL) - return search->current_entry; - ++search->current_hash; - } - - return NULL; -} - -/* Return first entry in hash chain for NAME. - If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ - -static unsigned int -hash_keyword_name (kt, name, case_sensitive_p) - const CGEN_KEYWORD *kt; - const char *name; - int case_sensitive_p; -{ - unsigned int hash; - - if (case_sensitive_p) - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) *name; - else - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) tolower (*name); - return hash % kt->hash_table_size; -} - -/* Return first entry in hash chain for VALUE. */ - -static unsigned int -hash_keyword_value (kt, value) - const CGEN_KEYWORD *kt; - unsigned int value; -{ - return value % kt->hash_table_size; -} - -/* Build a keyword table's hash tables. - We probably needn't build the value hash table for the assembler when - we're using the disassembler, but we keep things simple. */ - -static void -build_keyword_hash_tables (kt) - CGEN_KEYWORD *kt; -{ - int i; - /* Use the number of compiled in entries as an estimate for the - typical sized table [not too many added at runtime]. */ - unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); - - kt->hash_table_size = size; - kt->name_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - kt->value_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - - /* The table is scanned backwards as we want keywords appearing earlier to - be prefered over later ones. */ - for (i = kt->num_init_entries - 1; i >= 0; --i) - cgen_keyword_add (kt, &kt->init_entries[i]); -} - -/* Hardware support. */ - -/* Lookup a hardware element by its name. - Returns NULL if NAME is not supported by the currently selected - mach/isa. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; -{ - int i; - const CGEN_HW_ENTRY **hw = cd->hw_table.entries; - - for (i = 0; i < cd->hw_table.num_entries; ++i) - if (hw[i] && strcmp (name, hw[i]->name) == 0) - return hw[i]; - - return NULL; -} - -/* Lookup a hardware element by its number. - Hardware elements are enumerated, however it may be possible to add some - at runtime, thus HWNUM is not an enum type but rather an int. - Returns NULL if HWNUM is not supported by the currently selected mach. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_num (cd, hwnum) - CGEN_CPU_DESC cd; - int hwnum; -{ - int i; - const CGEN_HW_ENTRY **hw = cd->hw_table.entries; - - /* ??? This can be speeded up. */ - for (i = 0; i < cd->hw_table.num_entries; ++i) - if (hw[i] && hwnum == hw[i]->type) - return hw[i]; - - return NULL; -} - -/* Operand support. */ - -/* Lookup an operand by its name. - Returns NULL if NAME is not supported by the currently selected - mach/isa. */ - -const CGEN_OPERAND * -cgen_operand_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; -{ - int i; - const CGEN_OPERAND **op = cd->operand_table.entries; - - for (i = 0; i < cd->operand_table.num_entries; ++i) - if (op[i] && strcmp (name, op[i]->name) == 0) - return op[i]; - - return NULL; -} - -/* Lookup an operand by its number. - Operands are enumerated, however it may be possible to add some - at runtime, thus OPNUM is not an enum type but rather an int. - Returns NULL if OPNUM is not supported by the currently selected - mach/isa. */ - -const CGEN_OPERAND * -cgen_operand_lookup_by_num (cd, opnum) - CGEN_CPU_DESC cd; - int opnum; -{ - return cd->operand_table.entries[opnum]; -} - -/* Instruction support. */ - -/* Return number of instructions. This includes any added at runtime. */ - -int -cgen_insn_count (cd) - CGEN_CPU_DESC cd; -{ - int count = cd->insn_table.num_init_entries; - CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; - - for ( ; rt_insns != NULL; rt_insns = rt_insns->next) - ++count; - - return count; -} - -/* Return number of macro-instructions. - This includes any added at runtime. */ - -int -cgen_macro_insn_count (cd) - CGEN_CPU_DESC cd; -{ - int count = cd->macro_insn_table.num_init_entries; - CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; - - for ( ; rt_insns != NULL; rt_insns = rt_insns->next) - ++count; - - return count; -} - -/* Cover function to read and properly byteswap an insn value. */ - -CGEN_INSN_INT -cgen_get_insn_value (cd, buf, length) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; -{ - CGEN_INSN_INT value; - - switch (length) - { - case 8: - value = *buf; - break; - case 16: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - value = bfd_getb16 (buf); - else - value = bfd_getl16 (buf); - break; - case 32: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - value = bfd_getb32 (buf); - else - value = bfd_getl32 (buf); - break; - default: - abort (); - } - - return value; -} - -/* Cover function to store an insn value properly byteswapped. */ - -void -cgen_put_insn_value (cd, buf, length, value) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; - CGEN_INSN_INT value; -{ - switch (length) - { - case 8: - buf[0] = value; - break; - case 16: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - bfd_putb16 (value, buf); - else - bfd_putl16 (value, buf); - break; - case 32: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - bfd_putb32 (value, buf); - else - bfd_putl32 (value, buf); - break; - default: - abort (); - } -} - -/* Look up instruction INSN_*_VALUE and extract its fields. - INSN_INT_VALUE is used if CGEN_INT_INSN_P. - Otherwise INSN_BYTES_VALUE is used. - INSN, if non-null, is the insn table entry. - Otherwise INSN_*_VALUE is examined to compute it. - LENGTH is the bit length of INSN_*_VALUE if known, otherwise 0. - 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. - If INSN != NULL, LENGTH must be valid. - ALIAS_P is non-zero if alias insns are to be included in the search. - - The result is a pointer to the insn table entry, or NULL if the instruction - wasn't recognized. */ - -/* ??? Will need to be revisited for VLIW architectures. */ - -const CGEN_INSN * -cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, - alias_p) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - CGEN_FIELDS *fields; - int alias_p; -{ - unsigned char *buf; - CGEN_INSN_INT base_insn; - CGEN_EXTRACT_INFO ex_info; - CGEN_EXTRACT_INFO *info; - - if (cd->int_insn_p) - { - info = NULL; - buf = (unsigned char *) alloca (cd->max_insn_bitsize / 8); - cgen_put_insn_value (cd, buf, length, insn_int_value); - base_insn = insn_int_value; - } - else - { - info = &ex_info; - ex_info.dis_info = NULL; - ex_info.insn_bytes = insn_bytes_value; - ex_info.valid = -1; - buf = insn_bytes_value; - base_insn = cgen_get_insn_value (cd, buf, length); - } - - if (!insn) - { - const CGEN_INSN_LIST *insn_list; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = cgen_dis_lookup_insn (cd, buf, base_insn); - while (insn_list != NULL) - { - insn = insn_list->insn; - - if (alias_p - /* FIXME: Ensure ALIAS attribute always has same index. */ - || ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) - { - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the - extract handler. */ - if ((base_insn & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* ??? 0 is passed for `pc' */ - int elength = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, info, base_insn, fields, (bfd_vma) 0); - if (elength > 0) - { - /* sanity check */ - if (length != 0 && length != elength) - abort (); - return insn; - } - } - } - - insn_list = insn_list->next; - } - } - else - { - /* Sanity check: can't pass an alias insn if ! alias_p. */ - if (! alias_p - && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) - abort (); - /* Sanity check: length must be correct. */ - if (length != CGEN_INSN_BITSIZE (insn)) - abort (); - - /* ??? 0 is passed for `pc' */ - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, info, base_insn, fields, (bfd_vma) 0); - /* Sanity check: must succeed. - Could relax this later if it ever proves useful. */ - if (length == 0) - abort (); - return insn; - } - - return NULL; -} - -/* Fill in the operand instances used by INSN whose operands are FIELDS. - INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled - in. */ - -void -cgen_get_insn_operands (cd, insn, fields, indices) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const CGEN_FIELDS *fields; - int *indices; -{ - const CGEN_OPINST *opinst; - int i; - - if (insn->opinst == NULL) - abort (); - for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst) - { - enum cgen_operand_type op_type = opinst->op_type; - if (op_type == CGEN_OPERAND_NIL) - indices[i] = opinst->index; - else - indices[i] = (*cd->get_int_operand) (cd, op_type, fields); - } -} - -/* Cover function to cgen_get_insn_operands when either INSN or FIELDS - isn't known. - The INSN, INSN_*_VALUE, and LENGTH arguments are passed to - cgen_lookup_insn unchanged. - INSN_INT_VALUE is used if CGEN_INT_INSN_P. - Otherwise INSN_BYTES_VALUE is used. - - The result is the insn table entry or NULL if the instruction wasn't - recognized. */ - -const CGEN_INSN * -cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, - length, indices, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - int *indices; - CGEN_FIELDS *fields; -{ - /* Pass non-zero for ALIAS_P only if INSN != NULL. - If INSN == NULL, we want a real insn. */ - insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, - length, fields, insn != NULL); - if (! insn) - return NULL; - - cgen_get_insn_operands (cd, insn, fields, indices); - return insn; -} - -/* Allow signed overflow of instruction fields. */ -void -cgen_set_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; -{ - cd->signed_overflow_ok_p = 1; -} - -/* Generate an error message if a signed field in an instruction overflows. */ -void -cgen_clear_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; -{ - cd->signed_overflow_ok_p = 0; -} - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -unsigned int -cgen_signed_overflow_ok_p (cd) - CGEN_CPU_DESC cd; -{ - return cd->signed_overflow_ok_p; -} diff --git a/contrib/binutils/opcodes/config.in b/contrib/binutils/opcodes/config.in deleted file mode 100644 index c60a32101aeae..0000000000000 --- a/contrib/binutils/opcodes/config.in +++ /dev/null @@ -1,135 +0,0 @@ -/* config.in. Generated automatically from configure.in by autoheader. */ - -/* Define if using alloca.c. */ -#undef C_ALLOCA - -/* Define to empty if the keyword does not work. */ -#undef const - -/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. - This function is required for alloca.c support on those systems. */ -#undef CRAY_STACKSEG_END - -/* Define if you have alloca, as a function or macro. */ -#undef HAVE_ALLOCA - -/* Define if you have <alloca.h> and it should be used (not on Ultrix). */ -#undef HAVE_ALLOCA_H - -/* Define if you have a working `mmap' system call. */ -#undef HAVE_MMAP - -/* Define as __inline if that's what the C compiler calls it. */ -#undef inline - -/* Define to `long' if <sys/types.h> doesn't define. */ -#undef off_t - -/* Define if you need to in order for stat and other things to work. */ -#undef _POSIX_SOURCE - -/* Define to `unsigned' if <sys/types.h> doesn't define. */ -#undef size_t - -/* If using the C implementation of alloca, define if you know the - direction of stack growth for your system; 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Generated automatically by configure. */" > conftest.h - cat conftest.in >> conftest.h - rm -f conftest.in - if cmp -s $ac_file conftest.h 2>/dev/null; then - echo "$ac_file is unchanged" - rm -f conftest.h - else - # Remove last slash and all that follows it. Not all systems have dirname. - ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` - if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then - # The file is in a subdirectory. - test ! -d "$ac_dir" && mkdir "$ac_dir" - fi - rm -f $ac_file - mv conftest.h $ac_file - fi -fi; done - -EOF -cat >> $CONFIG_STATUS <<EOF - - -EOF -cat >> $CONFIG_STATUS <<\EOF -test -z "$CONFIG_HEADERS" || echo timestamp > stamp-h -sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile -exit 0 -EOF -chmod +x $CONFIG_STATUS -rm -fr confdefs* $ac_clean_files -test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 - diff --git a/contrib/binutils/opcodes/configure.in b/contrib/binutils/opcodes/configure.in deleted file mode 100644 index 6ef461f9a4985..0000000000000 --- a/contrib/binutils/opcodes/configure.in +++ /dev/null @@ -1,214 +0,0 @@ -dnl Process this file with autoconf to produce a configure script. -dnl - -AC_PREREQ(2.13) -AC_INIT(z8k-dis.c) - -AC_CANONICAL_SYSTEM -AC_ISC_POSIX - -# We currently only use the version number for the name of any shared -# library. For user convenience, we always use the same version -# number that BFD is using. -changequote(,)dnl -BFD_VERSION=`grep INIT_AUTOMAKE ${srcdir}/../bfd/configure.in | sed -n -e 's/[ ]//g' -e 's/^.*,\(.*\)).*$/\1/p'` -changequote([,])dnl - -AM_INIT_AUTOMAKE(opcodes, ${BFD_VERSION}) - -dnl These must be called before AM_PROG_LIBTOOL, because it may want -dnl to call AC_CHECK_PROG. -AC_CHECK_TOOL(AR, ar) -AC_CHECK_TOOL(RANLIB, ranlib, :) - -dnl Default to a non shared library. This may be overridden by the -dnl configure option --enable-shared. -AM_DISABLE_SHARED - -AM_PROG_LIBTOOL - -AC_ARG_ENABLE(targets, -[ --enable-targets alternative target configurations], -[case "${enableval}" in - yes | "") AC_ERROR(enable-targets option must specify target names or 'all') - ;; - no) enable_targets= ;; - *) enable_targets=$enableval ;; -esac])dnl -AC_ARG_ENABLE(commonbfdlib, -[ --enable-commonbfdlib build shared BFD/opcodes/libiberty library], -[case "${enableval}" in - yes) commonbfdlib=true ;; - no) commonbfdlib=false ;; - *) AC_MSG_ERROR([bad value ${enableval} for opcodes commonbfdlib option]) ;; -esac])dnl - -AM_CONFIG_HEADER(config.h:config.in) - -if test -z "$target" ; then - AC_MSG_ERROR(Unrecognized target system type; please check config.sub.) -fi -AC_ARG_PROGRAM - -AM_MAINTAINER_MODE -AC_EXEEXT - -# host-specific stuff: - -AC_PROG_CC - -ALL_LINGUAS= -CY_GNU_GETTEXT - -. ${srcdir}/../bfd/configure.host - -AC_SUBST(HDEFINES) -AC_PROG_INSTALL - -AC_CHECK_HEADERS(string.h strings.h stdlib.h) - - -using_cgen=no - -# Horrible hacks to build DLLs on Windows. -WIN32LDFLAGS= -WIN32LIBADD= -case "${host}" in -*-*-cygwin*) - if test "$enable_shared" = "yes"; then - WIN32LDFLAGS="-no-undefined" - WIN32LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" - fi - ;; -esac -AC_SUBST(WIN32LDFLAGS) -AC_SUBST(WIN32LIBADD) - -# target-specific stuff: - -# Canonicalize the secondary target names. -if test -n "$enable_targets" ; then - for targ in `echo $enable_targets | sed 's/,/ /g'` - do - result=`$ac_config_sub $targ 2>/dev/null` - if test -n "$result" ; then - canon_targets="$canon_targets $result" - else - # Allow targets that config.sub doesn't recognize, like "all". - canon_targets="$canon_targets $targ" - fi - done -fi - -all_targets=false -selarchs= -for targ in $target $canon_targets -do - if test "x$targ" = "xall" ; then - all_targets=true - else - . $srcdir/../bfd/config.bfd - selarchs="$selarchs $targ_archs" - fi -done - -# Utility var, documents generic cgen support files. - -cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo" - -# We don't do any links based on the target system, just makefile config. - -if test x${all_targets} = xfalse ; then - - # Target architecture .o files. - ta= - - for arch in $selarchs - do - ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` - archdefs="$archdefs -DARCH_$ad" - case "$arch" in - bfd_a29k_arch) ta="$ta a29k-dis.lo" ;; - bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo" ;; - bfd_arm_arch) ta="$ta arm-dis.lo" ;; - bfd_avr_arch) ta="$ta avr-dis.lo" ;; - bfd_convex_arch) ;; - bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; - bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; - bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; - bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; - bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; - bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; - bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; - bfd_i386_arch) ta="$ta i386-dis.lo" ;; - bfd_i860_arch) ;; - bfd_i960_arch) ta="$ta i960-dis.lo" ;; - bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; - bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; - bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; - bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; - bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; - bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; - bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; - bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; - bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; - bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_pyramid_arch) ;; - bfd_romp_arch) ;; - bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_sh_arch) ta="$ta sh-dis.lo" ;; - bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; - bfd_tahoe_arch) ;; - bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; - bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_vax_arch) ta="$ta vax-dis.lo" ;; - bfd_w65_arch) ta="$ta w65-dis.lo" ;; - bfd_we32k_arch) ;; - bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; - - "") ;; - *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; - esac - done - - if test $using_cgen = yes ; then - ta="$ta $cgen_files" - fi - - # Weed out duplicate .o files. - f="" - for i in $ta ; do - case " $f " in - *" $i "*) ;; - *) f="$f $i" ;; - esac - done - ta="$f" - - # And duplicate -D flags. - f="" - for i in $archdefs ; do - case " $f " in - *" $i "*) ;; - *) f="$f $i" ;; - esac - done - archdefs="$f" - - BFD_MACHINES="$ta" - -else # all_targets is true - archdefs=-DARCH_all - BFD_MACHINES='$(ALL_MACHINES)' -fi - -AC_SUBST(archdefs) -AC_SUBST(BFD_MACHINES) - -AC_OUTPUT(Makefile po/Makefile.in:po/Make-in, -[sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile]) diff --git a/contrib/binutils/opcodes/dep-in.sed b/contrib/binutils/opcodes/dep-in.sed deleted file mode 100644 index c30dee563915c..0000000000000 --- a/contrib/binutils/opcodes/dep-in.sed +++ /dev/null @@ -1,20 +0,0 @@ -:loop -/\\$/N -s/\\\n */ /g -t loop - -s!\.o:!.lo:! -s! @BFD_H@! $(BFD_H)!g -s!@INCDIR@!$(INCDIR)!g -s!@BFDDIR@!$(BFDDIR)!g -s!@SRCDIR@/!!g - -s/\\\n */ /g - -s/ *$// -s/ */ /g -s/ *:/:/g -/:$/d - -s/\(.\{50\}[^ ]*\) /\1 \\\ - /g diff --git a/contrib/binutils/opcodes/dis-buf.c b/contrib/binutils/opcodes/dis-buf.c deleted file mode 100644 index b828206d43f65..0000000000000 --- a/contrib/binutils/opcodes/dis-buf.c +++ /dev/null @@ -1,113 +0,0 @@ -/* Disassemble from a buffer, for GNU. - Copyright (C) 1993, 1994, 1998, 1999 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include <errno.h> -#include "opintl.h" - -/* Get LENGTH bytes from info's buffer, at target address memaddr. - Transfer them to myaddr. */ -int -buffer_read_memory (memaddr, myaddr, length, info) - bfd_vma memaddr; - bfd_byte *myaddr; - unsigned int length; - struct disassemble_info *info; -{ - unsigned int opb = info->octets_per_byte; - unsigned int end_addr_offset = length / opb; - unsigned int max_addr_offset = info->buffer_length / opb; - unsigned int octets = (memaddr - info->buffer_vma) * opb; - - if (memaddr < info->buffer_vma - || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset) - /* Out of bounds. Use EIO because GDB uses it. */ - return EIO; - memcpy (myaddr, info->buffer + octets, length); - - return 0; -} - -/* Print an error message. We can assume that this is in response to - an error return from buffer_read_memory. */ -void -perror_memory (status, memaddr, info) - int status; - bfd_vma memaddr; - struct disassemble_info *info; -{ - if (status != EIO) - /* Can't happen. */ - info->fprintf_func (info->stream, _("Unknown error %d\n"), status); - else - /* Actually, address between memaddr and memaddr + len was - out of bounds. */ - info->fprintf_func (info->stream, - _("Address 0x%x is out of bounds.\n"), memaddr); -} - -/* This could be in a separate file, to save miniscule amounts of space - in statically linked executables. */ - -/* Just print the address is hex. This is included for completeness even - though both GDB and objdump provide their own (to print symbolic - addresses). */ - -void -generic_print_address (addr, info) - bfd_vma addr; - struct disassemble_info *info; -{ - char buf[30]; - - sprintf_vma (buf, addr); - (*info->fprintf_func) (info->stream, "0x%s", buf); -} - -/* Just concatenate the address as hex. This is included for - completeness even though both GDB and objdump provide their own (to - print symbolic addresses). */ - -void -generic_strcat_address (addr, buf, len) - bfd_vma addr; - char *buf; - int len; -{ - if (buf != (char *)NULL && len > 0) - { - char tmpBuf[30]; - - sprintf_vma (tmpBuf, addr); - if ((strlen (buf) + strlen (tmpBuf)) <= (unsigned int) len) - strcat (buf, tmpBuf); - else - strncat (buf, tmpBuf, (len - strlen(buf))); - } - return; -} - -/* Just return the given address. */ - -int -generic_symbol_at_address (addr, info) - bfd_vma addr ATTRIBUTE_UNUSED; - struct disassemble_info *info ATTRIBUTE_UNUSED; -{ - return 1; -} diff --git a/contrib/binutils/opcodes/disassemble.c b/contrib/binutils/opcodes/disassemble.c deleted file mode 100644 index 373b6526cb153..0000000000000 --- a/contrib/binutils/opcodes/disassemble.c +++ /dev/null @@ -1,277 +0,0 @@ -/* Select disassembly routine for specified architecture. - Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 - Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" - -#ifdef ARCH_all -#define ARCH_a29k -#define ARCH_alpha -#define ARCH_arc -#define ARCH_arm -#define ARCH_avr -#define ARCH_d10v -#define ARCH_d30v -#define ARCH_h8300 -#define ARCH_h8500 -#define ARCH_hppa -#define ARCH_i370 -#define ARCH_i386 -#define ARCH_i960 -#define ARCH_fr30 -#define ARCH_m32r -#define ARCH_m68k -#define ARCH_m88k -#define ARCH_mcore -#define ARCH_mips -#define ARCH_mn10200 -#define ARCH_mn10300 -#define ARCH_ns32k -#define ARCH_pj -#define ARCH_powerpc -#define ARCH_rs6000 -#define ARCH_sh -#define ARCH_sparc -#define ARCH_tic30 -#define ARCH_tic80 -#define ARCH_v850 -#define ARCH_vax -#define ARCH_w65 -#define ARCH_z8k -#endif - - -disassembler_ftype -disassembler (abfd) - bfd *abfd; -{ - enum bfd_architecture a = bfd_get_arch (abfd); - disassembler_ftype disassemble; - - switch (a) - { - /* If you add a case to this table, also add it to the - ARCH_all definition right above this function. */ -#ifdef ARCH_a29k - case bfd_arch_a29k: - /* As far as I know we only handle big-endian 29k objects. */ - disassemble = print_insn_big_a29k; - break; -#endif -#ifdef ARCH_alpha - case bfd_arch_alpha: - disassemble = print_insn_alpha; - break; -#endif -#ifdef ARCH_arc - case bfd_arch_arc: - { - disassemble = arc_get_disassembler (bfd_get_mach (abfd), - bfd_big_endian (abfd)); - break; - } -#endif -#ifdef ARCH_arm - case bfd_arch_arm: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_arm; - else - disassemble = print_insn_little_arm; - break; -#endif -#ifdef ARCH_avr - case bfd_arch_avr: - disassemble = print_insn_avr; - break; -#endif -#ifdef ARCH_d10v - case bfd_arch_d10v: - disassemble = print_insn_d10v; - break; -#endif -#ifdef ARCH_d30v - case bfd_arch_d30v: - disassemble = print_insn_d30v; - break; -#endif -#ifdef ARCH_h8300 - case bfd_arch_h8300: - if (bfd_get_mach(abfd) == bfd_mach_h8300h) - disassemble = print_insn_h8300h; - else if (bfd_get_mach(abfd) == bfd_mach_h8300s) - disassemble = print_insn_h8300s; - else - disassemble = print_insn_h8300; - break; -#endif -#ifdef ARCH_h8500 - case bfd_arch_h8500: - disassemble = print_insn_h8500; - break; -#endif -#ifdef ARCH_hppa - case bfd_arch_hppa: - disassemble = print_insn_hppa; - break; -#endif -#ifdef ARCH_i370 - case bfd_arch_i370: - disassemble = print_insn_i370; - break; -#endif -#ifdef ARCH_i386 - case bfd_arch_i386: - if (bfd_get_mach (abfd) == bfd_mach_i386_i386_intel_syntax) - disassemble = print_insn_i386_intel; - else - disassemble = print_insn_i386_att; - break; -#endif -#ifdef ARCH_i960 - case bfd_arch_i960: - disassemble = print_insn_i960; - break; -#endif -#ifdef ARCH_fr30 - case bfd_arch_fr30: - disassemble = print_insn_fr30; - break; -#endif -#ifdef ARCH_m32r - case bfd_arch_m32r: - disassemble = print_insn_m32r; - break; -#endif -#ifdef ARCH_m68k - case bfd_arch_m68k: - disassemble = print_insn_m68k; - break; -#endif -#ifdef ARCH_m88k - case bfd_arch_m88k: - disassemble = print_insn_m88k; - break; -#endif -#ifdef ARCH_ns32k - case bfd_arch_ns32k: - disassemble = print_insn_ns32k; - break; -#endif -#ifdef ARCH_mcore - case bfd_arch_mcore: - disassemble = print_insn_mcore; - break; -#endif -#ifdef ARCH_mips - case bfd_arch_mips: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_mips; - else - disassemble = print_insn_little_mips; - break; -#endif -#ifdef ARCH_mn10200 - case bfd_arch_mn10200: - disassemble = print_insn_mn10200; - break; -#endif -#ifdef ARCH_mn10300 - case bfd_arch_mn10300: - disassemble = print_insn_mn10300; - break; -#endif -#ifdef ARCH_pj - case bfd_arch_pj: - disassemble = print_insn_pj; - break; -#endif -#ifdef ARCH_powerpc - case bfd_arch_powerpc: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_powerpc; - else - disassemble = print_insn_little_powerpc; - break; -#endif -#ifdef ARCH_rs6000 - case bfd_arch_rs6000: - disassemble = print_insn_rs6000; - break; -#endif -#ifdef ARCH_sh - case bfd_arch_sh: - if (bfd_big_endian (abfd)) - disassemble = print_insn_sh; - else - disassemble = print_insn_shl; - break; -#endif -#ifdef ARCH_sparc - case bfd_arch_sparc: - disassemble = print_insn_sparc; - break; -#endif -#ifdef ARCH_tic30 - case bfd_arch_tic30: - disassemble = print_insn_tic30; - break; -#endif -#ifdef ARCH_tic80 - case bfd_arch_tic80: - disassemble = print_insn_tic80; - break; -#endif -#ifdef ARCH_v850 - case bfd_arch_v850: - disassemble = print_insn_v850; - break; -#endif -#ifdef ARCH_w65 - case bfd_arch_w65: - disassemble = print_insn_w65; - break; -#endif -#ifdef ARCH_z8k - case bfd_arch_z8k: - if (bfd_get_mach(abfd) == bfd_mach_z8001) - disassemble = print_insn_z8001; - else - disassemble = print_insn_z8002; - break; -#endif -#ifdef ARCH_vax - case bfd_arch_vax: - disassemble = print_insn_vax; - break; -#endif - default: - return 0; - } - return disassemble; -} - -void -disassembler_usage (stream) - FILE *stream ATTRIBUTE_UNUSED; -{ -#ifdef ARCH_arm - print_arm_disassembler_options (stream); -#endif - - return; -} diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c deleted file mode 100644 index a75d6e316c3b2..0000000000000 --- a/contrib/binutils/opcodes/i386-dis.c +++ /dev/null @@ -1,3759 +0,0 @@ -/* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988, 89, 91, 93, 94, 95, 96, 97, 98, 1999 - Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* - * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) - * July 1988 - * modified by John Hassey (hassey@dg-rtp.dg.com) - */ - -/* - * The main tables describing the instructions is essentially a copy - * of the "Opcode Map" chapter (Appendix A) of the Intel 80386 - * Programmers Manual. Usually, there is a capital letter, followed - * by a small letter. The capital letter tell the addressing mode, - * and the small letter tells about the operand size. Refer to - * the Intel manual for details. - */ - -#include "dis-asm.h" -#include "sysdep.h" -#include "opintl.h" - -#define MAXLEN 20 - -#include <setjmp.h> - -#ifndef UNIXWARE_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes. */ -#define UNIXWARE_COMPAT 1 -#endif - -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); - -struct dis_private -{ - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - jmp_buf bailout; -}; - -/* The opcode for the fwait instruction, which we treat as a prefix - when we can. */ -#define FWAIT_OPCODE (0x9b) - -/* Flags for the prefixes for the current instruction. See below. */ -static int prefixes; - -/* Flags for prefixes which we somehow handled when printing the - current instruction. */ -static int used_prefixes; - -/* Flags stored in PREFIXES. */ -#define PREFIX_REPZ 1 -#define PREFIX_REPNZ 2 -#define PREFIX_LOCK 4 -#define PREFIX_CS 8 -#define PREFIX_SS 0x10 -#define PREFIX_DS 0x20 -#define PREFIX_ES 0x40 -#define PREFIX_FS 0x80 -#define PREFIX_GS 0x100 -#define PREFIX_DATA 0x200 -#define PREFIX_ADDR 0x400 -#define PREFIX_FWAIT 0x800 - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; -{ - int status; - struct dis_private *priv = (struct dis_private *)info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - /* If we did manage to read at least one byte, then - print_insn_i386 will do something sensible. Otherwise, print - an error. We do that here because this is where we know - STATUS. */ - if (priv->max_fetched == priv->the_buffer) - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - else - priv->max_fetched = addr; - return 1; -} - -#define XX NULL, 0 - -#define Eb OP_E, b_mode -#define indirEb OP_indirE, b_mode -#define Gb OP_G, b_mode -#define Ev OP_E, v_mode -#define Ed OP_E, d_mode -#define indirEv OP_indirE, v_mode -#define Ew OP_E, w_mode -#define Ma OP_E, v_mode -#define M OP_E, 0 /* lea */ -#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ -#define Gv OP_G, v_mode -#define Gw OP_G, w_mode -#define Rd OP_Rd, d_mode -#define Ib OP_I, b_mode -#define sIb OP_sI, b_mode /* sign extened byte */ -#define Iv OP_I, v_mode -#define Iw OP_I, w_mode -#define Jb OP_J, b_mode -#define Jv OP_J, v_mode -#define Cd OP_C, d_mode -#define Dd OP_D, d_mode -#define Td OP_T, d_mode - -#define eAX OP_REG, eAX_reg -#define eBX OP_REG, eBX_reg -#define eCX OP_REG, eCX_reg -#define eDX OP_REG, eDX_reg -#define eSP OP_REG, eSP_reg -#define eBP OP_REG, eBP_reg -#define eSI OP_REG, eSI_reg -#define eDI OP_REG, eDI_reg -#define AL OP_REG, al_reg -#define CL OP_REG, cl_reg -#define DL OP_REG, dl_reg -#define BL OP_REG, bl_reg -#define AH OP_REG, ah_reg -#define CH OP_REG, ch_reg -#define DH OP_REG, dh_reg -#define BH OP_REG, bh_reg -#define AX OP_REG, ax_reg -#define DX OP_REG, dx_reg -#define indirDX OP_REG, indir_dx_reg - -#define Sw OP_SEG, w_mode -#define Ap OP_DIR, 0 -#define Ob OP_OFF, b_mode -#define Ov OP_OFF, v_mode -#define Xb OP_DSreg, eSI_reg -#define Xv OP_DSreg, eSI_reg -#define Yb OP_ESreg, eDI_reg -#define Yv OP_ESreg, eDI_reg -#define DSBX OP_DSreg, eBX_reg - -#define es OP_REG, es_reg -#define ss OP_REG, ss_reg -#define cs OP_REG, cs_reg -#define ds OP_REG, ds_reg -#define fs OP_REG, fs_reg -#define gs OP_REG, gs_reg - -#define MX OP_MMX, 0 -#define XM OP_XMM, 0 -#define EM OP_EM, v_mode -#define EX OP_EX, v_mode -#define MS OP_MS, v_mode -#define None OP_E, 0 -#define OPSUF OP_3DNowSuffix, 0 -#define OPSIMD OP_SIMD_Suffix, 0 - -/* bits in sizeflag */ -#if 0 /* leave undefined until someone adds the extra flag to objdump */ -#define SUFFIX_ALWAYS 4 -#endif -#define AFLAG 2 -#define DFLAG 1 - -typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag)); - -static void OP_E PARAMS ((int, int)); -static void OP_G PARAMS ((int, int)); -static void OP_I PARAMS ((int, int)); -static void OP_indirE PARAMS ((int, int)); -static void OP_sI PARAMS ((int, int)); -static void OP_REG PARAMS ((int, int)); -static void OP_J PARAMS ((int, int)); -static void OP_DIR PARAMS ((int, int)); -static void OP_OFF PARAMS ((int, int)); -static void OP_ESreg PARAMS ((int, int)); -static void OP_DSreg PARAMS ((int, int)); -static void OP_SEG PARAMS ((int, int)); -static void OP_C PARAMS ((int, int)); -static void OP_D PARAMS ((int, int)); -static void OP_T PARAMS ((int, int)); -static void OP_Rd PARAMS ((int, int)); -static void OP_ST PARAMS ((int, int)); -static void OP_STi PARAMS ((int, int)); -static void OP_MMX PARAMS ((int, int)); -static void OP_XMM PARAMS ((int, int)); -static void OP_EM PARAMS ((int, int)); -static void OP_EX PARAMS ((int, int)); -static void OP_MS PARAMS ((int, int)); -static void OP_3DNowSuffix PARAMS ((int, int)); -static void OP_SIMD_Suffix PARAMS ((int, int)); -static void SIMD_Fixup PARAMS ((int, int)); - -static void append_seg PARAMS ((void)); -static void set_op PARAMS ((unsigned int op)); -static void putop PARAMS ((const char *template, int sizeflag)); -static void dofloat PARAMS ((int sizeflag)); -static int get16 PARAMS ((void)); -static int get32 PARAMS ((void)); -static void ckprefix PARAMS ((void)); -static const char *prefix_name PARAMS ((int, int)); -static void ptr_reg PARAMS ((int, int)); -static void BadOp PARAMS ((void)); - -#define b_mode 1 -#define v_mode 2 -#define w_mode 3 -#define d_mode 4 -#define x_mode 5 - -#define es_reg 100 -#define cs_reg 101 -#define ss_reg 102 -#define ds_reg 103 -#define fs_reg 104 -#define gs_reg 105 - -#define eAX_reg 108 -#define eCX_reg 109 -#define eDX_reg 110 -#define eBX_reg 111 -#define eSP_reg 112 -#define eBP_reg 113 -#define eSI_reg 114 -#define eDI_reg 115 - -#define al_reg 116 -#define cl_reg 117 -#define dl_reg 118 -#define bl_reg 119 -#define ah_reg 120 -#define ch_reg 121 -#define dh_reg 122 -#define bh_reg 123 - -#define ax_reg 124 -#define cx_reg 125 -#define dx_reg 126 -#define bx_reg 127 -#define sp_reg 128 -#define bp_reg 129 -#define si_reg 130 -#define di_reg 131 - -#define indir_dx_reg 150 - -#define USE_GROUPS 1 -#define USE_PREFIX_USER_TABLE 2 - -#define GRP1b NULL, NULL, 0, NULL, USE_GROUPS, NULL, 0 -#define GRP1S NULL, NULL, 1, NULL, USE_GROUPS, NULL, 0 -#define GRP1Ss NULL, NULL, 2, NULL, USE_GROUPS, NULL, 0 -#define GRP2b NULL, NULL, 3, NULL, USE_GROUPS, NULL, 0 -#define GRP2S NULL, NULL, 4, NULL, USE_GROUPS, NULL, 0 -#define GRP2b_one NULL, NULL, 5, NULL, USE_GROUPS, NULL, 0 -#define GRP2S_one NULL, NULL, 6, NULL, USE_GROUPS, NULL, 0 -#define GRP2b_cl NULL, NULL, 7, NULL, USE_GROUPS, NULL, 0 -#define GRP2S_cl NULL, NULL, 8, NULL, USE_GROUPS, NULL, 0 -#define GRP3b NULL, NULL, 9, NULL, USE_GROUPS, NULL, 0 -#define GRP3S NULL, NULL, 10, NULL, USE_GROUPS, NULL, 0 -#define GRP4 NULL, NULL, 11, NULL, USE_GROUPS, NULL, 0 -#define GRP5 NULL, NULL, 12, NULL, USE_GROUPS, NULL, 0 -#define GRP6 NULL, NULL, 13, NULL, USE_GROUPS, NULL, 0 -#define GRP7 NULL, NULL, 14, NULL, USE_GROUPS, NULL, 0 -#define GRP8 NULL, NULL, 15, NULL, USE_GROUPS, NULL, 0 -#define GRP9 NULL, NULL, 16, NULL, USE_GROUPS, NULL, 0 -#define GRP10 NULL, NULL, 17, NULL, USE_GROUPS, NULL, 0 -#define GRP11 NULL, NULL, 18, NULL, USE_GROUPS, NULL, 0 -#define GRP12 NULL, NULL, 19, NULL, USE_GROUPS, NULL, 0 -#define GRP13 NULL, NULL, 20, NULL, USE_GROUPS, NULL, 0 -#define GRP14 NULL, NULL, 21, NULL, USE_GROUPS, NULL, 0 -#define GRPAMD NULL, NULL, 22, NULL, USE_GROUPS, NULL, 0 - -#define PREGRP0 NULL, NULL, 0, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP1 NULL, NULL, 1, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP2 NULL, NULL, 2, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP3 NULL, NULL, 3, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP4 NULL, NULL, 4, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP5 NULL, NULL, 5, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP6 NULL, NULL, 6, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP7 NULL, NULL, 7, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP8 NULL, NULL, 8, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP9 NULL, NULL, 9, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP10 NULL, NULL, 10, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP11 NULL, NULL, 11, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP12 NULL, NULL, 12, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP13 NULL, NULL, 13, NULL, USE_PREFIX_USER_TABLE, NULL, 0 -#define PREGRP14 NULL, NULL, 14, NULL, USE_PREFIX_USER_TABLE, NULL, 0 - -#define FLOATCODE 50 -#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0 - -struct dis386 { - const char *name; - op_rtn op1; - int bytemode1; - op_rtn op2; - int bytemode2; - op_rtn op3; - int bytemode3; -}; - -/* Upper case letters in the instruction names here are macros. - 'A' => print 'b' if no register operands or suffix_always is true - 'B' => print 'b' if suffix_always is true - 'E' => print 'e' if 32-bit form of jcxz - 'L' => print 'l' if suffix_always is true - 'N' => print 'n' if instruction has no wait "prefix" - 'P' => print 'w' or 'l' if instruction has an operand size prefix, - or suffix_always is true - 'Q' => print 'w' or 'l' if no register operands or suffix_always is true - 'R' => print 'w' or 'l' ("wd" or "dq" in intel mode) - 'S' => print 'w' or 'l' if suffix_always is true - 'W' => print 'b' or 'w' ("w" or "de" in intel mode) -*/ - -static const struct dis386 dis386_att[] = { - /* 00 */ - { "addB", Eb, Gb, XX }, - { "addS", Ev, Gv, XX }, - { "addB", Gb, Eb, XX }, - { "addS", Gv, Ev, XX }, - { "addB", AL, Ib, XX }, - { "addS", eAX, Iv, XX }, - { "pushP", es, XX, XX }, - { "popP", es, XX, XX }, - /* 08 */ - { "orB", Eb, Gb, XX }, - { "orS", Ev, Gv, XX }, - { "orB", Gb, Eb, XX }, - { "orS", Gv, Ev, XX }, - { "orB", AL, Ib, XX }, - { "orS", eAX, Iv, XX }, - { "pushP", cs, XX, XX }, - { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */ - /* 10 */ - { "adcB", Eb, Gb, XX }, - { "adcS", Ev, Gv, XX }, - { "adcB", Gb, Eb, XX }, - { "adcS", Gv, Ev, XX }, - { "adcB", AL, Ib, XX }, - { "adcS", eAX, Iv, XX }, - { "pushP", ss, XX, XX }, - { "popP", ss, XX, XX }, - /* 18 */ - { "sbbB", Eb, Gb, XX }, - { "sbbS", Ev, Gv, XX }, - { "sbbB", Gb, Eb, XX }, - { "sbbS", Gv, Ev, XX }, - { "sbbB", AL, Ib, XX }, - { "sbbS", eAX, Iv, XX }, - { "pushP", ds, XX, XX }, - { "popP", ds, XX, XX }, - /* 20 */ - { "andB", Eb, Gb, XX }, - { "andS", Ev, Gv, XX }, - { "andB", Gb, Eb, XX }, - { "andS", Gv, Ev, XX }, - { "andB", AL, Ib, XX }, - { "andS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG ES prefix */ - { "daa", XX, XX, XX }, - /* 28 */ - { "subB", Eb, Gb, XX }, - { "subS", Ev, Gv, XX }, - { "subB", Gb, Eb, XX }, - { "subS", Gv, Ev, XX }, - { "subB", AL, Ib, XX }, - { "subS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG CS prefix */ - { "das", XX, XX, XX }, - /* 30 */ - { "xorB", Eb, Gb, XX }, - { "xorS", Ev, Gv, XX }, - { "xorB", Gb, Eb, XX }, - { "xorS", Gv, Ev, XX }, - { "xorB", AL, Ib, XX }, - { "xorS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG SS prefix */ - { "aaa", XX, XX, XX }, - /* 38 */ - { "cmpB", Eb, Gb, XX }, - { "cmpS", Ev, Gv, XX }, - { "cmpB", Gb, Eb, XX }, - { "cmpS", Gv, Ev, XX }, - { "cmpB", AL, Ib, XX }, - { "cmpS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG DS prefix */ - { "aas", XX, XX, XX }, - /* 40 */ - { "incS", eAX, XX, XX }, - { "incS", eCX, XX, XX }, - { "incS", eDX, XX, XX }, - { "incS", eBX, XX, XX }, - { "incS", eSP, XX, XX }, - { "incS", eBP, XX, XX }, - { "incS", eSI, XX, XX }, - { "incS", eDI, XX, XX }, - /* 48 */ - { "decS", eAX, XX, XX }, - { "decS", eCX, XX, XX }, - { "decS", eDX, XX, XX }, - { "decS", eBX, XX, XX }, - { "decS", eSP, XX, XX }, - { "decS", eBP, XX, XX }, - { "decS", eSI, XX, XX }, - { "decS", eDI, XX, XX }, - /* 50 */ - { "pushS", eAX, XX, XX }, - { "pushS", eCX, XX, XX }, - { "pushS", eDX, XX, XX }, - { "pushS", eBX, XX, XX }, - { "pushS", eSP, XX, XX }, - { "pushS", eBP, XX, XX }, - { "pushS", eSI, XX, XX }, - { "pushS", eDI, XX, XX }, - /* 58 */ - { "popS", eAX, XX, XX }, - { "popS", eCX, XX, XX }, - { "popS", eDX, XX, XX }, - { "popS", eBX, XX, XX }, - { "popS", eSP, XX, XX }, - { "popS", eBP, XX, XX }, - { "popS", eSI, XX, XX }, - { "popS", eDI, XX, XX }, - /* 60 */ - { "pushaP", XX, XX, XX }, - { "popaP", XX, XX, XX }, - { "boundS", Gv, Ma, XX }, - { "arpl", Ew, Gw, XX }, - { "(bad)", XX, XX, XX }, /* seg fs */ - { "(bad)", XX, XX, XX }, /* seg gs */ - { "(bad)", XX, XX, XX }, /* op size prefix */ - { "(bad)", XX, XX, XX }, /* adr size prefix */ - /* 68 */ - { "pushP", Iv, XX, XX }, /* 386 book wrong */ - { "imulS", Gv, Ev, Iv }, - { "pushP", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */ - { "imulS", Gv, Ev, sIb }, - { "insb", Yb, indirDX, XX }, - { "insR", Yv, indirDX, XX }, - { "outsb", indirDX, Xb, XX }, - { "outsR", indirDX, Xv, XX }, - /* 70 */ - { "jo", Jb, XX, XX }, - { "jno", Jb, XX, XX }, - { "jb", Jb, XX, XX }, - { "jae", Jb, XX, XX }, - { "je", Jb, XX, XX }, - { "jne", Jb, XX, XX }, - { "jbe", Jb, XX, XX }, - { "ja", Jb, XX, XX }, - /* 78 */ - { "js", Jb, XX, XX }, - { "jns", Jb, XX, XX }, - { "jp", Jb, XX, XX }, - { "jnp", Jb, XX, XX }, - { "jl", Jb, XX, XX }, - { "jge", Jb, XX, XX }, - { "jle", Jb, XX, XX }, - { "jg", Jb, XX, XX }, - /* 80 */ - { GRP1b }, - { GRP1S }, - { "(bad)", XX, XX, XX }, - { GRP1Ss }, - { "testB", Eb, Gb, XX }, - { "testS", Ev, Gv, XX }, - { "xchgB", Eb, Gb, XX }, - { "xchgS", Ev, Gv, XX }, - /* 88 */ - { "movB", Eb, Gb, XX }, - { "movS", Ev, Gv, XX }, - { "movB", Gb, Eb, XX }, - { "movS", Gv, Ev, XX }, - { "movQ", Ev, Sw, XX }, - { "leaS", Gv, M, XX }, - { "movQ", Sw, Ev, XX }, - { "popQ", Ev, XX, XX }, - /* 90 */ - { "nop", XX, XX, XX }, - { "xchgS", eCX, eAX, XX }, - { "xchgS", eDX, eAX, XX }, - { "xchgS", eBX, eAX, XX }, - { "xchgS", eSP, eAX, XX }, - { "xchgS", eBP, eAX, XX }, - { "xchgS", eSI, eAX, XX }, - { "xchgS", eDI, eAX, XX }, - /* 98 */ - { "cWtR", XX, XX, XX }, - { "cRtd", XX, XX, XX }, - { "lcallP", Ap, XX, XX }, - { "(bad)", XX, XX, XX }, /* fwait */ - { "pushfP", XX, XX, XX }, - { "popfP", XX, XX, XX }, - { "sahf", XX, XX, XX }, - { "lahf", XX, XX, XX }, - /* a0 */ - { "movB", AL, Ob, XX }, - { "movS", eAX, Ov, XX }, - { "movB", Ob, AL, XX }, - { "movS", Ov, eAX, XX }, - { "movsb", Yb, Xb, XX }, - { "movsR", Yv, Xv, XX }, - { "cmpsb", Xb, Yb, XX }, - { "cmpsR", Xv, Yv, XX }, - /* a8 */ - { "testB", AL, Ib, XX }, - { "testS", eAX, Iv, XX }, - { "stosB", Yb, AL, XX }, - { "stosS", Yv, eAX, XX }, - { "lodsB", AL, Xb, XX }, - { "lodsS", eAX, Xv, XX }, - { "scasB", AL, Yb, XX }, - { "scasS", eAX, Yv, XX }, - /* b0 */ - { "movB", AL, Ib, XX }, - { "movB", CL, Ib, XX }, - { "movB", DL, Ib, XX }, - { "movB", BL, Ib, XX }, - { "movB", AH, Ib, XX }, - { "movB", CH, Ib, XX }, - { "movB", DH, Ib, XX }, - { "movB", BH, Ib, XX }, - /* b8 */ - { "movS", eAX, Iv, XX }, - { "movS", eCX, Iv, XX }, - { "movS", eDX, Iv, XX }, - { "movS", eBX, Iv, XX }, - { "movS", eSP, Iv, XX }, - { "movS", eBP, Iv, XX }, - { "movS", eSI, Iv, XX }, - { "movS", eDI, Iv, XX }, - /* c0 */ - { GRP2b }, - { GRP2S }, - { "retP", Iw, XX, XX }, - { "retP", XX, XX, XX }, - { "lesS", Gv, Mp, XX }, - { "ldsS", Gv, Mp, XX }, - { "movA", Eb, Ib, XX }, - { "movQ", Ev, Iv, XX }, - /* c8 */ - { "enterP", Iw, Ib, XX }, - { "leaveP", XX, XX, XX }, - { "lretP", Iw, XX, XX }, - { "lretP", XX, XX, XX }, - { "int3", XX, XX, XX }, - { "int", Ib, XX, XX }, - { "into", XX, XX, XX}, - { "iretP", XX, XX, XX }, - /* d0 */ - { GRP2b_one }, - { GRP2S_one }, - { GRP2b_cl }, - { GRP2S_cl }, - { "aam", sIb, XX, XX }, - { "aad", sIb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "xlat", DSBX, XX, XX }, - /* d8 */ - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - /* e0 */ - { "loopne", Jb, XX, XX }, - { "loope", Jb, XX, XX }, - { "loop", Jb, XX, XX }, - { "jEcxz", Jb, XX, XX }, - { "inB", AL, Ib, XX }, - { "inS", eAX, Ib, XX }, - { "outB", Ib, AL, XX }, - { "outS", Ib, eAX, XX }, - /* e8 */ - { "callP", Jv, XX, XX }, - { "jmpP", Jv, XX, XX }, - { "ljmpP", Ap, XX, XX }, - { "jmp", Jb, XX, XX }, - { "inB", AL, indirDX, XX }, - { "inS", eAX, indirDX, XX }, - { "outB", indirDX, AL, XX }, - { "outS", indirDX, eAX, XX }, - /* f0 */ - { "(bad)", XX, XX, XX }, /* lock prefix */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, /* repne */ - { "(bad)", XX, XX, XX }, /* repz */ - { "hlt", XX, XX, XX }, - { "cmc", XX, XX, XX }, - { GRP3b }, - { GRP3S }, - /* f8 */ - { "clc", XX, XX, XX }, - { "stc", XX, XX, XX }, - { "cli", XX, XX, XX }, - { "sti", XX, XX, XX }, - { "cld", XX, XX, XX }, - { "std", XX, XX, XX }, - { GRP4 }, - { GRP5 }, -}; - -static const struct dis386 dis386_intel[] = { - /* 00 */ - { "add", Eb, Gb, XX }, - { "add", Ev, Gv, XX }, - { "add", Gb, Eb, XX }, - { "add", Gv, Ev, XX }, - { "add", AL, Ib, XX }, - { "add", eAX, Iv, XX }, - { "push", es, XX, XX }, - { "pop", es, XX, XX }, - /* 08 */ - { "or", Eb, Gb, XX }, - { "or", Ev, Gv, XX }, - { "or", Gb, Eb, XX }, - { "or", Gv, Ev, XX }, - { "or", AL, Ib, XX }, - { "or", eAX, Iv, XX }, - { "push", cs, XX, XX }, - { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */ - /* 10 */ - { "adc", Eb, Gb, XX }, - { "adc", Ev, Gv, XX }, - { "adc", Gb, Eb, XX }, - { "adc", Gv, Ev, XX }, - { "adc", AL, Ib, XX }, - { "adc", eAX, Iv, XX }, - { "push", ss, XX, XX }, - { "pop", ss, XX, XX }, - /* 18 */ - { "sbb", Eb, Gb, XX }, - { "sbb", Ev, Gv, XX }, - { "sbb", Gb, Eb, XX }, - { "sbb", Gv, Ev, XX }, - { "sbb", AL, Ib, XX }, - { "sbb", eAX, Iv, XX }, - { "push", ds, XX, XX }, - { "pop", ds, XX, XX }, - /* 20 */ - { "and", Eb, Gb, XX }, - { "and", Ev, Gv, XX }, - { "and", Gb, Eb, XX }, - { "and", Gv, Ev, XX }, - { "and", AL, Ib, XX }, - { "and", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG ES prefix */ - { "daa", XX, XX, XX }, - /* 28 */ - { "sub", Eb, Gb, XX }, - { "sub", Ev, Gv, XX }, - { "sub", Gb, Eb, XX }, - { "sub", Gv, Ev, XX }, - { "sub", AL, Ib, XX }, - { "sub", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG CS prefix */ - { "das", XX, XX, XX }, - /* 30 */ - { "xor", Eb, Gb, XX }, - { "xor", Ev, Gv, XX }, - { "xor", Gb, Eb, XX }, - { "xor", Gv, Ev, XX }, - { "xor", AL, Ib, XX }, - { "xor", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG SS prefix */ - { "aaa", XX, XX, XX }, - /* 38 */ - { "cmp", Eb, Gb, XX }, - { "cmp", Ev, Gv, XX }, - { "cmp", Gb, Eb, XX }, - { "cmp", Gv, Ev, XX }, - { "cmp", AL, Ib, XX }, - { "cmp", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG DS prefix */ - { "aas", XX, XX, XX }, - /* 40 */ - { "inc", eAX, XX, XX }, - { "inc", eCX, XX, XX }, - { "inc", eDX, XX, XX }, - { "inc", eBX, XX, XX }, - { "inc", eSP, XX, XX }, - { "inc", eBP, XX, XX }, - { "inc", eSI, XX, XX }, - { "inc", eDI, XX, XX }, - /* 48 */ - { "dec", eAX, XX, XX }, - { "dec", eCX, XX, XX }, - { "dec", eDX, XX, XX }, - { "dec", eBX, XX, XX }, - { "dec", eSP, XX, XX }, - { "dec", eBP, XX, XX }, - { "dec", eSI, XX, XX }, - { "dec", eDI, XX, XX }, - /* 50 */ - { "push", eAX, XX, XX }, - { "push", eCX, XX, XX }, - { "push", eDX, XX, XX }, - { "push", eBX, XX, XX }, - { "push", eSP, XX, XX }, - { "push", eBP, XX, XX }, - { "push", eSI, XX, XX }, - { "push", eDI, XX, XX }, - /* 58 */ - { "pop", eAX, XX, XX }, - { "pop", eCX, XX, XX }, - { "pop", eDX, XX, XX }, - { "pop", eBX, XX, XX }, - { "pop", eSP, XX, XX }, - { "pop", eBP, XX, XX }, - { "pop", eSI, XX, XX }, - { "pop", eDI, XX, XX }, - /* 60 */ - { "pusha", XX, XX, XX }, - { "popa", XX, XX, XX }, - { "bound", Gv, Ma, XX }, - { "arpl", Ew, Gw, XX }, - { "(bad)", XX, XX, XX }, /* seg fs */ - { "(bad)", XX, XX, XX }, /* seg gs */ - { "(bad)", XX, XX, XX }, /* op size prefix */ - { "(bad)", XX, XX, XX }, /* adr size prefix */ - /* 68 */ - { "push", Iv, XX, XX }, /* 386 book wrong */ - { "imul", Gv, Ev, Iv }, - { "push", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */ - { "imul", Gv, Ev, sIb }, - { "ins", Yb, indirDX, XX }, - { "ins", Yv, indirDX, XX }, - { "outs", indirDX, Xb, XX }, - { "outs", indirDX, Xv, XX }, - /* 70 */ - { "jo", Jb, XX, XX }, - { "jno", Jb, XX, XX }, - { "jb", Jb, XX, XX }, - { "jae", Jb, XX, XX }, - { "je", Jb, XX, XX }, - { "jne", Jb, XX, XX }, - { "jbe", Jb, XX, XX }, - { "ja", Jb, XX, XX }, - /* 78 */ - { "js", Jb, XX, XX }, - { "jns", Jb, XX, XX }, - { "jp", Jb, XX, XX }, - { "jnp", Jb, XX, XX }, - { "jl", Jb, XX, XX }, - { "jge", Jb, XX, XX }, - { "jle", Jb, XX, XX }, - { "jg", Jb, XX, XX }, - /* 80 */ - { GRP1b }, - { GRP1S }, - { "(bad)", XX, XX, XX }, - { GRP1Ss }, - { "test", Eb, Gb, XX }, - { "test", Ev, Gv, XX }, - { "xchg", Eb, Gb, XX }, - { "xchg", Ev, Gv, XX }, - /* 88 */ - { "mov", Eb, Gb, XX }, - { "mov", Ev, Gv, XX }, - { "mov", Gb, Eb, XX }, - { "mov", Gv, Ev, XX }, - { "mov", Ev, Sw, XX }, - { "lea", Gv, M, XX }, - { "mov", Sw, Ev, XX }, - { "pop", Ev, XX, XX }, - /* 90 */ - { "nop", XX, XX, XX }, - { "xchg", eCX, eAX, XX }, - { "xchg", eDX, eAX, XX }, - { "xchg", eBX, eAX, XX }, - { "xchg", eSP, eAX, XX }, - { "xchg", eBP, eAX, XX }, - { "xchg", eSI, eAX, XX }, - { "xchg", eDI, eAX, XX }, - /* 98 */ - { "cW", XX, XX, XX }, /* cwde and cbw */ - { "cR", XX, XX, XX }, /* cdq and cwd */ - { "lcall", Ap, XX, XX }, - { "(bad)", XX, XX, XX }, /* fwait */ - { "pushf", XX, XX, XX }, - { "popf", XX, XX, XX }, - { "sahf", XX, XX, XX }, - { "lahf", XX, XX, XX }, - /* a0 */ - { "mov", AL, Ob, XX }, - { "mov", eAX, Ov, XX }, - { "mov", Ob, AL, XX }, - { "mov", Ov, eAX, XX }, - { "movs", Yb, Xb, XX }, - { "movs", Yv, Xv, XX }, - { "cmps", Xb, Yb, XX }, - { "cmps", Xv, Yv, XX }, - /* a8 */ - { "test", AL, Ib, XX }, - { "test", eAX, Iv, XX }, - { "stos", Yb, AL, XX }, - { "stos", Yv, eAX, XX }, - { "lods", AL, Xb, XX }, - { "lods", eAX, Xv, XX }, - { "scas", AL, Yb, XX }, - { "scas", eAX, Yv, XX }, - /* b0 */ - { "mov", AL, Ib, XX }, - { "mov", CL, Ib, XX }, - { "mov", DL, Ib, XX }, - { "mov", BL, Ib, XX }, - { "mov", AH, Ib, XX }, - { "mov", CH, Ib, XX }, - { "mov", DH, Ib, XX }, - { "mov", BH, Ib, XX }, - /* b8 */ - { "mov", eAX, Iv, XX }, - { "mov", eCX, Iv, XX }, - { "mov", eDX, Iv, XX }, - { "mov", eBX, Iv, XX }, - { "mov", eSP, Iv, XX }, - { "mov", eBP, Iv, XX }, - { "mov", eSI, Iv, XX }, - { "mov", eDI, Iv, XX }, - /* c0 */ - { GRP2b }, - { GRP2S }, - { "ret", Iw, XX, XX }, - { "ret", XX, XX, XX }, - { "les", Gv, Mp, XX }, - { "lds", Gv, Mp, XX }, - { "mov", Eb, Ib, XX }, - { "mov", Ev, Iv, XX }, - /* c8 */ - { "enter", Iw, Ib, XX }, - { "leave", XX, XX, XX }, - { "lret", Iw, XX, XX }, - { "lret", XX, XX, XX }, - { "int3", XX, XX, XX }, - { "int", Ib, XX, XX }, - { "into", XX, XX, XX }, - { "iret", XX, XX, XX }, - /* d0 */ - { GRP2b_one }, - { GRP2S_one }, - { GRP2b_cl }, - { GRP2S_cl }, - { "aam", sIb, XX, XX }, - { "aad", sIb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "xlat", DSBX, XX, XX }, - /* d8 */ - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - /* e0 */ - { "loopne", Jb, XX, XX }, - { "loope", Jb, XX, XX }, - { "loop", Jb, XX, XX }, - { "jEcxz", Jb, XX, XX }, - { "in", AL, Ib, XX }, - { "in", eAX, Ib, XX }, - { "out", Ib, AL, XX }, - { "out", Ib, eAX, XX }, - /* e8 */ - { "call", Jv, XX, XX }, - { "jmp", Jv, XX, XX }, - { "ljmp", Ap, XX, XX }, - { "jmp", Jb, XX, XX }, - { "in", AL, indirDX, XX }, - { "in", eAX, indirDX, XX }, - { "out", indirDX, AL, XX }, - { "out", indirDX, eAX, XX }, - /* f0 */ - { "(bad)", XX, XX, XX }, /* lock prefix */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, /* repne */ - { "(bad)", XX, XX, XX }, /* repz */ - { "hlt", XX, XX, XX }, - { "cmc", XX, XX, XX }, - { GRP3b }, - { GRP3S }, - /* f8 */ - { "clc", XX, XX, XX }, - { "stc", XX, XX, XX }, - { "cli", XX, XX, XX }, - { "sti", XX, XX, XX }, - { "cld", XX, XX, XX }, - { "std", XX, XX, XX }, - { GRP4 }, - { GRP5 }, -}; - -static const struct dis386 dis386_twobyte_att[] = { - /* 00 */ - { GRP6 }, - { GRP7 }, - { "larS", Gv, Ew, XX }, - { "lslS", Gv, Ew, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "clts", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 08 */ - { "invd", XX, XX, XX }, - { "wbinvd", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "ud2a", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { GRPAMD }, - { "femms", XX, XX, XX }, - { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix */ - /* 10 */ - { PREGRP8 }, - { PREGRP9 }, - { "movlps", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ - { "movlps", EX, XM, SIMD_Fixup, 'h' }, - { "unpcklps", XM, EX, XX }, - { "unpckhps", XM, EX, XX }, - { "movhps", XM, EX, SIMD_Fixup, 'l' }, - { "movhps", EX, XM, SIMD_Fixup, 'l' }, - /* 18 */ - { GRP14 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 20 */ - /* these are all backward in appendix A of the intel book */ - { "movL", Rd, Cd, XX }, - { "movL", Rd, Dd, XX }, - { "movL", Cd, Rd, XX }, - { "movL", Dd, Rd, XX }, - { "movL", Rd, Td, XX }, - { "(bad)", XX, XX, XX }, - { "movL", Td, Rd, XX }, - { "(bad)", XX, XX, XX }, - /* 28 */ - { "movaps", XM, EX, XX }, - { "movaps", EX, XM, XX }, - { PREGRP2 }, - { "movntps", Ev, XM, XX }, - { PREGRP4 }, - { PREGRP3 }, - { "ucomiss", XM, EX, XX }, - { "comiss", XM, EX, XX }, - /* 30 */ - { "wrmsr", XX, XX, XX }, - { "rdtsc", XX, XX, XX }, - { "rdmsr", XX, XX, XX }, - { "rdpmc", XX, XX, XX }, - { "sysenter", XX, XX, XX }, - { "sysexit", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 38 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 40 */ - { "cmovo", Gv, Ev, XX }, - { "cmovno", Gv, Ev, XX }, - { "cmovb", Gv, Ev, XX }, - { "cmovae", Gv, Ev, XX }, - { "cmove", Gv, Ev, XX }, - { "cmovne", Gv, Ev, XX }, - { "cmovbe", Gv, Ev, XX }, - { "cmova", Gv, Ev, XX }, - /* 48 */ - { "cmovs", Gv, Ev, XX }, - { "cmovns", Gv, Ev, XX }, - { "cmovp", Gv, Ev, XX }, - { "cmovnp", Gv, Ev, XX }, - { "cmovl", Gv, Ev, XX }, - { "cmovge", Gv, Ev, XX }, - { "cmovle", Gv, Ev, XX }, - { "cmovg", Gv, Ev, XX }, - /* 50 */ - { "movmskps", Gv, EX, XX }, - { PREGRP13 }, - { PREGRP12 }, - { PREGRP11 }, - { "andps", XM, EX, XX }, - { "andnps", XM, EX, XX }, - { "orps", XM, EX, XX }, - { "xorps", XM, EX, XX }, - /* 58 */ - { PREGRP0 }, - { PREGRP10 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { PREGRP14 }, - { PREGRP7 }, - { PREGRP5 }, - { PREGRP6 }, - /* 60 */ - { "punpcklbw", MX, EM, XX }, - { "punpcklwd", MX, EM, XX }, - { "punpckldq", MX, EM, XX }, - { "packsswb", MX, EM, XX }, - { "pcmpgtb", MX, EM, XX }, - { "pcmpgtw", MX, EM, XX }, - { "pcmpgtd", MX, EM, XX }, - { "packuswb", MX, EM, XX }, - /* 68 */ - { "punpckhbw", MX, EM, XX }, - { "punpckhwd", MX, EM, XX }, - { "punpckhdq", MX, EM, XX }, - { "packssdw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "movd", MX, Ed, XX }, - { "movq", MX, EM, XX }, - /* 70 */ - { "pshufw", MX, EM, Ib }, - { GRP10 }, - { GRP11 }, - { GRP12 }, - { "pcmpeqb", MX, EM, XX }, - { "pcmpeqw", MX, EM, XX }, - { "pcmpeqd", MX, EM, XX }, - { "emms", XX, XX, XX }, - /* 78 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "movd", Ed, MX, XX }, - { "movq", EM, MX, XX }, - /* 80 */ - { "jo", Jv, XX, XX }, - { "jno", Jv, XX, XX }, - { "jb", Jv, XX, XX }, - { "jae", Jv, XX, XX }, - { "je", Jv, XX, XX }, - { "jne", Jv, XX, XX }, - { "jbe", Jv, XX, XX }, - { "ja", Jv, XX, XX }, - /* 88 */ - { "js", Jv, XX, XX }, - { "jns", Jv, XX, XX }, - { "jp", Jv, XX, XX }, - { "jnp", Jv, XX, XX }, - { "jl", Jv, XX, XX }, - { "jge", Jv, XX, XX }, - { "jle", Jv, XX, XX }, - { "jg", Jv, XX, XX }, - /* 90 */ - { "seto", Eb, XX, XX }, - { "setno", Eb, XX, XX }, - { "setb", Eb, XX, XX }, - { "setae", Eb, XX, XX }, - { "sete", Eb, XX, XX }, - { "setne", Eb, XX, XX }, - { "setbe", Eb, XX, XX }, - { "seta", Eb, XX, XX }, - /* 98 */ - { "sets", Eb, XX, XX }, - { "setns", Eb, XX, XX }, - { "setp", Eb, XX, XX }, - { "setnp", Eb, XX, XX }, - { "setl", Eb, XX, XX }, - { "setge", Eb, XX, XX }, - { "setle", Eb, XX, XX }, - { "setg", Eb, XX, XX }, - /* a0 */ - { "pushP", fs, XX, XX }, - { "popP", fs, XX, XX }, - { "cpuid", XX, XX, XX }, - { "btS", Ev, Gv, XX }, - { "shldS", Ev, Gv, Ib }, - { "shldS", Ev, Gv, CL }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* a8 */ - { "pushP", gs, XX, XX }, - { "popP", gs, XX, XX }, - { "rsm", XX, XX, XX }, - { "btsS", Ev, Gv, XX }, - { "shrdS", Ev, Gv, Ib }, - { "shrdS", Ev, Gv, CL }, - { GRP13 }, - { "imulS", Gv, Ev, XX }, - /* b0 */ - { "cmpxchgB", Eb, Gb, XX }, - { "cmpxchgS", Ev, Gv, XX }, - { "lssS", Gv, Mp, XX }, - { "btrS", Ev, Gv, XX }, - { "lfsS", Gv, Mp, XX }, - { "lgsS", Gv, Mp, XX }, - { "movzbR", Gv, Eb, XX }, - { "movzwR", Gv, Ew, XX }, /* yes, there really is movzww ! */ - /* b8 */ - { "(bad)", XX, XX, XX }, - { "ud2b", XX, XX, XX }, - { GRP8 }, - { "btcS", Ev, Gv, XX }, - { "bsfS", Gv, Ev, XX }, - { "bsrS", Gv, Ev, XX }, - { "movsbR", Gv, Eb, XX }, - { "movswR", Gv, Ew, XX }, /* yes, there really is movsww ! */ - /* c0 */ - { "xaddB", Eb, Gb, XX }, - { "xaddS", Ev, Gv, XX }, - { PREGRP1 }, - { "(bad)", XX, XX, XX }, - { "pinsrw", MX, Ev, Ib }, - { "pextrw", Ev, MX, Ib }, - { "shufps", XM, EX, Ib }, - { GRP9 }, - /* c8 */ - { "bswap", eAX, XX, XX }, /* bswap doesn't support 16 bit regs */ - { "bswap", eCX, XX, XX }, - { "bswap", eDX, XX, XX }, - { "bswap", eBX, XX, XX }, - { "bswap", eSP, XX, XX }, - { "bswap", eBP, XX, XX }, - { "bswap", eSI, XX, XX }, - { "bswap", eDI, XX, XX }, - /* d0 */ - { "(bad)", XX, XX, XX }, - { "psrlw", MX, EM, XX }, - { "psrld", MX, EM, XX }, - { "psrlq", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "pmullw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "pmovmskb", Ev, MX, XX }, - /* d8 */ - { "psubusb", MX, EM, XX }, - { "psubusw", MX, EM, XX }, - { "pminub", MX, EM, XX }, - { "pand", MX, EM, XX }, - { "paddusb", MX, EM, XX }, - { "paddusw", MX, EM, XX }, - { "pmaxub", MX, EM, XX }, - { "pandn", MX, EM, XX }, - /* e0 */ - { "pavgb", MX, EM, XX }, - { "psraw", MX, EM, XX }, - { "psrad", MX, EM, XX }, - { "pavgw", MX, EM, XX }, - { "pmulhuw", MX, EM, XX }, - { "pmulhw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "movntq", Ev, MX, XX }, - /* e8 */ - { "psubsb", MX, EM, XX }, - { "psubsw", MX, EM, XX }, - { "pminsw", MX, EM, XX }, - { "por", MX, EM, XX }, - { "paddsb", MX, EM, XX }, - { "paddsw", MX, EM, XX }, - { "pmaxsw", MX, EM, XX }, - { "pxor", MX, EM, XX }, - /* f0 */ - { "(bad)", XX, XX, XX }, - { "psllw", MX, EM, XX }, - { "pslld", MX, EM, XX }, - { "psllq", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "pmaddwd", MX, EM, XX }, - { "psadbw", MX, EM, XX }, - { "maskmovq", MX, EM, XX }, - /* f8 */ - { "psubb", MX, EM, XX }, - { "psubw", MX, EM, XX }, - { "psubd", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "paddb", MX, EM, XX }, - { "paddw", MX, EM, XX }, - { "paddd", MX, EM, XX }, - { "(bad)", XX, XX, XX } -}; - -static const struct dis386 dis386_twobyte_intel[] = { - /* 00 */ - { GRP6 }, - { GRP7 }, - { "lar", Gv, Ew, XX }, - { "lsl", Gv, Ew, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "clts", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 08 */ - { "invd", XX, XX, XX }, - { "wbinvd", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "ud2a", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { GRPAMD }, - { "femms" , XX, XX, XX}, - { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix */ - /* 10 */ - { PREGRP8 }, - { PREGRP9 }, - { "movlps", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ - { "movlps", EX, XM, SIMD_Fixup, 'h' }, - { "unpcklps", XM, EX, XX }, - { "unpckhps", XM, EX, XX }, - { "movhps", XM, EX, SIMD_Fixup, 'l' }, - { "movhps", EX, XM, SIMD_Fixup, 'l' }, - /* 18 */ - { GRP14 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 20 */ - /* these are all backward in appendix A of the intel book */ - { "mov", Rd, Cd, XX }, - { "mov", Rd, Dd, XX }, - { "mov", Cd, Rd, XX }, - { "mov", Dd, Rd, XX }, - { "mov", Rd, Td, XX }, - { "(bad)", XX, XX, XX }, - { "mov", Td, Rd, XX }, - { "(bad)", XX, XX, XX }, - /* 28 */ - { "movaps", XM, EX, XX }, - { "movaps", EX, XM, XX }, - { PREGRP2 }, - { "movntps", Ev, XM, XX }, - { PREGRP4 }, - { PREGRP3 }, - { "ucomiss", XM, EX, XX }, - { "comiss", XM, EX, XX }, - /* 30 */ - { "wrmsr", XX, XX, XX }, - { "rdtsc", XX, XX, XX }, - { "rdmsr", XX, XX, XX }, - { "rdpmc", XX, XX, XX }, - { "sysenter", XX, XX, XX }, - { "sysexit", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 38 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 40 */ - { "cmovo", Gv, Ev, XX }, - { "cmovno", Gv, Ev, XX }, - { "cmovb", Gv, Ev, XX }, - { "cmovae", Gv, Ev, XX }, - { "cmove", Gv, Ev, XX }, - { "cmovne", Gv, Ev, XX }, - { "cmovbe", Gv, Ev, XX }, - { "cmova", Gv, Ev, XX }, - /* 48 */ - { "cmovs", Gv, Ev, XX }, - { "cmovns", Gv, Ev, XX }, - { "cmovp", Gv, Ev, XX }, - { "cmovnp", Gv, Ev, XX }, - { "cmovl", Gv, Ev, XX }, - { "cmovge", Gv, Ev, XX }, - { "cmovle", Gv, Ev, XX }, - { "cmovg", Gv, Ev, XX }, - /* 50 */ - { "movmskps", Gv, EX, XX }, - { PREGRP13 }, - { PREGRP12 }, - { PREGRP11 }, - { "andps", XM, EX, XX }, - { "andnps", XM, EX, XX }, - { "orps", XM, EX, XX }, - { "xorps", XM, EX, XX }, - /* 58 */ - { PREGRP0 }, - { PREGRP10 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { PREGRP14 }, - { PREGRP7 }, - { PREGRP5 }, - { PREGRP6 }, - /* 60 */ - { "punpcklbw", MX, EM, XX }, - { "punpcklwd", MX, EM, XX }, - { "punpckldq", MX, EM, XX }, - { "packsswb", MX, EM, XX }, - { "pcmpgtb", MX, EM, XX }, - { "pcmpgtw", MX, EM, XX }, - { "pcmpgtd", MX, EM, XX }, - { "packuswb", MX, EM, XX }, - /* 68 */ - { "punpckhbw", MX, EM, XX }, - { "punpckhwd", MX, EM, XX }, - { "punpckhdq", MX, EM, XX }, - { "packssdw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "movd", MX, Ed, XX }, - { "movq", MX, EM, XX }, - /* 70 */ - { "pshufw", MX, EM, Ib }, - { GRP10 }, - { GRP11 }, - { GRP12 }, - { "pcmpeqb", MX, EM, XX }, - { "pcmpeqw", MX, EM, XX }, - { "pcmpeqd", MX, EM, XX }, - { "emms", XX, XX, XX }, - /* 78 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "movd", Ed, MX, XX }, - { "movq", EM, MX, XX }, - /* 80 */ - { "jo", Jv, XX, XX }, - { "jno", Jv, XX, XX }, - { "jb", Jv, XX, XX }, - { "jae", Jv, XX, XX }, - { "je", Jv, XX, XX }, - { "jne", Jv, XX, XX }, - { "jbe", Jv, XX, XX }, - { "ja", Jv, XX, XX }, - /* 88 */ - { "js", Jv, XX, XX }, - { "jns", Jv, XX, XX }, - { "jp", Jv, XX, XX }, - { "jnp", Jv, XX, XX }, - { "jl", Jv, XX, XX }, - { "jge", Jv, XX, XX }, - { "jle", Jv, XX, XX }, - { "jg", Jv, XX, XX }, - /* 90 */ - { "seto", Eb, XX, XX }, - { "setno", Eb, XX, XX }, - { "setb", Eb, XX, XX }, - { "setae", Eb, XX, XX }, - { "sete", Eb, XX, XX }, - { "setne", Eb, XX, XX }, - { "setbe", Eb, XX, XX }, - { "seta", Eb, XX, XX }, - /* 98 */ - { "sets", Eb, XX, XX }, - { "setns", Eb, XX, XX }, - { "setp", Eb, XX, XX }, - { "setnp", Eb, XX, XX }, - { "setl", Eb, XX, XX }, - { "setge", Eb, XX, XX }, - { "setle", Eb, XX, XX }, - { "setg", Eb, XX, XX }, - /* a0 */ - { "push", fs, XX, XX }, - { "pop", fs, XX, XX }, - { "cpuid", XX, XX, XX }, - { "bt", Ev, Gv, XX }, - { "shld", Ev, Gv, Ib }, - { "shld", Ev, Gv, CL }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* a8 */ - { "push", gs, XX, XX }, - { "pop", gs, XX, XX }, - { "rsm" , XX, XX, XX}, - { "bts", Ev, Gv, XX }, - { "shrd", Ev, Gv, Ib }, - { "shrd", Ev, Gv, CL }, - { GRP13 }, - { "imul", Gv, Ev, XX }, - /* b0 */ - { "cmpxchg", Eb, Gb, XX }, - { "cmpxchg", Ev, Gv, XX }, - { "lss", Gv, Mp, XX }, - { "btr", Ev, Gv, XX }, - { "lfs", Gv, Mp, XX }, - { "lgs", Gv, Mp, XX }, - { "movzx", Gv, Eb, XX }, - { "movzx", Gv, Ew, XX }, - /* b8 */ - { "(bad)", XX, XX, XX }, - { "ud2b", XX, XX, XX }, - { GRP8 }, - { "btc", Ev, Gv, XX }, - { "bsf", Gv, Ev, XX }, - { "bsr", Gv, Ev, XX }, - { "movsx", Gv, Eb, XX }, - { "movsx", Gv, Ew, XX }, - /* c0 */ - { "xadd", Eb, Gb, XX }, - { "xadd", Ev, Gv, XX }, - { PREGRP1 }, - { "(bad)", XX, XX, XX }, - { "pinsrw", MX, Ev, Ib }, - { "pextrw", Ev, MX, Ib }, - { "shufps", XM, EX, Ib }, - { GRP9 }, - /* c8 */ - { "bswap", eAX, XX, XX }, /* bswap doesn't support 16 bit regs */ - { "bswap", eCX, XX, XX }, - { "bswap", eDX, XX, XX }, - { "bswap", eBX, XX, XX }, - { "bswap", eSP, XX, XX }, - { "bswap", eBP, XX, XX }, - { "bswap", eSI, XX, XX }, - { "bswap", eDI, XX, XX }, - /* d0 */ - { "(bad)", XX, XX, XX }, - { "psrlw", MX, EM, XX }, - { "psrld", MX, EM, XX }, - { "psrlq", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "pmullw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "pmovmskb", Ev, MX, XX }, - /* d8 */ - { "psubusb", MX, EM, XX }, - { "psubusw", MX, EM, XX }, - { "pminub", MX, EM, XX }, - { "pand", MX, EM, XX }, - { "paddusb", MX, EM, XX }, - { "paddusw", MX, EM, XX }, - { "pmaxub", MX, EM, XX }, - { "pandn", MX, EM, XX }, - /* e0 */ - { "pavgb", MX, EM, XX }, - { "psraw", MX, EM, XX }, - { "psrad", MX, EM, XX }, - { "pavgw", MX, EM, XX }, - { "pmulhuw", MX, EM, XX }, - { "pmulhw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "movntq", Ev, MX, XX }, - /* e8 */ - { "psubsb", MX, EM, XX }, - { "psubsw", MX, EM, XX }, - { "pminsw", MX, EM, XX }, - { "por", MX, EM, XX }, - { "paddsb", MX, EM, XX }, - { "paddsw", MX, EM, XX }, - { "pmaxsw", MX, EM, XX }, - { "pxor", MX, EM, XX }, - /* f0 */ - { "(bad)", XX, XX, XX }, - { "psllw", MX, EM, XX }, - { "pslld", MX, EM, XX }, - { "psllq", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "pmaddwd", MX, EM, XX }, - { "psadbw", MX, EM, XX }, - { "maskmovq", MX, EM, XX }, - /* f8 */ - { "psubb", MX, EM, XX }, - { "psubw", MX, EM, XX }, - { "psubd", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "paddb", MX, EM, XX }, - { "paddw", MX, EM, XX }, - { "paddd", MX, EM, XX }, - { "(bad)", XX, XX, XX } -}; - -static const unsigned char onebyte_has_modrm[256] = { - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - /* ------------------------------- */ - /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ - /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ - /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ - /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ - /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ - /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ - /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ - /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ - /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ - /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ - /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ - /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ - /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ - /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ - /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ - /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ - /* ------------------------------- */ - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ -}; - -static const unsigned char twobyte_has_modrm[256] = { - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - /* ------------------------------- */ - /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ - /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */ - /* 20 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 2f */ - /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ - /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ - /* 50 */ 1,1,1,1,1,1,1,1,1,1,0,0,1,1,1,1, /* 5f */ - /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,0,0,1,1, /* 6f */ - /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */ - /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ - /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ - /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ - /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1, /* df */ - /* e0 */ 1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 0,1,1,1,0,1,1,1,1,1,1,0,1,1,1,0 /* ff */ - /* ------------------------------- */ - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ -}; - -static const unsigned char twobyte_uses_f3_prefix[256] = { - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - /* ------------------------------- */ - /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ - /* 10 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ - /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */ - /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ - /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ - /* 50 */ 0,1,1,1,0,0,0,0,1,1,0,0,1,1,1,1, /* 5f */ - /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ - /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ - /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ - /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ - /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ - /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ - /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ - /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 /* ff */ - /* ------------------------------- */ - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ -}; - -static char obuf[100]; -static char *obufp; -static char scratchbuf[100]; -static unsigned char *start_codep; -static unsigned char *insn_codep; -static unsigned char *codep; -static disassemble_info *the_info; -static int mod; -static int rm; -static int reg; -static void oappend PARAMS ((const char *s)); - -static const char *names32[]={ - "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi", -}; -static const char *names16[] = { - "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di", -}; -static const char *names8[] = { - "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh", -}; -static const char *names_seg[] = { - "%es","%cs","%ss","%ds","%fs","%gs","%?","%?", -}; -static const char *index16[] = { - "%bx,%si","%bx,%di","%bp,%si","%bp,%di","%si","%di","%bp","%bx" -}; - -static const struct dis386 grps[][8] = { - /* GRP1b */ - { - { "addA", Eb, Ib, XX }, - { "orA", Eb, Ib, XX }, - { "adcA", Eb, Ib, XX }, - { "sbbA", Eb, Ib, XX }, - { "andA", Eb, Ib, XX }, - { "subA", Eb, Ib, XX }, - { "xorA", Eb, Ib, XX }, - { "cmpA", Eb, Ib, XX } - }, - /* GRP1S */ - { - { "addQ", Ev, Iv, XX }, - { "orQ", Ev, Iv, XX }, - { "adcQ", Ev, Iv, XX }, - { "sbbQ", Ev, Iv, XX }, - { "andQ", Ev, Iv, XX }, - { "subQ", Ev, Iv, XX }, - { "xorQ", Ev, Iv, XX }, - { "cmpQ", Ev, Iv, XX } - }, - /* GRP1Ss */ - { - { "addQ", Ev, sIb, XX }, - { "orQ", Ev, sIb, XX }, - { "adcQ", Ev, sIb, XX }, - { "sbbQ", Ev, sIb, XX }, - { "andQ", Ev, sIb, XX }, - { "subQ", Ev, sIb, XX }, - { "xorQ", Ev, sIb, XX }, - { "cmpQ", Ev, sIb, XX } - }, - /* GRP2b */ - { - { "rolA", Eb, Ib, XX }, - { "rorA", Eb, Ib, XX }, - { "rclA", Eb, Ib, XX }, - { "rcrA", Eb, Ib, XX }, - { "shlA", Eb, Ib, XX }, - { "shrA", Eb, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, Ib, XX }, - }, - /* GRP2S */ - { - { "rolQ", Ev, Ib, XX }, - { "rorQ", Ev, Ib, XX }, - { "rclQ", Ev, Ib, XX }, - { "rcrQ", Ev, Ib, XX }, - { "shlQ", Ev, Ib, XX }, - { "shrQ", Ev, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "sarQ", Ev, Ib, XX }, - }, - /* GRP2b_one */ - { - { "rolA", Eb, XX, XX }, - { "rorA", Eb, XX, XX }, - { "rclA", Eb, XX, XX }, - { "rcrA", Eb, XX, XX }, - { "shlA", Eb, XX, XX }, - { "shrA", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, XX, XX }, - }, - /* GRP2S_one */ - { - { "rolQ", Ev, XX, XX }, - { "rorQ", Ev, XX, XX }, - { "rclQ", Ev, XX, XX }, - { "rcrQ", Ev, XX, XX }, - { "shlQ", Ev, XX, XX }, - { "shrQ", Ev, XX, XX }, - { "(bad)", XX, XX, XX}, - { "sarQ", Ev, XX, XX }, - }, - /* GRP2b_cl */ - { - { "rolA", Eb, CL, XX }, - { "rorA", Eb, CL, XX }, - { "rclA", Eb, CL, XX }, - { "rcrA", Eb, CL, XX }, - { "shlA", Eb, CL, XX }, - { "shrA", Eb, CL, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, CL, XX }, - }, - /* GRP2S_cl */ - { - { "rolQ", Ev, CL, XX }, - { "rorQ", Ev, CL, XX }, - { "rclQ", Ev, CL, XX }, - { "rcrQ", Ev, CL, XX }, - { "shlQ", Ev, CL, XX }, - { "shrQ", Ev, CL, XX }, - { "(bad)", XX, XX, XX }, - { "sarQ", Ev, CL, XX } - }, - /* GRP3b */ - { - { "testA", Eb, Ib, XX }, - { "(bad)", Eb, XX, XX }, - { "notA", Eb, XX, XX }, - { "negA", Eb, XX, XX }, - { "mulB", AL, Eb, XX }, - { "imulB", AL, Eb, XX }, - { "divB", AL, Eb, XX }, - { "idivB", AL, Eb, XX } - }, - /* GRP3S */ - { - { "testQ", Ev, Iv, XX }, - { "(bad)", XX, XX, XX }, - { "notQ", Ev, XX, XX }, - { "negQ", Ev, XX, XX }, - { "mulS", eAX, Ev, XX }, - { "imulS", eAX, Ev, XX }, - { "divS", eAX, Ev, XX }, - { "idivS", eAX, Ev, XX }, - }, - /* GRP4 */ - { - { "incA", Eb, XX, XX }, - { "decA", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP5 */ - { - { "incQ", Ev, XX, XX }, - { "decQ", Ev, XX, XX }, - { "callP", indirEv, XX, XX }, - { "lcallP", indirEv, XX, XX }, - { "jmpP", indirEv, XX, XX }, - { "ljmpP", indirEv, XX, XX }, - { "pushQ", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP6 */ - { - { "sldt", Ew, XX, XX }, - { "str", Ew, XX, XX }, - { "lldt", Ew, XX, XX }, - { "ltr", Ew, XX, XX }, - { "verr", Ew, XX, XX }, - { "verw", Ew, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX } - }, - /* GRP7 */ - { - { "sgdt", Ew, XX, XX }, - { "sidt", Ew, XX, XX }, - { "lgdt", Ew, XX, XX }, - { "lidt", Ew, XX, XX }, - { "smsw", Ew, XX, XX }, - { "(bad)", XX, XX, XX }, - { "lmsw", Ew, XX, XX }, - { "invlpg", Ew, XX, XX }, - }, - /* GRP8 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "btQ", Ev, Ib, XX }, - { "btsQ", Ev, Ib, XX }, - { "btrQ", Ev, Ib, XX }, - { "btcQ", Ev, Ib, XX }, - }, - /* GRP9 */ - { - { "(bad)", XX, XX, XX }, - { "cmpxchg8b", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP10 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrlw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psraw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psllw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP11 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrld", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psrad", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "pslld", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP12 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrlq", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psllq", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP13 */ - { - { "fxsave", Ev, XX, XX }, - { "fxrstor", Ev, XX, XX }, - { "ldmxcsr", Ev, XX, XX }, - { "stmxcsr", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "sfence", None, XX, XX }, - }, - /* GRP14 */ - { - { "prefetchnta", Ev, XX, XX }, - { "prefetcht0", Ev, XX, XX }, - { "prefetcht1", Ev, XX, XX }, - { "prefetcht2", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRPAMD */ - { - { "prefetch", Eb, XX, XX }, - { "prefetchw", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - } - -}; - -static const struct dis386 prefix_user_table[][2] = { - /* PREGRP0 */ - { - { "addps", XM, EX, XX }, - { "addss", XM, EX, XX }, - }, - /* PREGRP1 */ - { - { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX */ - { "", XM, EX, OPSIMD }, - }, - /* PREGRP2 */ - { - { "cvtpi2ps", XM, EM, XX }, - { "cvtsi2ss", XM, Ev, XX }, - }, - /* PREGRP3 */ - { - { "cvtps2pi", MX, EX, XX }, - { "cvtss2si", Gv, EX, XX }, - }, - /* PREGRP4 */ - { - { "cvttps2pi", MX, EX, XX }, - { "cvttss2si", Gv, EX, XX }, - }, - /* PREGRP5 */ - { - { "divps", XM, EX, XX }, - { "divss", XM, EX, XX }, - }, - /* PREGRP6 */ - { - { "maxps", XM, EX, XX }, - { "maxss", XM, EX, XX }, - }, - /* PREGRP7 */ - { - { "minps", XM, EX, XX }, - { "minss", XM, EX, XX }, - }, - /* PREGRP8 */ - { - { "movups", XM, EX, XX }, - { "movss", XM, EX, XX }, - }, - /* PREGRP9 */ - { - { "movups", EX, XM, XX }, - { "movss", EX, XM, XX }, - }, - /* PREGRP10 */ - { - { "mulps", XM, EX, XX }, - { "mulss", XM, EX, XX }, - }, - /* PREGRP11 */ - { - { "rcpps", XM, EX, XX }, - { "rcpss", XM, EX, XX }, - }, - /* PREGRP12 */ - { - { "rsqrtps", XM, EX, XX }, - { "rsqrtss", XM, EX, XX }, - }, - /* PREGRP13 */ - { - { "sqrtps", XM, EX, XX }, - { "sqrtss", XM, EX, XX }, - }, - /* PREGRP14 */ - { - { "subps", XM, EX, XX }, - { "subss", XM, EX, XX }, - } -}; - -#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") - -static void -ckprefix () -{ - prefixes = 0; - used_prefixes = 0; - while (1) - { - FETCH_DATA (the_info, codep + 1); - switch (*codep) - { - case 0xf3: - prefixes |= PREFIX_REPZ; - break; - case 0xf2: - prefixes |= PREFIX_REPNZ; - break; - case 0xf0: - prefixes |= PREFIX_LOCK; - break; - case 0x2e: - prefixes |= PREFIX_CS; - break; - case 0x36: - prefixes |= PREFIX_SS; - break; - case 0x3e: - prefixes |= PREFIX_DS; - break; - case 0x26: - prefixes |= PREFIX_ES; - break; - case 0x64: - prefixes |= PREFIX_FS; - break; - case 0x65: - prefixes |= PREFIX_GS; - break; - case 0x66: - prefixes |= PREFIX_DATA; - break; - case 0x67: - prefixes |= PREFIX_ADDR; - break; - case FWAIT_OPCODE: - /* fwait is really an instruction. If there are prefixes - before the fwait, they belong to the fwait, *not* to the - following instruction. */ - if (prefixes) - { - prefixes |= PREFIX_FWAIT; - codep++; - return; - } - prefixes = PREFIX_FWAIT; - break; - default: - return; - } - codep++; - } -} - -/* Return the name of the prefix byte PREF, or NULL if PREF is not a - prefix byte. */ - -static const char * -prefix_name (pref, sizeflag) - int pref; - int sizeflag; -{ - switch (pref) - { - case 0xf3: - return "repz"; - case 0xf2: - return "repnz"; - case 0xf0: - return "lock"; - case 0x2e: - return "cs"; - case 0x36: - return "ss"; - case 0x3e: - return "ds"; - case 0x26: - return "es"; - case 0x64: - return "fs"; - case 0x65: - return "gs"; - case 0x66: - return (sizeflag & DFLAG) ? "data16" : "data32"; - case 0x67: - return (sizeflag & AFLAG) ? "addr16" : "addr32"; - case FWAIT_OPCODE: - return "fwait"; - default: - return NULL; - } -} - -static char op1out[100], op2out[100], op3out[100]; -static int op_ad, op_index[3]; -static unsigned int op_address[3]; -static unsigned int start_pc; - - -/* - * On the 386's of 1988, the maximum length of an instruction is 15 bytes. - * (see topic "Redundant prefixes" in the "Differences from 8086" - * section of the "Virtual 8086 Mode" chapter.) - * 'pc' should be the address of this instruction, it will - * be used to print the target address if this is a relative jump or call - * The function returns the length of this instruction in bytes. - */ - -static int print_insn_i386 - PARAMS ((bfd_vma pc, disassemble_info *info)); - -static char intel_syntax; -static char open_char; -static char close_char; -static char separator_char; -static char scale_char; - -int -print_insn_i386_att (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - intel_syntax = 0; - open_char = '('; - close_char = ')'; - separator_char = ','; - scale_char = ','; - - return print_insn_i386 (pc, info); -} - -int -print_insn_i386_intel (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - intel_syntax = 1; - open_char = '['; - close_char = ']'; - separator_char = '+'; - scale_char = '*'; - - return print_insn_i386 (pc, info); -} - -static int -print_insn_i386 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - const struct dis386 *dp; - int i; - int two_source_ops; - char *first, *second, *third; - int needcomma; - unsigned char need_modrm; - unsigned char uses_f3_prefix; - VOLATILE int sizeflag; - VOLATILE int orig_sizeflag; - - struct dis_private priv; - bfd_byte *inbuf = priv.the_buffer; - - if (info->mach == bfd_mach_i386_i386 - || info->mach == bfd_mach_i386_i386_intel_syntax) - sizeflag = AFLAG|DFLAG; - else if (info->mach == bfd_mach_i386_i8086) - sizeflag = 0; - else - abort (); - orig_sizeflag = sizeflag; - - /* The output looks better if we put 7 bytes on a line, since that - puts most long word instructions on a single line. */ - info->bytes_per_line = 7; - - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = pc; - - obuf[0] = 0; - op1out[0] = 0; - op2out[0] = 0; - op3out[0] = 0; - - op_index[0] = op_index[1] = op_index[2] = -1; - - the_info = info; - start_pc = pc; - start_codep = inbuf; - codep = inbuf; - - if (setjmp (priv.bailout) != 0) - { - const char *name; - - /* Getting here means we tried for data but didn't get it. That - means we have an incomplete instruction of some sort. Just - print the first byte as a prefix or a .byte pseudo-op. */ - if (codep > inbuf) - { - name = prefix_name (inbuf[0], orig_sizeflag); - if (name != NULL) - (*info->fprintf_func) (info->stream, "%s", name); - else - { - /* Just print the first byte as a .byte instruction. */ - (*info->fprintf_func) (info->stream, ".byte 0x%x", - (unsigned int) inbuf[0]); - } - - return 1; - } - - return -1; - } - - ckprefix (); - - insn_codep = codep; - - FETCH_DATA (info, codep + 1); - two_source_ops = (*codep == 0x62) || (*codep == 0xc8); - - obufp = obuf; - - if ((prefixes & PREFIX_FWAIT) - && ((*codep < 0xd8) || (*codep > 0xdf))) - { - const char *name; - - /* fwait not followed by floating point instruction. Print the - first prefix, which is probably fwait itself. */ - name = prefix_name (inbuf[0], orig_sizeflag); - if (name == NULL) - name = INTERNAL_DISASSEMBLER_ERROR; - (*info->fprintf_func) (info->stream, "%s", name); - return 1; - } - - if (*codep == 0x0f) - { - FETCH_DATA (info, codep + 2); - if (intel_syntax) - dp = &dis386_twobyte_intel[*++codep]; - else - dp = &dis386_twobyte_att[*++codep]; - need_modrm = twobyte_has_modrm[*codep]; - uses_f3_prefix = twobyte_uses_f3_prefix[*codep]; - } - else - { - if (intel_syntax) - dp = &dis386_intel[*codep]; - else - dp = &dis386_att[*codep]; - need_modrm = onebyte_has_modrm[*codep]; - uses_f3_prefix = 0; - } - codep++; - - if (!uses_f3_prefix && (prefixes & PREFIX_REPZ)) - { - oappend ("repz "); - used_prefixes |= PREFIX_REPZ; - } - if (prefixes & PREFIX_REPNZ) - { - oappend ("repnz "); - used_prefixes |= PREFIX_REPNZ; - } - if (prefixes & PREFIX_LOCK) - { - oappend ("lock "); - used_prefixes |= PREFIX_LOCK; - } - - if (prefixes & PREFIX_DATA) - sizeflag ^= DFLAG; - - if (prefixes & PREFIX_ADDR) - { - sizeflag ^= AFLAG; - if (sizeflag & AFLAG) - oappend ("addr32 "); - else - oappend ("addr16 "); - used_prefixes |= PREFIX_ADDR; - } - - if (need_modrm) - { - FETCH_DATA (info, codep + 1); - mod = (*codep >> 6) & 3; - reg = (*codep >> 3) & 7; - rm = *codep & 7; - } - - if (dp->name == NULL && dp->bytemode1 == FLOATCODE) - { - dofloat (sizeflag); - } - else - { - if (dp->name == NULL) - { - switch(dp->bytemode2) - { - case USE_GROUPS: - dp = &grps[dp->bytemode1][reg]; - break; - case USE_PREFIX_USER_TABLE: - dp = &prefix_user_table[dp->bytemode1][prefixes & PREFIX_REPZ ? 1 : 0]; - used_prefixes |= (prefixes & PREFIX_REPZ); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } - } - - putop (dp->name, sizeflag); - - obufp = op1out; - op_ad = 2; - if (dp->op1) - (*dp->op1)(dp->bytemode1, sizeflag); - - obufp = op2out; - op_ad = 1; - if (dp->op2) - (*dp->op2)(dp->bytemode2, sizeflag); - - obufp = op3out; - op_ad = 0; - if (dp->op3) - (*dp->op3)(dp->bytemode3, sizeflag); - } - - /* See if any prefixes were not used. If so, print the first one - separately. If we don't do this, we'll wind up printing an - instruction stream which does not precisely correspond to the - bytes we are disassembling. */ - if ((prefixes & ~used_prefixes) != 0) - { - const char *name; - - name = prefix_name (inbuf[0], orig_sizeflag); - if (name == NULL) - name = INTERNAL_DISASSEMBLER_ERROR; - (*info->fprintf_func) (info->stream, "%s", name); - return 1; - } - - obufp = obuf + strlen (obuf); - for (i = strlen (obuf); i < 6; i++) - oappend (" "); - oappend (" "); - (*info->fprintf_func) (info->stream, "%s", obuf); - - /* The enter and bound instructions are printed with operands in the same - order as the intel book; everything else is printed in reverse order. */ - if (intel_syntax || two_source_ops) - { - first = op1out; - second = op2out; - third = op3out; - op_ad = op_index[0]; - op_index[0] = op_index[2]; - op_index[2] = op_ad; - } - else - { - first = op3out; - second = op2out; - third = op1out; - } - needcomma = 0; - if (*first) - { - if (op_index[0] != -1) - (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info); - else - (*info->fprintf_func) (info->stream, "%s", first); - needcomma = 1; - } - if (*second) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[1] != -1) - (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info); - else - (*info->fprintf_func) (info->stream, "%s", second); - needcomma = 1; - } - if (*third) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[2] != -1) - (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info); - else - (*info->fprintf_func) (info->stream, "%s", third); - } - return codep - inbuf; -} - -static const char *float_mem_att[] = { - /* d8 */ - "fadds", - "fmuls", - "fcoms", - "fcomps", - "fsubs", - "fsubrs", - "fdivs", - "fdivrs", - /* d9 */ - "flds", - "(bad)", - "fsts", - "fstps", - "fldenv", - "fldcw", - "fNstenv", - "fNstcw", - /* da */ - "fiaddl", - "fimull", - "ficoml", - "ficompl", - "fisubl", - "fisubrl", - "fidivl", - "fidivrl", - /* db */ - "fildl", - "(bad)", - "fistl", - "fistpl", - "(bad)", - "fldt", - "(bad)", - "fstpt", - /* dc */ - "faddl", - "fmull", - "fcoml", - "fcompl", - "fsubl", - "fsubrl", - "fdivl", - "fdivrl", - /* dd */ - "fldl", - "(bad)", - "fstl", - "fstpl", - "frstor", - "(bad)", - "fNsave", - "fNstsw", - /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", - /* df */ - "fild", - "(bad)", - "fist", - "fistp", - "fbld", - "fildll", - "fbstp", - "fistpll", -}; - -static const char *float_mem_intel[] = { - /* d8 */ - "fadd", - "fmul", - "fcom", - "fcomp", - "fsub", - "fsubr", - "fdiv", - "fdivr", - /* d9 */ - "fld", - "(bad)", - "fst", - "fstp", - "fldenv", - "fldcw", - "fNstenv", - "fNstcw", - /* da */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", - /* db */ - "fild", - "(bad)", - "fist", - "fistp", - "(bad)", - "fld", - "(bad)", - "fstp", - /* dc */ - "fadd", - "fmul", - "fcom", - "fcomp", - "fsub", - "fsubr", - "fdiv", - "fdivr", - /* dd */ - "fld", - "(bad)", - "fst", - "fstp", - "frstor", - "(bad)", - "fNsave", - "fNstsw", - /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", - /* df */ - "fild", - "(bad)", - "fist", - "fistp", - "fbld", - "fild", - "fbstp", - "fistpll", -}; - -#define ST OP_ST, 0 -#define STi OP_STi, 0 - -#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0 -#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0 -#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0 -#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0 -#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0 -#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0 -#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0 -#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0 -#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0 - -static const struct dis386 float_reg[][8] = { - /* d8 */ - { - { "fadd", ST, STi, XX }, - { "fmul", ST, STi, XX }, - { "fcom", STi, XX, XX }, - { "fcomp", STi, XX, XX }, - { "fsub", ST, STi, XX }, - { "fsubr", ST, STi, XX }, - { "fdiv", ST, STi, XX }, - { "fdivr", ST, STi, XX }, - }, - /* d9 */ - { - { "fld", STi, XX, XX }, - { "fxch", STi, XX, XX }, - { FGRPd9_2 }, - { "(bad)", XX, XX, XX }, - { FGRPd9_4 }, - { FGRPd9_5 }, - { FGRPd9_6 }, - { FGRPd9_7 }, - }, - /* da */ - { - { "fcmovb", ST, STi, XX }, - { "fcmove", ST, STi, XX }, - { "fcmovbe",ST, STi, XX }, - { "fcmovu", ST, STi, XX }, - { "(bad)", XX, XX, XX }, - { FGRPda_5 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* db */ - { - { "fcmovnb",ST, STi, XX }, - { "fcmovne",ST, STi, XX }, - { "fcmovnbe",ST, STi, XX }, - { "fcmovnu",ST, STi, XX }, - { FGRPdb_4 }, - { "fucomi", ST, STi, XX }, - { "fcomi", ST, STi, XX }, - { "(bad)", XX, XX, XX }, - }, - /* dc */ - { - { "fadd", STi, ST, XX }, - { "fmul", STi, ST, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, -#if UNIXWARE_COMPAT - { "fsub", STi, ST, XX }, - { "fsubr", STi, ST, XX }, - { "fdiv", STi, ST, XX }, - { "fdivr", STi, ST, XX }, -#else - { "fsubr", STi, ST, XX }, - { "fsub", STi, ST, XX }, - { "fdivr", STi, ST, XX }, - { "fdiv", STi, ST, XX }, -#endif - }, - /* dd */ - { - { "ffree", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "fst", STi, XX, XX }, - { "fstp", STi, XX, XX }, - { "fucom", STi, XX, XX }, - { "fucomp", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* de */ - { - { "faddp", STi, ST, XX }, - { "fmulp", STi, ST, XX }, - { "(bad)", XX, XX, XX }, - { FGRPde_3 }, -#if UNIXWARE_COMPAT - { "fsubp", STi, ST, XX }, - { "fsubrp", STi, ST, XX }, - { "fdivp", STi, ST, XX }, - { "fdivrp", STi, ST, XX }, -#else - { "fsubrp", STi, ST, XX }, - { "fsubp", STi, ST, XX }, - { "fdivrp", STi, ST, XX }, - { "fdivp", STi, ST, XX }, -#endif - }, - /* df */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { FGRPdf_4 }, - { "fucomip",ST, STi, XX }, - { "fcomip", ST, STi, XX }, - { "(bad)", XX, XX, XX }, - }, -}; - - -static char *fgrps[][8] = { - /* d9_2 0 */ - { - "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* d9_4 1 */ - { - "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", - }, - - /* d9_5 2 */ - { - "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", - }, - - /* d9_6 3 */ - { - "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", - }, - - /* d9_7 4 */ - { - "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", - }, - - /* da_5 5 */ - { - "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* db_4 6 */ - { - "feni(287 only)","fdisi(287 only)","fNclex","fNinit", - "fNsetpm(287 only)","(bad)","(bad)","(bad)", - }, - - /* de_3 7 */ - { - "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* df_4 8 */ - { - "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, -}; - -static void -dofloat (sizeflag) - int sizeflag; -{ - const struct dis386 *dp; - unsigned char floatop; - - floatop = codep[-1]; - - if (mod != 3) - { - if (intel_syntax) - putop (float_mem_intel[(floatop - 0xd8 ) * 8 + reg], sizeflag); - else - putop (float_mem_att[(floatop - 0xd8 ) * 8 + reg], sizeflag); - obufp = op1out; - if (floatop == 0xdb) - OP_E (x_mode, sizeflag); - else if (floatop == 0xdd) - OP_E (d_mode, sizeflag); - else - OP_E (v_mode, sizeflag); - return; - } - codep++; - - dp = &float_reg[floatop - 0xd8][reg]; - if (dp->name == NULL) - { - putop (fgrps[dp->bytemode1][rm], sizeflag); - - /* instruction fnstsw is only one with strange arg */ - if (floatop == 0xdf && codep[-1] == 0xe0) - strcpy (op1out, names16[0]); - } - else - { - putop (dp->name, sizeflag); - - obufp = op1out; - if (dp->op1) - (*dp->op1)(dp->bytemode1, sizeflag); - obufp = op2out; - if (dp->op2) - (*dp->op2)(dp->bytemode2, sizeflag); - } -} - -/* ARGSUSED */ -static void -OP_ST (ignore, sizeflag) - int ignore ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - oappend ("%st"); -} - -/* ARGSUSED */ -static void -OP_STi (ignore, sizeflag) - int ignore ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - sprintf (scratchbuf, "%%st(%d)", rm); - oappend (scratchbuf); -} - - -/* capital letters in template are macros */ -static void -putop (template, sizeflag) - const char *template; - int sizeflag; -{ - const char *p; - - for (p = template; *p; p++) - { - switch (*p) - { - default: - *obufp++ = *p; - break; - case 'A': - if (intel_syntax) - break; - if (mod != 3 -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) - *obufp++ = 'b'; - break; - case 'B': - if (intel_syntax) - break; -#ifdef SUFFIX_ALWAYS - if (sizeflag & SUFFIX_ALWAYS) - *obufp++ = 'b'; -#endif - break; - case 'E': /* For jcxz/jecxz */ - if (sizeflag & AFLAG) - *obufp++ = 'e'; - break; - case 'L': - if (intel_syntax) - break; -#ifdef SUFFIX_ALWAYS - if (sizeflag & SUFFIX_ALWAYS) - *obufp++ = 'l'; -#endif - break; - case 'N': - if ((prefixes & PREFIX_FWAIT) == 0) - *obufp++ = 'n'; - else - used_prefixes |= PREFIX_FWAIT; - break; - case 'P': - if (intel_syntax) - break; - if ((prefixes & PREFIX_DATA) -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } - break; - case 'Q': - if (intel_syntax) - break; - if (mod != 3 -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } - break; - case 'R': - if (intel_syntax) - { - if (sizeflag & DFLAG) - { - *obufp++ = 'd'; - *obufp++ = 'q'; - } - else - { - *obufp++ = 'w'; - *obufp++ = 'd'; - } - } - else - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case 'S': - if (intel_syntax) - break; -#ifdef SUFFIX_ALWAYS - if (sizeflag & SUFFIX_ALWAYS) - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } -#endif - break; - case 'W': - /* operand size flag for cwtl, cbtw */ - if (sizeflag & DFLAG) - *obufp++ = 'w'; - else - *obufp++ = 'b'; - if (intel_syntax) - { - if (sizeflag & DFLAG) - { - *obufp++ = 'd'; - *obufp++ = 'e'; - } - else - { - *obufp++ = 'w'; - } - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - } - } - *obufp = 0; -} - -static void -oappend (s) - const char *s; -{ - strcpy (obufp, s); - obufp += strlen (s); -} - -static void -append_seg () -{ - if (prefixes & PREFIX_CS) - { - oappend ("%cs:"); - used_prefixes |= PREFIX_CS; - } - if (prefixes & PREFIX_DS) - { - oappend ("%ds:"); - used_prefixes |= PREFIX_DS; - } - if (prefixes & PREFIX_SS) - { - oappend ("%ss:"); - used_prefixes |= PREFIX_SS; - } - if (prefixes & PREFIX_ES) - { - oappend ("%es:"); - used_prefixes |= PREFIX_ES; - } - if (prefixes & PREFIX_FS) - { - oappend ("%fs:"); - used_prefixes |= PREFIX_FS; - } - if (prefixes & PREFIX_GS) - { - oappend ("%gs:"); - used_prefixes |= PREFIX_GS; - } -} - -static void -OP_indirE (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - if (!intel_syntax) - oappend ("*"); - OP_E (bytemode, sizeflag); -} - -static void -OP_E (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int disp; - - /* skip mod/rm byte */ - codep++; - - if (mod == 3) - { - switch (bytemode) - { - case b_mode: - oappend (names8[rm]); - break; - case w_mode: - oappend (names16[rm]); - break; - case d_mode: - oappend (names32[rm]); - break; - case v_mode: - if (sizeflag & DFLAG) - oappend (names32[rm]); - else - oappend (names16[rm]); - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case 0: - if ( !(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */)) - BadOp(); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */ - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } - return; - } - - disp = 0; - append_seg (); - - if (sizeflag & AFLAG) /* 32 bit address mode */ - { - int havesib; - int havebase; - int base; - int index = 0; - int scale = 0; - - havesib = 0; - havebase = 1; - base = rm; - - if (base == 4) - { - havesib = 1; - FETCH_DATA (the_info, codep + 1); - scale = (*codep >> 6) & 3; - index = (*codep >> 3) & 7; - base = *codep & 7; - codep++; - } - - switch (mod) - { - case 0: - if (base == 5) - { - havebase = 0; - disp = get32 (); - } - break; - case 1: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case 2: - disp = get32 (); - break; - } - - if (!intel_syntax) - if (mod != 0 || base == 5) - { - sprintf (scratchbuf, "0x%x", disp); - oappend (scratchbuf); - } - - if (havebase || (havesib && (index != 4 || scale != 0))) - { - if (intel_syntax) - { - switch (bytemode) - { - case b_mode: - oappend("BYTE PTR "); - break; - case w_mode: - oappend("WORD PTR "); - break; - case v_mode: - oappend("DWORD PTR "); - break; - case d_mode: - oappend("QWORD PTR "); - break; - case x_mode: - oappend("XWORD PTR "); - break; - default: - break; - } - } - *obufp++ = open_char; - *obufp = '\0'; - if (havebase) - oappend (names32[base]); - if (havesib) - { - if (index != 4) - { - if (intel_syntax) - { - if (havebase) - { - *obufp++ = separator_char; - *obufp = '\0'; - } - sprintf (scratchbuf, "%s", names32[index]); - } - else - sprintf (scratchbuf, ",%s", names32[index]); - oappend (scratchbuf); - } - if (!intel_syntax - || (intel_syntax - && bytemode != b_mode - && bytemode != w_mode - && bytemode != v_mode)) - { - *obufp++ = scale_char; - *obufp = '\0'; - sprintf (scratchbuf, "%d", 1 << scale); - oappend (scratchbuf); - } - } - if (intel_syntax) - if (mod != 0 || base == 5) - { - /* Don't print zero displacements */ - if (disp > 0) - { - sprintf (scratchbuf, "+%d", disp); - oappend (scratchbuf); - } - else if (disp < 0) - { - sprintf (scratchbuf, "%d", disp); - oappend (scratchbuf); - } - } - - *obufp++ = close_char; - *obufp = '\0'; - } - else if (intel_syntax) - { - if (mod != 0 || base == 5) - { - if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS)) - ; - else - { - oappend (names_seg[3]); - oappend (":"); - } - sprintf (scratchbuf, "0x%x", disp); - oappend (scratchbuf); - } - } - } - else - { /* 16 bit address mode */ - switch (mod) - { - case 0: - if (rm == 6) - { - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - } - break; - case 1: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case 2: - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - break; - } - - if (!intel_syntax) - if (mod != 0 || rm == 6) - { - sprintf (scratchbuf, "%d", disp); - oappend (scratchbuf); - } - - if (mod != 0 || rm != 6) - { - *obufp++ = open_char; - *obufp = '\0'; - oappend (index16[rm]); - *obufp++ = close_char; - *obufp = '\0'; - } - } -} - -static void -OP_G (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - switch (bytemode) - { - case b_mode: - oappend (names8[reg]); - break; - case w_mode: - oappend (names16[reg]); - break; - case d_mode: - oappend (names32[reg]); - break; - case v_mode: - if (sizeflag & DFLAG) - oappend (names32[reg]); - else - oappend (names16[reg]); - used_prefixes |= (prefixes & PREFIX_DATA); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } -} - -static int -get32 () -{ - int x = 0; - - FETCH_DATA (the_info, codep + 4); - x = *codep++ & 0xff; - x |= (*codep++ & 0xff) << 8; - x |= (*codep++ & 0xff) << 16; - x |= (*codep++ & 0xff) << 24; - return x; -} - -static int -get16 () -{ - int x = 0; - - FETCH_DATA (the_info, codep + 2); - x = *codep++ & 0xff; - x |= (*codep++ & 0xff) << 8; - return x; -} - -static void -set_op (op) - unsigned int op; -{ - op_index[op_ad] = op_ad; - op_address[op_ad] = op; -} - -static void -OP_REG (code, sizeflag) - int code; - int sizeflag; -{ - const char *s; - - switch (code) - { - case indir_dx_reg: - s = "(%dx)"; - break; - case ax_reg: case cx_reg: case dx_reg: case bx_reg: - case sp_reg: case bp_reg: case si_reg: case di_reg: - s = names16[code - ax_reg]; - break; - case es_reg: case ss_reg: case cs_reg: - case ds_reg: case fs_reg: case gs_reg: - s = names_seg[code - es_reg]; - break; - case al_reg: case ah_reg: case cl_reg: case ch_reg: - case dl_reg: case dh_reg: case bl_reg: case bh_reg: - s = names8[code - al_reg]; - break; - case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: - case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: - if (sizeflag & DFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - used_prefixes |= (prefixes & PREFIX_DATA); - break; - default: - s = INTERNAL_DISASSEMBLER_ERROR; - break; - } - oappend (s); -} - -static void -OP_I (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int op; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++ & 0xff; - break; - case v_mode: - if (sizeflag & DFLAG) - op = get32 (); - else - op = get16 (); - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case w_mode: - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - - if (intel_syntax) - sprintf (scratchbuf, "0x%x", op); - else - sprintf (scratchbuf, "$0x%x", op); - oappend (scratchbuf); - scratchbuf[0] = '\0'; -} - -static void -OP_sI (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int op; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - if ((op & 0x80) != 0) - op -= 0x100; - break; - case v_mode: - if (sizeflag & DFLAG) - op = get32 (); - else - { - op = get16(); - if ((op & 0x8000) != 0) - op -= 0x10000; - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case w_mode: - op = get16 (); - if ((op & 0x8000) != 0) - op -= 0x10000; - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - if (intel_syntax) - sprintf (scratchbuf, "%d", op); - else - sprintf (scratchbuf, "$0x%x", op); - oappend (scratchbuf); -} - -static void -OP_J (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int disp; - int mask = -1; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case v_mode: - if (sizeflag & DFLAG) - disp = get32 (); - else - { - disp = get16 (); - /* for some reason, a data16 prefix on a jump instruction - means that the pc is masked to 16 bits after the - displacement is added! */ - mask = 0xffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - disp = (start_pc + codep - start_codep + disp) & mask; - set_op (disp); - sprintf (scratchbuf, "0x%x", disp); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_SEG (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - static char *sreg[] = { - "%es","%cs","%ss","%ds","%fs","%gs","%?","%?", - }; - - oappend (sreg[reg]); -} - -/* ARGSUSED */ -static void -OP_DIR (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag; -{ - int seg, offset; - - if (sizeflag & DFLAG) - { - offset = get32 (); - seg = get16 (); - } - else - { - offset = get16 (); - seg = get16 (); - } - used_prefixes |= (prefixes & PREFIX_DATA); - sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_OFF (ignore, sizeflag) - int ignore ATTRIBUTE_UNUSED; - int sizeflag; -{ - int off; - - append_seg (); - - if (sizeflag & AFLAG) - off = get32 (); - else - off = get16 (); - - if (intel_syntax) - { - if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) - { - oappend (names_seg[3]); - oappend (":"); - } - } - sprintf (scratchbuf, "0x%x", off); - oappend (scratchbuf); -} - -static void -ptr_reg (code, sizeflag) - int code; - int sizeflag; -{ - const char *s; - oappend ("("); - if (sizeflag & AFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - oappend (s); - oappend (")"); -} - -static void -OP_ESreg (code, sizeflag) - int code; - int sizeflag; -{ - oappend ("%es:"); - ptr_reg (code, sizeflag); -} - -static void -OP_DSreg (code, sizeflag) - int code; - int sizeflag; -{ - if ((prefixes - & (PREFIX_CS - | PREFIX_DS - | PREFIX_SS - | PREFIX_ES - | PREFIX_FS - | PREFIX_GS)) == 0) - prefixes |= PREFIX_DS; - append_seg(); - ptr_reg (code, sizeflag); -} - -/* ARGSUSED */ -static void -OP_C (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - sprintf (scratchbuf, "%%cr%d", reg); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_D (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - sprintf (scratchbuf, "%%db%d", reg); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_T (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - sprintf (scratchbuf, "%%tr%d", reg); - oappend (scratchbuf); -} - -static void -OP_Rd (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - if (mod == 3) - OP_E (bytemode, sizeflag); - else - BadOp(); -} - -static void -OP_MMX (ignore, sizeflag) - int ignore ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - sprintf (scratchbuf, "%%mm%d", reg); - oappend (scratchbuf); -} - -static void -OP_XMM (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - sprintf (scratchbuf, "%%xmm%d", reg); - oappend (scratchbuf); -} - -static void -OP_EM (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - if (mod != 3) - { - OP_E (bytemode, sizeflag); - return; - } - - codep++; - sprintf (scratchbuf, "%%mm%d", rm); - oappend (scratchbuf); -} - -static void -OP_EX (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - if (mod != 3) - { - OP_E (bytemode, sizeflag); - return; - } - - codep++; - sprintf (scratchbuf, "%%xmm%d", rm); - oappend (scratchbuf); -} - -static void -OP_MS (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - if (mod == 3) - OP_EM (bytemode, sizeflag); - else - BadOp(); -} - -static const char *Suffix3DNow[] = { -/* 00 */ NULL, NULL, NULL, NULL, -/* 04 */ NULL, NULL, NULL, NULL, -/* 08 */ NULL, NULL, NULL, NULL, -/* 0C */ "pi2fw", "pi2fd", NULL, NULL, -/* 10 */ NULL, NULL, NULL, NULL, -/* 14 */ NULL, NULL, NULL, NULL, -/* 18 */ NULL, NULL, NULL, NULL, -/* 1C */ "pf2iw", "pf2id", NULL, NULL, -/* 20 */ NULL, NULL, NULL, NULL, -/* 24 */ NULL, NULL, NULL, NULL, -/* 28 */ NULL, NULL, NULL, NULL, -/* 2C */ NULL, NULL, NULL, NULL, -/* 30 */ NULL, NULL, NULL, NULL, -/* 34 */ NULL, NULL, NULL, NULL, -/* 38 */ NULL, NULL, NULL, NULL, -/* 3C */ NULL, NULL, NULL, NULL, -/* 40 */ NULL, NULL, NULL, NULL, -/* 44 */ NULL, NULL, NULL, NULL, -/* 48 */ NULL, NULL, NULL, NULL, -/* 4C */ NULL, NULL, NULL, NULL, -/* 50 */ NULL, NULL, NULL, NULL, -/* 54 */ NULL, NULL, NULL, NULL, -/* 58 */ NULL, NULL, NULL, NULL, -/* 5C */ NULL, NULL, NULL, NULL, -/* 60 */ NULL, NULL, NULL, NULL, -/* 64 */ NULL, NULL, NULL, NULL, -/* 68 */ NULL, NULL, NULL, NULL, -/* 6C */ NULL, NULL, NULL, NULL, -/* 70 */ NULL, NULL, NULL, NULL, -/* 74 */ NULL, NULL, NULL, NULL, -/* 78 */ NULL, NULL, NULL, NULL, -/* 7C */ NULL, NULL, NULL, NULL, -/* 80 */ NULL, NULL, NULL, NULL, -/* 84 */ NULL, NULL, NULL, NULL, -/* 88 */ NULL, NULL, "pfnacc", NULL, -/* 8C */ NULL, NULL, "pfpnacc", NULL, -/* 90 */ "pfcmpge", NULL, NULL, NULL, -/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", -/* 98 */ NULL, NULL, "pfsub", NULL, -/* 9C */ NULL, NULL, "pfadd", NULL, -/* A0 */ "pfcmpgt", NULL, NULL, NULL, -/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", -/* A8 */ NULL, NULL, "pfsubr", NULL, -/* AC */ NULL, NULL, "pfacc", NULL, -/* B0 */ "pfcmpeq", NULL, NULL, NULL, -/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw", -/* B8 */ NULL, NULL, NULL, "pswapd", -/* BC */ NULL, NULL, NULL, "pavgusb", -/* C0 */ NULL, NULL, NULL, NULL, -/* C4 */ NULL, NULL, NULL, NULL, -/* C8 */ NULL, NULL, NULL, NULL, -/* CC */ NULL, NULL, NULL, NULL, -/* D0 */ NULL, NULL, NULL, NULL, -/* D4 */ NULL, NULL, NULL, NULL, -/* D8 */ NULL, NULL, NULL, NULL, -/* DC */ NULL, NULL, NULL, NULL, -/* E0 */ NULL, NULL, NULL, NULL, -/* E4 */ NULL, NULL, NULL, NULL, -/* E8 */ NULL, NULL, NULL, NULL, -/* EC */ NULL, NULL, NULL, NULL, -/* F0 */ NULL, NULL, NULL, NULL, -/* F4 */ NULL, NULL, NULL, NULL, -/* F8 */ NULL, NULL, NULL, NULL, -/* FC */ NULL, NULL, NULL, NULL, -}; - -static void -OP_3DNowSuffix (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - const char *mnemonic; - - FETCH_DATA (the_info, codep + 1); - /* AMD 3DNow! instructions are specified by an opcode suffix in the - place where an 8-bit immediate would normally go. ie. the last - byte of the instruction. */ - obufp = obuf + strlen(obuf); - mnemonic = Suffix3DNow[*codep++ & 0xff]; - if (mnemonic) - oappend (mnemonic); - else - { - /* Since a variable sized modrm/sib chunk is between the start - of the opcode (0x0f0f) and the opcode suffix, we need to do - all the modrm processing first, and don't know until now that - we have a bad opcode. This necessitates some cleaning up. */ - op1out[0] = '\0'; - op2out[0] = '\0'; - BadOp(); - } -} - - -static const char *simd_cmp_op [] = { - "eq", - "lt", - "le", - "unord", - "neq", - "nlt", - "nle", - "ord" -}; - -static void -OP_SIMD_Suffix (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; -{ - unsigned int cmp_type; - - FETCH_DATA (the_info, codep + 1); - obufp = obuf + strlen(obuf); - cmp_type = *codep++ & 0xff; - if (cmp_type < 8) - { - sprintf (scratchbuf, "cmp%s%cs", - simd_cmp_op[cmp_type], - prefixes & PREFIX_REPZ ? 's' : 'p'); - used_prefixes |= (prefixes & PREFIX_REPZ); - oappend (scratchbuf); - } - else - { - /* We have a bad extension byte. Clean up. */ - op1out[0] = '\0'; - op2out[0] = '\0'; - BadOp(); - } -} - -static void -SIMD_Fixup (extrachar, sizeflag) - int extrachar; - int sizeflag ATTRIBUTE_UNUSED; -{ - /* Change movlps/movhps to movhlps/movlhps for 2 register operand - forms of these instructions. */ - if (mod == 3) - { - char *p = obuf + strlen(obuf); - *(p+1) = '\0'; - *p = *(p-1); - *(p-1) = *(p-2); - *(p-2) = *(p-3); - *(p-3) = extrachar; - } -} - -static void BadOp (void) -{ - codep = insn_codep + 1; /* throw away prefixes and 1st. opcode byte */ - oappend ("(bad)"); -} diff --git a/contrib/binutils/opcodes/opintl.h b/contrib/binutils/opcodes/opintl.h deleted file mode 100644 index a590160408180..0000000000000 --- a/contrib/binutils/opcodes/opintl.h +++ /dev/null @@ -1,30 +0,0 @@ -/* opintl.h - opcodes specific header for gettext code. - Copyright (C) 1998, 1999 Free Software Foundation, Inc. - - Written by Tom Tromey <tromey@cygnus.com> - - This file is part of the opcodes library used by GAS and the GNU binutils. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#ifdef ENABLE_NLS -# include <libintl.h> -# define _(String) dgettext (PACKAGE, String) -# ifdef gettext_noop -# define N_(String) gettext_noop (String) -# else -# define N_(String) (String) -# endif -#else -/* Stubs that do something close enough. */ -# define textdomain(String) (String) -# define gettext(String) (String) -# define dgettext(Domain,Message) (Message) -# define dcgettext(Domain,Message,Type) (Message) -# define bindtextdomain(Domain,Directory) (Domain) -# define _(String) (String) -# define N_(String) (String) -#endif diff --git a/contrib/binutils/opcodes/po/Make-in b/contrib/binutils/opcodes/po/Make-in deleted file mode 100644 index 0552db1feef38..0000000000000 --- a/contrib/binutils/opcodes/po/Make-in +++ /dev/null @@ -1,251 +0,0 @@ -# Makefile for program source directory in GNU NLS utilities package. -# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper <drepper@gnu.ai.mit.edu> -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -PACKAGE = @PACKAGE@ -VERSION = @VERSION@ - -SHELL = /bin/sh -@SET_MAKE@ - -srcdir = @srcdir@ -top_srcdir = @top_srcdir@ -VPATH = @srcdir@ - -prefix = @prefix@ -exec_prefix = @exec_prefix@ -datadir = $(prefix)/@DATADIRNAME@ -localedir = $(datadir)/locale -gnulocaledir = $(prefix)/share/locale -gettextsrcdir = $(prefix)/share/gettext/po -subdir = po - -INSTALL = @INSTALL@ -INSTALL_DATA = @INSTALL_DATA@ -MKINSTALLDIRS = @MKINSTALLDIRS@ - -CC = @CC@ -GENCAT = @GENCAT@ -GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ -MSGFMT = @MSGFMT@ -XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ -MSGMERGE = PATH=../src:$$PATH msgmerge - -DEFS = @DEFS@ -CFLAGS = @CFLAGS@ -CPPFLAGS = @CPPFLAGS@ - -INCLUDES = -I.. -I$(top_srcdir)/intl - -COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) - -SOURCES = cat-id-tbl.c -POFILES = @POFILES@ -GMOFILES = @GMOFILES@ -DISTFILES = ChangeLog Makefile.in.in POTFILES.in $(PACKAGE).pot \ -stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) - -POTFILES = \ - -CATALOGS = @CATALOGS@ -CATOBJEXT = @CATOBJEXT@ -INSTOBJEXT = @INSTOBJEXT@ - -.SUFFIXES: -.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat - -.c.o: - $(COMPILE) $< - -.po.pox: - $(MAKE) $(PACKAGE).pot - $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox - -.po.mo: - $(MSGFMT) -o $@ $< - -.po.gmo: - file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \ - && rm -f $$file && $(GMSGFMT) -o $$file $< - -.po.cat: - sed -f ../intl/po2msg.sed < $< > $*.msg \ - && rm -f $@ && $(GENCAT) $@ $*.msg - - -all: all-@USE_NLS@ - -all-yes: $(CATALOGS) @MAINT@ $(PACKAGE).pot -all-no: - -$(srcdir)/$(PACKAGE).pot: $(POTFILES) - $(XGETTEXT) --default-domain=$(PACKAGE) --directory=$(top_srcdir) \ - --add-comments --keyword=_ --keyword=N_ \ - --files-from=$(srcdir)/POTFILES.in - rm -f $(srcdir)/$(PACKAGE).pot - mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot - -$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: -$(srcdir)/stamp-cat-id: $(PACKAGE).pot - rm -f cat-id-tbl.tmp - sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ - | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp - if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ - rm cat-id-tbl.tmp; \ - else \ - echo cat-id-tbl.c changed; \ - rm -f $(srcdir)/cat-id-tbl.c; \ - mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ - fi - cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id - - -install: install-exec install-data -install-exec: -install-info: -install-data: install-data-@USE_NLS@ -install-data-no: all -install-data-yes: all - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(datadir); \ - else \ - $(top_srcdir)/mkinstalldirs $(datadir); \ - fi - @catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - case "$$cat" in \ - *.gmo) destdir=$(gnulocaledir);; \ - *) destdir=$(localedir);; \ - esac; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - dir=$$destdir/$$lang/LC_MESSAGES; \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $$dir; \ - else \ - $(top_srcdir)/mkinstalldirs $$dir; \ - fi; \ - if test -r $$cat; then \ - $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - else \ - $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - fi; \ - if test -r $$cat.m; then \ - $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - if test -r $(srcdir)/$$cat.m ; then \ - $(INSTALL_DATA) $(srcdir)/$$cat.m \ - $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - true; \ - fi; \ - fi; \ - done - if test "$(PACKAGE)" = "gettext"; then \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(gettextsrcdir); \ - else \ - $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \ - fi; \ - $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ - $(gettextsrcdir)/Makefile.in.in; \ - else \ - : ; \ - fi - -# Define this as empty until I found a useful application. -installcheck: - -uninstall: - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - done - rm -f $(gettextsrcdir)/po-Makefile.in.in - -check: all - -cat-id-tbl.o: ../intl/libgettext.h - -dvi info tags TAGS ID: - -mostlyclean: - rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp - rm -fr *.o - -clean: mostlyclean - -distclean: clean - rm -f Makefile Makefile.in POTFILES *.mo *.msg *.cat *.cat.m - -maintainer-clean: distclean - @echo "This command is intended for maintainers to use;" - @echo "it deletes files that may require special tools to rebuild." - rm -f $(GMOFILES) - -distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) -dist distdir: update-po $(DISTFILES) - dists="$(DISTFILES)"; \ - for file in $$dists; do \ - ln $(srcdir)/$$file $(distdir) 2> /dev/null \ - || cp -p $(srcdir)/$$file $(distdir); \ - done - -update-po: Makefile - $(MAKE) $(PACKAGE).pot - PATH=`pwd`/../src:$$PATH; \ - cd $(srcdir); \ - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - mv $$lang.po $$lang.old.po; \ - echo "$$lang:"; \ - if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ - rm -f $$lang.old.po; \ - else \ - echo "msgmerge for $$cat failed!"; \ - rm -f $$lang.po; \ - mv $$lang.old.po $$lang.po; \ - fi; \ - done - -POTFILES: POTFILES.in - ( if test 'x$(srcdir)' != 'x.'; then \ - posrcprefix='$(top_srcdir)/'; \ - else \ - posrcprefix="../"; \ - fi; \ - rm -f $@-t $@ \ - && (sed -e '/^#/d' -e '/^[ ]*$$/d' \ - -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ - | sed -e '$$s/\\$$//') > $@-t \ - && chmod a-w $@-t \ - && mv $@-t $@ ) - -POTFILES.in: @MAINT@ ../Makefile - cd .. && $(MAKE) po/POTFILES.in - -Makefile: Make-in ../config.status POTFILES - cd .. \ - && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ - CONFIG_HEADERS= $(SHELL) ./config.status - -# Tell versions [3.59,3.63) of GNU make not to export all variables. -# Otherwise a system limit (for SysV at least) may be exceeded. -.NOEXPORT: diff --git a/contrib/binutils/opcodes/po/POTFILES.in b/contrib/binutils/opcodes/po/POTFILES.in deleted file mode 100644 index f88ddb1c38153..0000000000000 --- a/contrib/binutils/opcodes/po/POTFILES.in +++ /dev/null @@ -1,73 +0,0 @@ -a29k-dis.c -alpha-dis.c -alpha-opc.c -arc-dis.c -arc-opc.c -arm-dis.c -arm-opc.h -avr-dis.c -cgen-asm.c -cgen-dis.c -cgen-opc.c -d10v-dis.c -d10v-opc.c -d30v-dis.c -d30v-opc.c -disassemble.c -dis-buf.c -fr30-asm.c -fr30-desc.c -fr30-desc.h -fr30-dis.c -fr30-ibld.c -fr30-opc.c -fr30-opc.h -h8300-dis.c -h8500-dis.c -h8500-opc.h -hppa-dis.c -i370-dis.c -i370-opc.c -i386-dis.c -i960-dis.c -m10200-dis.c -m10200-opc.c -m10300-dis.c -m10300-opc.c -m32r-asm.c -m32r-desc.c -m32r-desc.h -m32r-dis.c -m32r-ibld.c -m32r-opc.c -m32r-opc.h -m32r-opinst.c -m68k-dis.c -m68k-opc.c -m88k-dis.c -mcore-dis.c -mcore-opc.h -mips16-opc.c -mips-dis.c -mips-opc.c -ns32k-dis.c -pj-dis.c -pj-opc.c -ppc-dis.c -ppc-opc.c -sh-dis.c -sh-opc.h -sparc-dis.c -sparc-opc.c -sysdep.h -tic30-dis.c -tic80-dis.c -tic80-opc.c -v850-dis.c -v850-opc.c -vax-dis.c -w65-dis.c -w65-opc.h -z8k-dis.c -z8kgen.c -z8k-opc.h diff --git a/contrib/binutils/opcodes/po/opcodes.pot b/contrib/binutils/opcodes/po/opcodes.pot deleted file mode 100644 index c5c26b891a35d..0000000000000 --- a/contrib/binutils/opcodes/po/opcodes.pot +++ /dev/null @@ -1,345 +0,0 @@ -# SOME DESCRIPTIVE TITLE. -# Copyright (C) YEAR Free Software Foundation, Inc. -# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR. -# -#, fuzzy -msgid "" -msgstr "" -"Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2000-04-04 22:10+0930\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" -"Language-Team: LANGUAGE <LL@li.org>\n" -"MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=CHARSET\n" -"Content-Transfer-Encoding: ENCODING\n" - -#: alpha-opc.c:335 -msgid "branch operand unaligned" -msgstr "" - -#: alpha-opc.c:358 alpha-opc.c:380 -msgid "jump hint unaligned" -msgstr "" - -#: arc-dis.c:231 -msgid "*unknown*" -msgstr "" - -#: arc-opc.c:629 -msgid "unable to fit different valued constants into instruction" -msgstr "" - -#: arc-opc.c:639 -msgid "auxiliary register not allowed here" -msgstr "" - -#: arc-opc.c:652 -#, c-format -msgid "invalid register number `%d'" -msgstr "" - -#: arc-opc.c:775 -#, c-format -msgid "value won't fit in range %ld - %ld" -msgstr "" - -#: arc-opc.c:871 -msgid "branch address not on 4 byte boundary" -msgstr "" - -#: arm-dis.c:470 -msgid "<illegal precision>" -msgstr "" - -#: arm-dis.c:882 -#, c-format -msgid "Unrecognised register name set: %s\n" -msgstr "" - -#: arm-dis.c:889 -#, c-format -msgid "Unrecognised disassembler option: %s\n" -msgstr "" - -#: arm-dis.c:1053 -msgid "" -"\n" -"The following ARM specific disassembler options are supported for use with\n" -"the -M switch:\n" -msgstr "" - -#: cgen-asm.c:224 -msgid "unrecognized keyword/register name" -msgstr "" - -#: cgen-asm.c:332 fr30-ibld.c:223 m32r-ibld.c:227 -#, c-format -msgid "operand out of range (%ld not between %ld and %ld)" -msgstr "" - -#: cgen-asm.c:353 -#, c-format -msgid "operand out of range (%lu not between %lu and %lu)" -msgstr "" - -#: d30v-dis.c:305 -#, c-format -msgid "<unknown register %d>" -msgstr "" - -#. Can't happen. -#: dis-buf.c:56 -#, c-format -msgid "Unknown error %d\n" -msgstr "" - -#: dis-buf.c:61 -#, c-format -msgid "Address 0x%x is out of bounds.\n" -msgstr "" - -#: fr30-asm.c:305 m32r-asm.c:313 -#, c-format -msgid "Unrecognized field %d while parsing.\n" -msgstr "" - -#. We couldn't parse it. -#: fr30-asm.c:369 fr30-asm.c:373 fr30-asm.c:447 m32r-asm.c:377 m32r-asm.c:381 -#: m32r-asm.c:455 -msgid "unrecognized instruction" -msgstr "" - -#. Syntax char didn't match. Can't be this insn. -#. FIXME: would like to return something like -#. "expected char `c'" -#: fr30-asm.c:415 m32r-asm.c:423 -msgid "syntax error" -msgstr "" - -#: fr30-asm.c:441 m32r-asm.c:449 -msgid "junk at end of line" -msgstr "" - -#: fr30-asm.c:534 m32r-asm.c:552 -#, c-format -msgid "bad instruction `%.50s...'" -msgstr "" - -#: fr30-asm.c:537 m32r-asm.c:555 -#, c-format -msgid "bad instruction `%.50s'" -msgstr "" - -#: fr30-dis.c:300 m32r-dis.c:239 -#, c-format -msgid "Unrecognized field %d while printing insn.\n" -msgstr "" - -#: fr30-ibld.c:210 m32r-ibld.c:211 -#, c-format -msgid "operand out of range (%lu not between 0 and %lu)" -msgstr "" - -#: fr30-ibld.c:745 m32r-ibld.c:679 -#, c-format -msgid "Unrecognized field %d while building insn.\n" -msgstr "" - -#: fr30-ibld.c:947 m32r-ibld.c:809 -#, c-format -msgid "Unrecognized field %d while decoding insn.\n" -msgstr "" - -#: fr30-ibld.c:1091 m32r-ibld.c:914 -#, c-format -msgid "Unrecognized field %d while getting int operand.\n" -msgstr "" - -#: fr30-ibld.c:1220 m32r-ibld.c:1004 -#, c-format -msgid "Unrecognized field %d while getting vma operand.\n" -msgstr "" - -#: fr30-ibld.c:1349 m32r-ibld.c:1097 -#, c-format -msgid "Unrecognized field %d while setting int operand.\n" -msgstr "" - -#: fr30-ibld.c:1471 m32r-ibld.c:1183 -#, c-format -msgid "Unrecognized field %d while setting vma operand.\n" -msgstr "" - -#: h8300-dis.c:404 -#, c-format -msgid "Hmmmm %x" -msgstr "" - -#: h8300-dis.c:416 -#, c-format -msgid "Don't understand %x \n" -msgstr "" - -#: h8500-dis.c:139 -#, c-format -msgid "can't cope with insert %d\n" -msgstr "" - -#. Couldn't understand anything -#: h8500-dis.c:344 -#, c-format -msgid "%02x\t\t*unknown*" -msgstr "" - -#: m10200-dis.c:199 -#, c-format -msgid "unknown\t0x%02x" -msgstr "" - -#: m10200-dis.c:339 -#, c-format -msgid "unknown\t0x%04lx" -msgstr "" - -#: m10300-dis.c:680 -#, c-format -msgid "unknown\t0x%04x" -msgstr "" - -#: m68k-dis.c:410 -#, c-format -msgid "<internal error in opcode table: %s %s>\n" -msgstr "" - -#: m68k-dis.c:988 -#, c-format -msgid "<function code %d>" -msgstr "" - -#: m88k-dis.c:273 -#, c-format -msgid "# <dis error: %08x>" -msgstr "" - -#: mips-dis.c:237 -#, c-format -msgid "# internal error, undefined modifier(%c)" -msgstr "" - -#. I and Z are output operands and can`t be immediate -#. * A is an address and we can`t have the address of -#. * an immediate either. We don't know how much to increase -#. * aoffsetp by since whatever generated this is broken -#. * anyway! -#. -#: ns32k-dis.c:618 -msgid "$<undefined>" -msgstr "" - -#: ppc-opc.c:586 ppc-opc.c:617 -msgid "invalid conditional option" -msgstr "" - -#: ppc-opc.c:619 -msgid "attempt to set y bit when using + or - modifier" -msgstr "" - -#: ppc-opc.c:674 -msgid "ignoring least significant bits in branch offset" -msgstr "" - -#: ppc-opc.c:709 ppc-opc.c:746 -msgid "illegal bitmask" -msgstr "" - -#: ppc-opc.c:815 -msgid "value out of range" -msgstr "" - -#: ppc-opc.c:889 -msgid "index register in load range" -msgstr "" - -#: ppc-opc.c:904 -msgid "invalid register operand when updating" -msgstr "" - -#. Mark as non-valid instruction -#: sparc-dis.c:744 -msgid "unknown" -msgstr "" - -#: sparc-dis.c:816 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" - -#: sparc-dis.c:827 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" - -#: sparc-dis.c:876 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" -msgstr "" - -#: v850-dis.c:221 -#, c-format -msgid "unknown operand shift: %x\n" -msgstr "" - -#: v850-dis.c:233 -#, c-format -msgid "unknown pop reg: %d\n" -msgstr "" - -#. The functions used to insert and extract complicated operands. -#. Note: There is a conspiracy between these functions and -#. v850_insert_operand() in gas/config/tc-v850.c. Error messages -#. containing the string 'out of range' will be ignored unless a -#. specific command line option is given to GAS. -#: v850-opc.c:46 -msgid "displacement value is not in range and is not aligned" -msgstr "" - -#: v850-opc.c:47 -msgid "displacement value is out of range" -msgstr "" - -#: v850-opc.c:48 -msgid "displacement value is not aligned" -msgstr "" - -#: v850-opc.c:50 -msgid "immediate value is out of range" -msgstr "" - -#: v850-opc.c:61 -msgid "branch value not in range and to odd offset" -msgstr "" - -#: v850-opc.c:63 v850-opc.c:95 -msgid "branch value out of range" -msgstr "" - -#: v850-opc.c:66 v850-opc.c:98 -msgid "branch to odd offset" -msgstr "" - -#: v850-opc.c:93 -msgid "branch value not in range and to an odd offset" -msgstr "" - -#: v850-opc.c:321 -msgid "invalid register for stack adjustment" -msgstr "" - -#: v850-opc.c:343 -msgid "immediate value not in range and not even" -msgstr "" - -#: v850-opc.c:348 -msgid "immediate value must be even" -msgstr "" diff --git a/contrib/binutils/opcodes/ppc-dis.c b/contrib/binutils/opcodes/ppc-dis.c deleted file mode 100644 index f2566328548be..0000000000000 --- a/contrib/binutils/opcodes/ppc-dis.c +++ /dev/null @@ -1,237 +0,0 @@ -/* ppc-dis.c -- Disassemble PowerPC instructions - Copyright 1994 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/ppc.h" - -/* This file provides several disassembler functions, all of which use - the disassembler interface defined in dis-asm.h. Several functions - are provided because this file handles disassembly for the PowerPC - in both big and little endian mode and also for the POWER (RS/6000) - chip. */ - -static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *, - int bigendian, int dialect)); - -/* Print a big endian PowerPC instruction. For convenience, also - disassemble instructions supported by the Motorola PowerPC 601. */ - -int -print_insn_big_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return print_insn_powerpc (memaddr, info, 1, - PPC_OPCODE_PPC | PPC_OPCODE_601); -} - -/* Print a little endian PowerPC instruction. For convenience, also - disassemble instructions supported by the Motorola PowerPC 601. */ - -int -print_insn_little_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return print_insn_powerpc (memaddr, info, 0, - PPC_OPCODE_PPC | PPC_OPCODE_601); -} - -/* Print a POWER (RS/6000) instruction. */ - -int -print_insn_rs6000 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); -} - -/* Print a PowerPC or POWER instruction. */ - -static int -print_insn_powerpc (memaddr, info, bigendian, dialect) - bfd_vma memaddr; - struct disassemble_info *info; - int bigendian; - int dialect; -{ - bfd_byte buffer[4]; - int status; - unsigned long insn; - const struct powerpc_opcode *opcode; - const struct powerpc_opcode *opcode_end; - unsigned long op; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - if (bigendian) - insn = bfd_getb32 (buffer); - else - insn = bfd_getl32 (buffer); - - /* Get the major opcode of the instruction. */ - op = PPC_OP (insn); - - /* Find the first match in the opcode table. We could speed this up - a bit by doing a binary search on the major opcode. */ - opcode_end = powerpc_opcodes + powerpc_num_opcodes; - for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) - { - unsigned long table_op; - const unsigned char *opindex; - const struct powerpc_operand *operand; - int invalid; - int need_comma; - int need_paren; - - table_op = PPC_OP (opcode->opcode); - if (op < table_op) - break; - if (op > table_op) - continue; - - if ((insn & opcode->mask) != opcode->opcode - || (opcode->flags & dialect) == 0) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - operand = powerpc_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - (*info->fprintf_func) (info->stream, "%s", opcode->name); - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "\t"); - - /* Now extract and print the operands. */ - need_comma = 0; - need_paren = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - long value; - - operand = powerpc_operands + *opindex; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & PPC_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & PPC_OPERAND_SIGNED) != 0 - && (value & (1 << (operand->bits - 1))) != 0) - value -= 1 << operand->bits; - } - - /* If the operand is optional, and the value is zero, don't - print anything. */ - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 - && (operand->flags & PPC_OPERAND_NEXT) == 0 - && value == 0) - continue; - - if (need_comma) - { - (*info->fprintf_func) (info->stream, ","); - need_comma = 0; - } - - /* Print the operand as directed by the flags. */ - if ((operand->flags & PPC_OPERAND_GPR) != 0) - (*info->fprintf_func) (info->stream, "r%ld", value); - else if ((operand->flags & PPC_OPERAND_FPR) != 0) - (*info->fprintf_func) (info->stream, "f%ld", value); - else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) - (*info->print_address_func) (memaddr + value, info); - else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if ((operand->flags & PPC_OPERAND_CR) == 0 - || (dialect & PPC_OPCODE_PPC) == 0) - (*info->fprintf_func) (info->stream, "%ld", value); - else - { - if (operand->bits == 3) - (*info->fprintf_func) (info->stream, "cr%d", value); - else - { - static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; - int cr; - int cc; - - cr = value >> 2; - if (cr != 0) - (*info->fprintf_func) (info->stream, "4*cr%d", cr); - cc = value & 3; - if (cc != 0) - { - if (cr != 0) - (*info->fprintf_func) (info->stream, "+"); - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); - } - } - } - - if (need_paren) - { - (*info->fprintf_func) (info->stream, ")"); - need_paren = 0; - } - - if ((operand->flags & PPC_OPERAND_PARENS) == 0) - need_comma = 1; - else - { - (*info->fprintf_func) (info->stream, "("); - need_paren = 1; - } - } - - /* We have found and printed an instruction; return. */ - return 4; - } - - /* We could not find a match. */ - (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); - - return 4; -} diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c deleted file mode 100644 index 02fb7a4edf6d3..0000000000000 --- a/contrib/binutils/opcodes/ppc-opc.c +++ /dev/null @@ -1,3124 +0,0 @@ -/* ppc-opc.c -- PowerPC opcode list - Copyright (c) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/ppc.h" -#include "opintl.h" - -/* This file holds the PowerPC opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ - -/* Local insertion and extraction functions. */ - -static unsigned long insert_bat PARAMS ((unsigned long, long, const char **)); -static long extract_bat PARAMS ((unsigned long, int *)); -static unsigned long insert_bba PARAMS ((unsigned long, long, const char **)); -static long extract_bba PARAMS ((unsigned long, int *)); -static unsigned long insert_bd PARAMS ((unsigned long, long, const char **)); -static long extract_bd PARAMS ((unsigned long, int *)); -static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **)); -static long extract_bdm PARAMS ((unsigned long, int *)); -static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **)); -static long extract_bdp PARAMS ((unsigned long, int *)); -static int valid_bo PARAMS ((long)); -static unsigned long insert_bo PARAMS ((unsigned long, long, const char **)); -static long extract_bo PARAMS ((unsigned long, int *)); -static unsigned long insert_boe PARAMS ((unsigned long, long, const char **)); -static long extract_boe PARAMS ((unsigned long, int *)); -static unsigned long insert_ds PARAMS ((unsigned long, long, const char **)); -static long extract_ds PARAMS ((unsigned long, int *)); -static unsigned long insert_li PARAMS ((unsigned long, long, const char **)); -static long extract_li PARAMS ((unsigned long, int *)); -static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **)); -static long extract_mbe PARAMS ((unsigned long, int *)); -static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **)); -static long extract_mb6 PARAMS ((unsigned long, int *)); -static unsigned long insert_nb PARAMS ((unsigned long, long, const char **)); -static long extract_nb PARAMS ((unsigned long, int *)); -static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **)); -static long extract_nsi PARAMS ((unsigned long, int *)); -static unsigned long insert_ral PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ram PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ras PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **)); -static long extract_rbs PARAMS ((unsigned long, int *)); -static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **)); -static long extract_sh6 PARAMS ((unsigned long, int *)); -static unsigned long insert_spr PARAMS ((unsigned long, long, const char **)); -static long extract_spr PARAMS ((unsigned long, int *)); -static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **)); -static long extract_tbr PARAMS ((unsigned long, int *)); - -/* The operands table. - - The fields are bits, shift, insert, extract, flags. - - We used to put parens around the various additions, like the one - for BA just below. However, that caused trouble with feeble - compilers with a limit on depth of a parenthesized expression, like - (reportedly) the compiler in Microsoft Developer Studio 5. So we - omit the parens, since the macros are never used in a context where - the addition will be ambiguous. */ - -const struct powerpc_operand powerpc_operands[] = -{ - /* The zero index is used to indicate the end of the list of - operands. */ -#define UNUSED 0 - { 0, 0, 0, 0, 0 }, - - /* The BA field in an XL form instruction. */ -#define BA UNUSED + 1 -#define BA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_CR }, - - /* The BA field in an XL form instruction when it must be the same - as the BT field in the same instruction. */ -#define BAT BA + 1 - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, - - /* The BB field in an XL form instruction. */ -#define BB BAT + 1 -#define BB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_CR }, - - /* The BB field in an XL form instruction when it must be the same - as the BA field in the same instruction. */ -#define BBA BB + 1 - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, - - /* The BD field in a B form instruction. The lower two bits are - forced to zero. */ -#define BD BBA + 1 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when absolute addressing is - used. */ -#define BDA BD + 1 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDM BDA + 1 - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used - and absolute address is used. */ -#define BDMA BDM + 1 - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDP BDMA + 1 - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used - and absolute addressing is used. */ -#define BDPA BDP + 1 - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BF field in an X or XL form instruction. */ -#define BF BDPA + 1 - { 3, 23, 0, 0, PPC_OPERAND_CR }, - - /* An optional BF field. This is used for comparison instructions, - in which an omitted BF field is taken as zero. */ -#define OBF BF + 1 - { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The BFA field in an X or XL form instruction. */ -#define BFA OBF + 1 - { 3, 18, 0, 0, PPC_OPERAND_CR }, - - /* The BI field in a B form or XL form instruction. */ -#define BI BFA + 1 -#define BI_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_CR }, - - /* The BO field in a B form instruction. Certain values are - illegal. */ -#define BO BI + 1 -#define BO_MASK (0x1f << 21) - { 5, 21, insert_bo, extract_bo, 0 }, - - /* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. */ -#define BOE BO + 1 - { 5, 21, insert_boe, extract_boe, 0 }, - - /* The BT field in an X or XL form instruction. */ -#define BT BOE + 1 - { 5, 21, 0, 0, PPC_OPERAND_CR }, - - /* The condition register number portion of the BI field in a B form - or XL form instruction. This is used for the extended - conditional branch mnemonics, which set the lower two bits of the - BI field. This field is optional. */ -#define CR BT + 1 - { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The D field in a D form instruction. This is a displacement off - a register, and implies that the next operand is a register in - parentheses. */ -#define D CR + 1 - { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ -#define DS D + 1 - { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The E field in a wrteei instruction. */ -#define E DS + 1 - { 1, 15, 0, 0, 0 }, - - /* The FL1 field in a POWER SC form instruction. */ -#define FL1 E + 1 - { 4, 12, 0, 0, 0 }, - - /* The FL2 field in a POWER SC form instruction. */ -#define FL2 FL1 + 1 - { 3, 2, 0, 0, 0 }, - - /* The FLM field in an XFL form instruction. */ -#define FLM FL2 + 1 - { 8, 17, 0, 0, 0 }, - - /* The FRA field in an X or A form instruction. */ -#define FRA FLM + 1 -#define FRA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_FPR }, - - /* The FRB field in an X or A form instruction. */ -#define FRB FRA + 1 -#define FRB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_FPR }, - - /* The FRC field in an A form instruction. */ -#define FRC FRB + 1 -#define FRC_MASK (0x1f << 6) - { 5, 6, 0, 0, PPC_OPERAND_FPR }, - - /* The FRS field in an X form instruction or the FRT field in a D, X - or A form instruction. */ -#define FRS FRC + 1 -#define FRT FRS - { 5, 21, 0, 0, PPC_OPERAND_FPR }, - - /* The FXM field in an XFX instruction. */ -#define FXM FRS + 1 -#define FXM_MASK (0xff << 12) - { 8, 12, 0, 0, 0 }, - - /* The L field in a D or X form instruction. */ -#define L FXM + 1 - { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, - - /* The LEV field in a POWER SC form instruction. */ -#define LEV L + 1 - { 7, 5, 0, 0, 0 }, - - /* The LI field in an I form instruction. The lower two bits are - forced to zero. */ -#define LI LEV + 1 - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The LI field in an I form instruction when used as an absolute - address. */ -#define LIA LI + 1 - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The MB field in an M form instruction. */ -#define MB LIA + 1 -#define MB_MASK (0x1f << 6) - { 5, 6, 0, 0, 0 }, - - /* The ME field in an M form instruction. */ -#define ME MB + 1 -#define ME_MASK (0x1f << 1) - { 5, 1, 0, 0, 0 }, - - /* The MB and ME fields in an M form instruction expressed a single - operand which is a bitmask indicating which bits to select. This - is a two operand form using PPC_OPERAND_NEXT. See the - description in opcode/ppc.h for what this means. */ -#define MBE ME + 1 - { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, - { 32, 0, insert_mbe, extract_mbe, 0 }, - - /* The MB or ME field in an MD or MDS form instruction. The high - bit is wrapped to the low end. */ -#define MB6 MBE + 2 -#define ME6 MB6 -#define MB6_MASK (0x3f << 5) - { 6, 5, insert_mb6, extract_mb6, 0 }, - - /* The NB field in an X form instruction. The value 32 is stored as - 0. */ -#define NB MB6 + 1 - { 6, 11, insert_nb, extract_nb, 0 }, - - /* The NSI field in a D form instruction. This is the same as the - SI field, only negated. */ -#define NSI NB + 1 - { 16, 0, insert_nsi, extract_nsi, - PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ -#define RA NSI + 1 -#define RA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_GPR }, - - /* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ -#define RAL RA + 1 - { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, - - /* The RA field in an lmw instruction, which has special value - restrictions. */ -#define RAM RAL + 1 - { 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, - - /* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ -#define RAS RAM + 1 - { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, - - /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB RAS + 1 -#define RB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_GPR }, - - /* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. */ -#define RBS RB + 1 - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, - - /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form - instruction or the RT field in a D, DS, X, XFX or XO form - instruction. */ -#define RS RBS + 1 -#define RT RS -#define RT_MASK (0x1f << 21) - { 5, 21, 0, 0, PPC_OPERAND_GPR }, - - /* The SH field in an X or M form instruction. */ -#define SH RS + 1 -#define SH_MASK (0x1f << 11) - { 5, 11, 0, 0, 0 }, - - /* The SH field in an MD form instruction. This is split. */ -#define SH6 SH + 1 -#define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 6, 1, insert_sh6, extract_sh6, 0 }, - - /* The SI field in a D form instruction. */ -#define SI SH6 + 1 - { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, - - /* The SI field in a D form instruction when we accept a wide range - of positive values. */ -#define SISIGNOPT SI + 1 - { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, - - /* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ -#define SPR SISIGNOPT + 1 -#define SPR_MASK (0x3ff << 11) - { 10, 11, insert_spr, extract_spr, 0 }, - - /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ -#define SPRBAT SPR + 1 -#define SPRBAT_MASK (0x3 << 17) - { 2, 17, 0, 0, 0 }, - - /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG SPRBAT + 1 -#define SPRG_MASK (0x3 << 16) - { 2, 16, 0, 0, 0 }, - - /* The SR field in an X form instruction. */ -#define SR SPRG + 1 - { 4, 16, 0, 0, 0 }, - - /* The SV field in a POWER SC form instruction. */ -#define SV SR + 1 - { 14, 2, 0, 0, 0 }, - - /* The TBR field in an XFX form instruction. This is like the SPR - field, but it is optional. */ -#define TBR SV + 1 - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, - - /* The TO field in a D or X form instruction. */ -#define TO TBR + 1 -#define TO_MASK (0x1f << 21) - { 5, 21, 0, 0, 0 }, - - /* The U field in an X form instruction. */ -#define U TO + 1 - { 4, 12, 0, 0, 0 }, - - /* The UI field in a D form instruction. */ -#define UI U + 1 - { 16, 0, 0, 0, 0 }, -}; - -/* The functions used to insert and extract complicated operands. */ - -/* The BA field in an XL form instruction when it must be the same as - the BT field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BT field into the BA field, - and the extraction function just checks that the fields are the - same. */ - -/*ARGSUSED*/ -static unsigned long -insert_bat (insn, value, errmsg) - unsigned long insn; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static long -extract_bat (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BB field in an XL form instruction when it must be the same as - the BA field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BA field into the BB field, - and the extraction function just checks that the fields are the - same. */ - -/*ARGSUSED*/ -static unsigned long -insert_bba (insn, value, errmsg) - unsigned long insn; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (((insn >> 16) & 0x1f) << 11); -} - -static long -extract_bba (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BD field in a B form instruction. The lower two bits are - forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_bd (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (value & 0xfffc); -} - -/*ARGSUSED*/ -static long -extract_bd (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The BD field in a B form instruction when the - modifier is used. - This modifier means that the branch is not expected to be taken. - We must set the y bit of the BO field to 1 if the offset is - negative. When extracting, we require that the y bit be 1 and that - the offset be positive, since if the y bit is 0 we just want to - print the normal form of the instruction. */ - -/*ARGSUSED*/ -static unsigned long -insert_bdm (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - if ((value & 0x8000) != 0) - insn |= 1 << 21; - return insn | (value & 0xfffc); -} - -static long -extract_bdm (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) == 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The BD field in a B form instruction when the + modifier is used. - This is like BDM, above, except that the branch is expected to be - taken. */ - -/*ARGSUSED*/ -static unsigned long -insert_bdp (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - if ((value & 0x8000) == 0) - insn |= 1 << 21; - return insn | (value & 0xfffc); -} - -static long -extract_bdp (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) != 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* Check for legal values of a BO field. */ - -static int -valid_bo (value) - long value; -{ - /* Certain encodings have bits that are required to be zero. These - are (z must be zero, y may be anything): - 001zy - 011zy - 1z00y - 1z01y - 1z1zz - */ - switch (value & 0x14) - { - default: - case 0: - return 1; - case 0x4: - return (value & 0x2) == 0; - case 0x10: - return (value & 0x8) == 0; - case 0x14: - return value == 0x14; - } -} - -/* The BO field in a B form instruction. Warn about attempts to set - the field to an illegal value. */ - -static unsigned long -insert_bo (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (errmsg != (const char **) NULL - && ! valid_bo (value)) - *errmsg = _("invalid conditional option"); - return insn | ((value & 0x1f) << 21); -} - -static long -extract_bo (insn, invalid) - unsigned long insn; - int *invalid; -{ - long value; - - value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value)) - *invalid = 1; - return value; -} - -/* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. When - extracting it, we force it to be even. */ - -static unsigned long -insert_boe (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (errmsg != (const char **) NULL) - { - if (! valid_bo (value)) - *errmsg = _("invalid conditional option"); - else if ((value & 1) != 0) - *errmsg = _("attempt to set y bit when using + or - modifier"); - } - return insn | ((value & 0x1f) << 21); -} - -static long -extract_boe (insn, invalid) - unsigned long insn; - int *invalid; -{ - long value; - - value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value)) - *invalid = 1; - return value & 0x1e; -} - -/* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_ds (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (value & 0xfffc); -} - -/*ARGSUSED*/ -static long -extract_ds (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The LI field in an I form instruction. The lower two bits are - forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_li (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if ((value & 3) != 0 && errmsg != (const char **) NULL) - *errmsg = _("ignoring least significant bits in branch offset"); - return insn | (value & 0x3fffffc); -} - -/*ARGSUSED*/ -static long -extract_li (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - if ((insn & 0x2000000) != 0) - return (insn & 0x3fffffc) - 0x4000000; - else - return insn & 0x3fffffc; -} - -/* The MB and ME fields in an M form instruction expressed as a single - operand which is itself a bitmask. The extraction function always - marks it as invalid, since we never want to recognize an - instruction which uses a field of this type. */ - -static unsigned long -insert_mbe (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - unsigned long uval, mask; - int mb, me, mx, count, last; - - uval = value; - - if (uval == 0) - { - if (errmsg != (const char **) NULL) - *errmsg = _("illegal bitmask"); - return insn; - } - - mb = 0; - me = 32; - if ((uval & 1) != 0) - last = 1; - else - last = 0; - count = 0; - - /* mb: location of last 0->1 transition */ - /* me: location of last 1->0 transition */ - /* count: # transitions */ - - for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1) - { - if ((uval & mask) && !last) - { - ++count; - mb = mx; - last = 1; - } - else if (!(uval & mask) && last) - { - ++count; - me = mx; - last = 0; - } - } - if (me == 0) - me = 32; - - if (count != 2 && (count != 0 || ! last)) - { - if (errmsg != (const char **) NULL) - *errmsg = _("illegal bitmask"); - } - - return insn | (mb << 6) | ((me - 1) << 1); -} - -static long -extract_mbe (insn, invalid) - unsigned long insn; - int *invalid; -{ - long ret; - int mb, me; - int i; - - if (invalid != (int *) NULL) - *invalid = 1; - - mb = (insn >> 6) & 0x1f; - me = (insn >> 1) & 0x1f; - if (mb < me + 1) - { - ret = 0; - for (i = mb; i <= me; i++) - ret |= (long) 1 << (31 - i); - } - else if (mb == me + 1) - ret = ~0; - else /* (mb > me + 1) */ - { - ret = ~ (long) 0; - for (i = me + 1; i < mb; i++) - ret &= ~ ((long) 1 << (31 - i)); - } - return ret; -} - -/* The MB or ME field in an MD or MDS form instruction. The high bit - is wrapped to the low end. */ - -/*ARGSUSED*/ -static unsigned long -insert_mb6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((value & 0x1f) << 6) | (value & 0x20); -} - -/*ARGSUSED*/ -static long -extract_mb6 (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return ((insn >> 6) & 0x1f) | (insn & 0x20); -} - -/* The NB field in an X form instruction. The value 32 is stored as - 0. */ - -static unsigned long -insert_nb (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value < 0 || value > 32) - *errmsg = _("value out of range"); - if (value == 32) - value = 0; - return insn | ((value & 0x1f) << 11); -} - -/*ARGSUSED*/ -static long -extract_nb (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - long ret; - - ret = (insn >> 11) & 0x1f; - if (ret == 0) - ret = 32; - return ret; -} - -/* The NSI field in a D form instruction. This is the same as the SI - field, only negated. The extraction function always marks it as - invalid, since we never want to recognize an instruction which uses - a field of this type. */ - -/*ARGSUSED*/ -static unsigned long -insert_nsi (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((- value) & 0xffff); -} - -static long -extract_nsi (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL) - *invalid = 1; - if ((insn & 0x8000) != 0) - return - ((long)(insn & 0xffff) - 0x10000); - else - return - (long)(insn & 0xffff); -} - -/* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ - -static unsigned long -insert_ral (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value == 0 - || (unsigned long) value == ((insn >> 21) & 0x1f)) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in an lmw instruction, which has special value - restrictions. */ - -static unsigned long -insert_ram (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if ((unsigned long) value >= ((insn >> 21) & 0x1f)) - *errmsg = _("index register in load range"); - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ - -static unsigned long -insert_ras (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value == 0) - *errmsg = _("invalid register operand when updating"); - return insn | ((value & 0x1f) << 16); -} - -/* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. This operand is marked FAKE. The insertion - function just copies the BT field into the BA field, and the - extraction function just checks that the fields are the same. */ - -/*ARGSUSED*/ -static unsigned long -insert_rbs (insn, value, errmsg) - unsigned long insn; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (((insn >> 21) & 0x1f) << 11); -} - -static long -extract_rbs (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The SH field in an MD form instruction. This is split. */ - -/*ARGSUSED*/ -static unsigned long -insert_sh6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); -} - -/*ARGSUSED*/ -static long -extract_sh6 (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); -} - -/* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ - -static unsigned long -insert_spr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_spr (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); -} - -/* The TBR field in an XFX instruction. This is just like SPR, but it - is optional. When TBR is omitted, it must be inserted as 268 (the - magic number of the TB register). These functions treat 0 - (indicating an omitted optional operand) as 268. This means that - ``mftb 4,0'' is not handled correctly. This does not matter very - much, since the architecture manual does not define mftb as - accepting any values other than 268 or 269. */ - -#define TB (268) - -static unsigned long -insert_tbr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - if (value == 0) - value = TB; - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_tbr (insn, invalid) - unsigned long insn; - int *invalid ATTRIBUTE_UNUSED; -{ - long ret; - - ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); - if (ret == TB) - ret = 0; - return ret; -} - -/* Macros used to form opcodes. */ - -/* The main opcode. */ -#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) -#define OP_MASK OP (0x3f) - -/* The main opcode combined with a trap code in the TO field of a D - form instruction. Used for extended mnemonics for the trap - instructions. */ -#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) -#define OPTO_MASK (OP_MASK | TO_MASK) - -/* The main opcode combined with a comparison size bit in the L field - of a D form or X form instruction. Used for extended mnemonics for - the comparison instructions. */ -#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) -#define OPL_MASK OPL (0x3f,1) - -/* An A form instruction. */ -#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) -#define A_MASK A (0x3f, 0x1f, 1) - -/* An A_MASK with the FRB field fixed. */ -#define AFRB_MASK (A_MASK | FRB_MASK) - -/* An A_MASK with the FRC field fixed. */ -#define AFRC_MASK (A_MASK | FRC_MASK) - -/* An A_MASK with the FRA and FRC fields fixed. */ -#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) - -/* A B form instruction. */ -#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) -#define B_MASK B (0x3f, 1, 1) - -/* A B form instruction setting the BO field. */ -#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) -#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) - -/* A BBO_MASK with the y bit of the BO field removed. This permits - matching a conditional branch regardless of the setting of the y - bit. */ -#define Y_MASK (((unsigned long)1) << 21) -#define BBOY_MASK (BBO_MASK &~ Y_MASK) - -/* A B form instruction setting the BO field and the condition bits of - the BI field. */ -#define BBOCB(op, bo, cb, aa, lk) \ - (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) -#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) - -/* A BBOCB_MASK with the y bit of the BO field removed. */ -#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) - -/* A BBOYCB_MASK in which the BI field is fixed. */ -#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) - -/* The main opcode mask with the RA field clear. */ -#define DRA_MASK (OP_MASK | RA_MASK) - -/* A DS form instruction. */ -#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) -#define DS_MASK DSO (0x3f, 3) - -/* An M form instruction. */ -#define M(op, rc) (OP (op) | ((rc) & 1)) -#define M_MASK M (0x3f, 1) - -/* An M form instruction with the ME field specified. */ -#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) - -/* An M_MASK with the MB and ME fields fixed. */ -#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) - -/* An M_MASK with the SH and ME fields fixed. */ -#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) - -/* An MD form instruction. */ -#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) -#define MD_MASK MD (0x3f, 0x7, 1) - -/* An MD_MASK with the MB field fixed. */ -#define MDMB_MASK (MD_MASK | MB6_MASK) - -/* An MD_MASK with the SH field fixed. */ -#define MDSH_MASK (MD_MASK | SH6_MASK) - -/* An MDS form instruction. */ -#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) -#define MDS_MASK MDS (0x3f, 0xf, 1) - -/* An MDS_MASK with the MB field fixed. */ -#define MDSMB_MASK (MDS_MASK | MB6_MASK) - -/* An SC form instruction. */ -#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) -#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) - -/* An X form instruction. */ -#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) - -/* An X form instruction with the RC bit specified. */ -#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) - -/* The mask for an X form instruction. */ -#define X_MASK XRC (0x3f, 0x3ff, 1) - -/* An X_MASK with the RA field fixed. */ -#define XRA_MASK (X_MASK | RA_MASK) - -/* An X_MASK with the RB field fixed. */ -#define XRB_MASK (X_MASK | RB_MASK) - -/* An X_MASK with the RT field fixed. */ -#define XRT_MASK (X_MASK | RT_MASK) - -/* An X_MASK with the RA and RB fields fixed. */ -#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) - -/* An X_MASK with the RT and RA fields fixed. */ -#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) - -/* An X form comparison instruction. */ -#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) - -/* The mask for an X form comparison instruction. */ -#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) - -/* The mask for an X form comparison instruction with the L field - fixed. */ -#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) - -/* An X form trap instruction with the TO field specified. */ -#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) -#define XTO_MASK (X_MASK | TO_MASK) - -/* An XFL form instruction. */ -#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) - -/* An XL form instruction with the LK field set to 0. */ -#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) - -/* An XL form instruction which uses the LK field. */ -#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) - -/* The mask for an XL form instruction. */ -#define XL_MASK XLLK (0x3f, 0x3ff, 1) - -/* An XL form instruction which explicitly sets the BO field. */ -#define XLO(op, bo, xop, lk) \ - (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) -#define XLO_MASK (XL_MASK | BO_MASK) - -/* An XL form instruction which explicitly sets the y bit of the BO - field. */ -#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) -#define XLYLK_MASK (XL_MASK | Y_MASK) - -/* An XL form instruction which sets the BO field and the condition - bits of the BI field. */ -#define XLOCB(op, bo, cb, xop, lk) \ - (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) -#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) - -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ -#define XLBB_MASK (XL_MASK | BB_MASK) -#define XLYBB_MASK (XLYLK_MASK | BB_MASK) -#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) - -/* An XL_MASK with the BO and BB fields fixed. */ -#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) - -/* An XL_MASK with the BO, BI and BB fields fixed. */ -#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) - -/* An XO form instruction. */ -#define XO(op, xop, oe, rc) \ - (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) -#define XO_MASK XO (0x3f, 0x1ff, 1, 1) - -/* An XO_MASK with the RB field fixed. */ -#define XORB_MASK (XO_MASK | RB_MASK) - -/* An XS form instruction. */ -#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) -#define XS_MASK XS (0x3f, 0x1ff, 1) - -/* A mask for the FXM version of an XFX form instruction. */ -#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11)) - -/* An XFX form instruction with the FXM field filled in. */ -#define XFXM(op, xop, fxm) \ - (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) - -/* An XFX form instruction with the SPR field filled in. */ -#define XSPR(op, xop, spr) \ - (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) -#define XSPR_MASK (X_MASK | SPR_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRBAT field. */ -#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRG field. */ -#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) - -/* An X form instruction with everything filled in except the E field. */ -#define XE_MASK (0xffff7fff) - -/* The BO encodings used in extended conditional branch mnemonics. */ -#define BODNZF (0x0) -#define BODNZFP (0x1) -#define BODZF (0x2) -#define BODZFP (0x3) -#define BOF (0x4) -#define BOFP (0x5) -#define BODNZT (0x8) -#define BODNZTP (0x9) -#define BODZT (0xa) -#define BODZTP (0xb) -#define BOT (0xc) -#define BOTP (0xd) -#define BODNZ (0x10) -#define BODNZP (0x11) -#define BODZ (0x12) -#define BODZP (0x13) -#define BOU (0x14) - -/* The BI condition bit encodings used in extended conditional branch - mnemonics. */ -#define CBLT (0) -#define CBGT (1) -#define CBEQ (2) -#define CBSO (3) - -/* The TO encodings used in extended trap mnemonics. */ -#define TOLGT (0x1) -#define TOLLT (0x2) -#define TOEQ (0x4) -#define TOLGE (0x5) -#define TOLNL (0x5) -#define TOLLE (0x6) -#define TOLNG (0x6) -#define TOGT (0x8) -#define TOGE (0xc) -#define TONL (0xc) -#define TOLT (0x10) -#define TOLE (0x14) -#define TONG (0x14) -#define TONE (0x18) -#define TOU (0x1f) - -/* Smaller names for the flags so each entry in the opcodes table will - fit on a single line. */ -#undef PPC -#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY -#define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY -#define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY -#define PPCONLY PPC_OPCODE_PPC -#define PPC403 PPC -#define PPC750 PPC -#define PPC860 PPC -#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY -#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY -#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY -#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32 -#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY -#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 -#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY -#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY -#define MFDEC1 PPC_OPCODE_POWER -#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK FLAGS { OPERANDS } - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - FLAGS are flags indicated what processors support the instruction. - OPERANDS is the list of operands. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ - -const struct powerpc_opcode powerpc_opcodes[] = { -{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, - -{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, -{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, - -{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, - -{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, - -{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, - -{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, -{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, - -{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, -{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, - -{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, -{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, -{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, -{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, -{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } }, -{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } }, -{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, - -{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, -{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, -{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } }, -{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } }, -{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } }, -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } }, -{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } }, -{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, -{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } }, -{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } }, -{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, -{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } }, -{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } }, -{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, -{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } }, -{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } }, -{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, - -{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, -{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, -{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, - -{ "b", B(18,0,0), B_MASK, COM, { LI } }, -{ "bl", B(18,0,1), B_MASK, COM, { LI } }, -{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, -{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, - -{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, - -{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, -{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, -{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, -{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, - -{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, -{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, - -{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } }, - -{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, - -{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, - -{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, -{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, - -{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, -{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, - -{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, - -{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, - -{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, -{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, - -{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, - -{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, -{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, - -{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, -{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, -{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, - -{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, -{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, -{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, -{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, -{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, -{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, -{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, - -{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, -{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, -{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, -{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, -{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, -{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, - -{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, -{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, -{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, -{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, -{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, -{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, -{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, - -{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, -{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, -{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, -{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, - -{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, -{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, - -{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, -{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, - -{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, -{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, -{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, -{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, - -{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, -{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } }, - -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, - -{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, - -{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, -{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, -{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, -{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, -{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, - -{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, -{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, - -{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, -{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, - -{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, -{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, - -{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, - -{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, - -{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, -{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, -{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, - -{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, -{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, - -{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, -{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, -{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, -{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, - -{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, - -{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } }, - -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, - -{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, - -{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, -{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, -{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, -{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, - -{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } }, - -{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, - -{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, -{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, -{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, -{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, - -{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, - -{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }}, -{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, - -{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, - -{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } }, - -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, - -{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, -{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, - -{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, -{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, -{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, - -{ "wrteei", X(31,163), XE_MASK, PPC403, { E } }, - -{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, - -{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, -{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } }, - -{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, -{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, - -{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, - -{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, - -{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, - -{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, -{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, -{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, - -{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, -{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, - -{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, - -{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, - -{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, -{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, - -{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, -{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, - -{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, - -{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, - -{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } }, - -{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, -{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, - -{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, -{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } }, - -{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, - -{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, - -{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, -{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, - -{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, -{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, -{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, -{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, -{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, -{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, -{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, -{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, -{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, -{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, -{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, -{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, -{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, -{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } }, - -{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, -{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, -{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, -{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, -{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, -{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, -{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, -{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, -{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, -{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, -{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, -{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, -{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, -{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, -{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, -{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, -{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, -{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, -{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, -{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, -{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, -{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, -{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, -{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, -{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, -{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, -{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, -{ "mficdbdr",XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, -{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, -{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, -{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, -{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, -{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, -{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, -{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, -{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, -{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, -{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, -{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, -{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, -{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, -{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, -{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, -{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, -{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, -{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, -{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, -{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, -{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, -{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, -{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, -{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, -{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, -{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, -{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, -{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, -{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, -{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, -{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, -{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, - -{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, - -{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, - -{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } }, - -{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, -{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, -{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, -{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, - -{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, - -{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, -{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, - -{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, - -{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, - -{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, - -{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, -{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, - -{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, -{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, - -{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, - -{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, - -{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, - -{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, -{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, -{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, -{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, - -{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } }, -{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } }, -{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } }, -{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } }, -{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } }, -{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } }, -{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } }, -{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } }, -{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } }, -{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } }, -{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } }, -{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } }, -{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } }, -{ "mtummcr0", XSPR(31,451,936), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc1", XSPR(31,451,937), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc2", XSPR(31,451,938), XSPR_MASK, PPC750, { RT } }, -{ "mtusia", XSPR(31,451,939), XSPR_MASK, PPC750, { RT } }, -{ "mtummcr1", XSPR(31,451,940), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc3", XSPR(31,451,941), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc4", XSPR(31,451,942), XSPR_MASK, PPC750, { RT } }, -{ "mtmmcr0", XSPR(31,451,952), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc1", XSPR(31,451,953), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc2", XSPR(31,451,954), XSPR_MASK, PPC750, { RT } }, -{ "mtsia", XSPR(31,451,955), XSPR_MASK, PPC750, { RT } }, -{ "mtmmcr1", XSPR(31,451,956), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc3", XSPR(31,451,957), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc4", XSPR(31,451,958), XSPR_MASK, PPC750, { RT } }, -{ "mtl2cr", XSPR(31,451,1017), XSPR_MASK, PPC750, { RT } }, -{ "mtictc", XSPR(31,451,1019), XSPR_MASK, PPC750, { RT } }, -{ "mtthrm1", XSPR(31,451,1020), XSPR_MASK, PPC750, { RT } }, -{ "mtthrm2", XSPR(31,451,1021), XSPR_MASK, PPC750, { RT } }, -{ "mtthrm3", XSPR(31,451,1022), XSPR_MASK, PPC750, { RT } }, -{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } }, - -{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, -{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, -{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, -{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, -{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, -{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, -{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } }, -{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } }, -{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } }, -{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } }, -{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } }, -{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } }, -{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } }, -{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } }, -{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } }, -{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } }, -{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, -{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, -{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, -{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } }, -{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } }, -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } }, -{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } }, -{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } }, -{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } }, -{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } }, -{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } }, -{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } }, -{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } }, -{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } }, -{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } }, -{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } }, -{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } }, -{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } }, -{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } }, -{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } }, -{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } }, -{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } }, -{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } }, -{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } }, -{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } }, -{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } }, -{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } }, -{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } }, -{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } }, -{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, - -{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, - -{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, -{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, - -{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, - -{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, -{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, -{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, -{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, - -{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, - -{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, - -{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, - -{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, - -{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, -{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } }, -{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, - -{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, -{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, - -{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, -{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, - -{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, - -{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, - -{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, - -{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, -{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, - -{ "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } }, -{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, - -{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, - -{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, - -{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, - -{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, - -{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, -{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } }, - -{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } }, -{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } }, - -{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } }, - -{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, -{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, -{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, - -{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, - -{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, -{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, - -{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, -{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } }, - -{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } }, - -{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, -{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, -{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, - -{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, - -{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, -{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, - -{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, - -{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, -{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, -{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, -{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, - -{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, - -{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, - -{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, - -{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, -{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, - -{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, -{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, - -{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, -{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, -{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, -{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, - -{ "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } }, - -{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, -{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, - -{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, -{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, - -{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } }, - -{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, -{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, - -{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, - -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, - -{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, - -{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } }, - -{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, - -{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, -{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, - -{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } }, -{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } }, - -{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, -{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } }, - -{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } }, - -{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, - -{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } }, -{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } }, - -{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, -{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } }, - -{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } }, - -{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, - -{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } }, - -{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, - -{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } }, - -{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, - -{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } }, - -{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, - -{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, -{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } }, - -{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } }, -{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } }, - -{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, - -{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, - -{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, - -{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, - -{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } }, - -{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, - -{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } }, - -{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, - -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, - -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, - -{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } }, - -{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, - -{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } }, - -{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, - -{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } }, - -{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, - -{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, - -{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, -{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, - -{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, - -{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, - -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, - -{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, -{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, -{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, -{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, - -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, - -{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, -{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, - -{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, - -{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, -{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, - -{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, - -{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, -{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, - -{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, -{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, - -{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, - -{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, - -{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, - -}; - -const int powerpc_num_opcodes = - sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); - -/* The macro table. This is only used by the assembler. */ - -/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 - when x=0; 32-x when x is between 1 and 31; are negative if x is - negative; and are 32 or more otherwise. This is what you want - when, for instance, you are emulating a right shift by a - rotate-left-and-mask, because the underlying instructions support - shifts of size 0 but not shifts of size 32. By comparison, when - extracting x bits from some word you want to use just 32-x, because - the underlying instructions don't support extracting 0 bits but do - support extracting the whole word (32 bits in this case). */ - -const struct powerpc_macro powerpc_macros[] = { -{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, -{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, -{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, -{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, -{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, -{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, -{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, -{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, -{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, -{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, -{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, -{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, -{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, -{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, -{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, -{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, - -{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, -{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, -{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, -{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, -{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, -{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, -{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, -{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, -{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, -{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, -{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, -{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, -{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, -{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, -{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, -{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, -{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, -{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, - -}; - -const int powerpc_num_macros = - sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c deleted file mode 100644 index c4e960c24e8bc..0000000000000 --- a/contrib/binutils/opcodes/sh-dis.c +++ /dev/null @@ -1,734 +0,0 @@ -/* Disassemble SH instructions. - Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#define STATIC_TABLE -#define DEFINE_TABLE - -#include "sh-opc.h" -#include "dis-asm.h" - -#define LITTLE_BIT 2 - -static void -print_movxy (op, rn, rm, fprintf_fn, stream) - sh_opcode_info *op; - int rn, rm; - fprintf_ftype fprintf_fn; - void *stream; -{ - int n; - - fprintf_fn (stream,"%s\t", op->name); - for (n = 0; n < 2; n++) - { - switch (op->arg[n]) - { - case A_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case A_PMOD_N: - fprintf_fn (stream, "@r%d+r8", rn); - break; - case A_PMODY_N: - fprintf_fn (stream, "@r%d+r9", rn); - break; - case DSP_REG_M: - fprintf_fn (stream, "a%c", '0' + rm); - break; - case DSP_REG_X: - fprintf_fn (stream, "x%c", '0' + rm); - break; - case DSP_REG_Y: - fprintf_fn (stream, "y%c", '0' + rm); - break; - default: - abort (); - } - if (n == 0) - fprintf_fn (stream, ","); - } -} - -/* Print a double data transfer insn. INSN is just the lower three - nibbles of the insn, i.e. field a and the bit that indicates if - a parallel processing insn follows. - Return nonzero if a field b of a parallel processing insns follows. */ -static void -print_insn_ddt (insn, info) - int insn; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - - /* If this is just a nop, make sure to emit something. */ - if (insn == 0x000) - fprintf_fn (stream, "nopx\tnopy"); - - /* If a parallel processing insn was printed before, - and we got a non-nop, emit a tab. */ - if ((insn & 0x800) && (insn & 0x3ff)) - fprintf_fn (stream, "\t"); - - /* Check if either the x or y part is invalid. */ - if (((insn & 0xc) == 0 && (insn & 0x2a0)) - || ((insn & 3) == 0 && (insn & 0x150))) - fprintf_fn (stream, ".word 0x%x", insn); - else - { - static sh_opcode_info *first_movx, *first_movy; - sh_opcode_info *opx, *opy; - int insn_x, insn_y; - - if (! first_movx) - { - for (first_movx = sh_table; first_movx->nibbles[1] != MOVX; ) - first_movx++; - for (first_movy = first_movx; first_movy->nibbles[1] != MOVY; ) - first_movy++; - } - insn_x = (insn >> 2) & 0xb; - if (insn_x) - { - for (opx = first_movx; opx->nibbles[2] != insn_x; ) opx++; - print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, - fprintf_fn, stream); - } - insn_y = (insn & 3) | ((insn >> 1) & 8); - if (insn_y) - { - if (insn_x) - fprintf_fn (stream, "\t"); - for (opy = first_movy; opy->nibbles[2] != insn_y; ) opy++; - print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, - fprintf_fn, stream); - } - } -} - -static void -print_dsp_reg (rm, fprintf_fn, stream) - int rm; - fprintf_ftype fprintf_fn; - void *stream; -{ - switch (rm) - { - case A_A1_NUM: - fprintf_fn (stream, "a1"); - break; - case A_A0_NUM: - fprintf_fn (stream, "a0"); - break; - case A_X0_NUM: - fprintf_fn (stream, "x0"); - break; - case A_X1_NUM: - fprintf_fn (stream, "x1"); - break; - case A_Y0_NUM: - fprintf_fn (stream, "y0"); - break; - case A_Y1_NUM: - fprintf_fn (stream, "y1"); - break; - case A_M0_NUM: - fprintf_fn (stream, "m0"); - break; - case A_A1G_NUM: - fprintf_fn (stream, "a1g"); - break; - case A_M1_NUM: - fprintf_fn (stream, "m1"); - break; - case A_A0G_NUM: - fprintf_fn (stream, "a0g"); - break; - default: - fprintf_fn (stream, "0x%x", rm); - break; - } -} - -static void -print_insn_ppi (field_b, info) - int field_b; - struct disassemble_info *info; -{ - static char *sx_tab[] = {"x0","x1","a0","a1"}; - static char *sy_tab[] = {"y0","y1","m0","m1"}; - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - int nib1, nib2, nib3; - char *dc; - sh_opcode_info *op; - - if ((field_b & 0xe800) == 0) - { - fprintf_fn (stream, "psh%c\t#%d,", - field_b & 0x1000 ? 'a' : 'l', - (field_b >> 4) & 127); - print_dsp_reg (field_b & 0xf, fprintf_fn, stream); - return; - } - if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) - { - static char *du_tab[] = {"x0","y0","a0","a1"}; - static char *se_tab[] = {"x0","x1","y0","a1"}; - static char *sf_tab[] = {"y0","y1","x0","a1"}; - static char *sg_tab[] = {"m0","m1","a0","a1"}; - - if (field_b & 0x2000) - { - fprintf_fn (stream, "p%s %s,%s,%s\t", - (field_b & 0x1000) ? "add" : "sub", - sx_tab[(field_b >> 6) & 3], - sy_tab[(field_b >> 4) & 3], - du_tab[(field_b >> 0) & 3]); - } - fprintf_fn (stream, "pmuls%c%s,%s,%s", - field_b & 0x2000 ? ' ' : '\t', - se_tab[(field_b >> 10) & 3], - sf_tab[(field_b >> 8) & 3], - sg_tab[(field_b >> 2) & 3]); - return; - } - - nib1 = PPIC; - nib2 = field_b >> 12 & 0xf; - nib3 = field_b >> 8 & 0xf; - switch (nib3 & 0x3) - { - case 0: - dc = ""; - nib1 = PPI3; - break; - case 1: - dc = ""; - break; - case 2: - dc = "dct "; - nib3 -= 1; - break; - case 3: - dc = "dcf "; - nib3 -= 2; - break; - } - for (op = sh_table; op->name; op++) - { - if (op->nibbles[1] == nib1 - && op->nibbles[2] == nib2 - && op->nibbles[3] == nib3) - { - int n; - - fprintf_fn (stream, "%s%s\t", dc, op->name); - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case DSP_REG_N: - print_dsp_reg (field_b & 0xf, fprintf_fn, stream); - break; - case DSP_REG_X: - fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); - break; - case DSP_REG_Y: - fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream ,"macl"); - break; - default: - abort (); - } - } - return; - } - } - /* Not found. */ - fprintf_fn (stream, ".word 0x%x", field_b); -} - -static int -print_insn_shx (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - unsigned char insn[2]; - unsigned char nibs[4]; - int status; - bfd_vma relmask = ~ (bfd_vma) 0; - sh_opcode_info *op; - int target_arch; - - switch (info->mach) - { - case bfd_mach_sh: - target_arch = arch_sh1; - break; - case bfd_mach_sh2: - target_arch = arch_sh2; - break; - case bfd_mach_sh_dsp: - target_arch = arch_sh_dsp; - break; - case bfd_mach_sh3: - target_arch = arch_sh3; - break; - case bfd_mach_sh3_dsp: - target_arch = arch_sh3_dsp; - break; - case bfd_mach_sh3e: - target_arch = arch_sh3e; - break; - case bfd_mach_sh4: - target_arch = arch_sh4; - break; - default: - abort (); - } - - status = info->read_memory_func (memaddr, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - if (info->flags & LITTLE_BIT) - { - nibs[0] = (insn[1] >> 4) & 0xf; - nibs[1] = insn[1] & 0xf; - - nibs[2] = (insn[0] >> 4) & 0xf; - nibs[3] = insn[0] & 0xf; - } - else - { - nibs[0] = (insn[0] >> 4) & 0xf; - nibs[1] = insn[0] & 0xf; - - nibs[2] = (insn[1] >> 4) & 0xf; - nibs[3] = insn[1] & 0xf; - } - - if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up) - { - if (nibs[1] & 8) - { - int field_b; - - status = info->read_memory_func (memaddr + 2, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr + 2, info); - return -1; - } - - if (info->flags & LITTLE_BIT) - field_b = insn[1] << 8 | insn[0]; - else - field_b = insn[0] << 8 | insn[1]; - - print_insn_ppi (field_b, info); - print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); - return 4; - } - print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); - return 2; - } - for (op = sh_table; op->name; op++) - { - int n; - int imm = 0; - int rn = 0; - int rm = 0; - int rb = 0; - int disp_pc; - bfd_vma disp_pc_addr = 0; - - if ((op->arch & target_arch) == 0) - goto fail; - for (n = 0; n < 4; n++) - { - int i = op->nibbles[n]; - - if (i < 16) - { - if (nibs[n] == i) - continue; - goto fail; - } - switch (i) - { - case BRANCH_8: - imm = (nibs[2] << 4) | (nibs[3]); - if (imm & 0x80) - imm |= ~0xff; - imm = ((char)imm) * 2 + 4 ; - goto ok; - case BRANCH_12: - imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); - if (imm & 0x800) - imm |= ~0xfff; - imm = imm * 2 + 4; - goto ok; - case IMM_4: - imm = nibs[3]; - goto ok; - case IMM_4BY2: - imm = nibs[3] <<1; - goto ok; - case IMM_4BY4: - imm = nibs[3] <<2; - goto ok; - case IMM_8: - imm = (nibs[2] << 4) | nibs[3]; - goto ok; - case PCRELIMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) <<1; - relmask = ~ (bfd_vma) 1; - goto ok; - case PCRELIMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) <<2; - relmask = ~ (bfd_vma) 3; - goto ok; - case IMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) <<1; - goto ok; - case IMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) <<2; - goto ok; - case DISP_8: - imm = (nibs[2] << 4) | (nibs[3]); - goto ok; - case DISP_4: - imm = nibs[3]; - goto ok; - case REG_N: - rn = nibs[n]; - break; - case REG_M: - rm = nibs[n]; - break; - case REG_NM: - rn = (nibs[n] & 0xc) >> 2; - rm = (nibs[n] & 0x3); - break; - case REG_B: - rb = nibs[n] & 0x07; - break; - case SDT_REG_N: - /* sh-dsp: single data transfer. */ - rn = nibs[n]; - if ((rn & 0xc) != 4) - goto fail; - rn = rn & 0x3; - rn |= (rn & 2) << 1; - break; - case PPI: - goto fail; - default: - abort(); - } - } - - ok: - fprintf_fn (stream,"%s\t", op->name); - disp_pc = 0; - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case A_IMM: - fprintf_fn (stream, "#%d", (char)(imm)); - break; - case A_R0: - fprintf_fn (stream, "r0"); - break; - case A_REG_N: - fprintf_fn (stream, "r%d", rn); - break; - case A_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case A_DEC_N: - fprintf_fn (stream, "@-r%d", rn); - break; - case A_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_DISP_REG_N: - fprintf_fn (stream, "@(%d,r%d)", imm, rn); - break; - case A_PMOD_N: - fprintf_fn (stream, "@r%d+r8", rn); - break; - case A_REG_M: - fprintf_fn (stream, "r%d", rm); - break; - case A_INC_M: - fprintf_fn (stream, "@r%d+", rm); - break; - case A_DEC_M: - fprintf_fn (stream, "@-r%d", rm); - break; - case A_IND_M: - fprintf_fn (stream, "@r%d", rm); - break; - case A_DISP_REG_M: - fprintf_fn (stream, "@(%d,r%d)", imm, rm); - break; - case A_REG_B: - fprintf_fn (stream, "r%d_bank", rb); - break; - case A_DISP_PC: - disp_pc = 1; - disp_pc_addr = imm + 4 + (memaddr & relmask); - (*info->print_address_func) (disp_pc_addr, info); - break; - case A_IND_R0_REG_N: - fprintf_fn (stream, "@(r0,r%d)", rn); - break; - case A_IND_R0_REG_M: - fprintf_fn (stream, "@(r0,r%d)", rm); - break; - case A_DISP_GBR: - fprintf_fn (stream, "@(%d,gbr)",imm); - break; - case A_R0_GBR: - fprintf_fn (stream, "@(r0,gbr)"); - break; - case A_BDISP12: - case A_BDISP8: - (*info->print_address_func) (imm + memaddr, info); - break; - case A_SR: - fprintf_fn (stream, "sr"); - break; - case A_GBR: - fprintf_fn (stream, "gbr"); - break; - case A_VBR: - fprintf_fn (stream, "vbr"); - break; - case A_DSR: - fprintf_fn (stream, "dsr"); - break; - case A_MOD: - fprintf_fn (stream, "mod"); - break; - case A_RE: - fprintf_fn (stream, "re"); - break; - case A_RS: - fprintf_fn (stream, "rs"); - break; - case A_A0: - fprintf_fn (stream, "a0"); - break; - case A_X0: - fprintf_fn (stream, "x0"); - break; - case A_X1: - fprintf_fn (stream, "x1"); - break; - case A_Y0: - fprintf_fn (stream, "y0"); - break; - case A_Y1: - fprintf_fn (stream, "y1"); - break; - case DSP_REG_M: - print_dsp_reg (rm, fprintf_fn, stream); - break; - case A_SSR: - fprintf_fn (stream, "ssr"); - break; - case A_SPC: - fprintf_fn (stream, "spc"); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream ,"macl"); - break; - case A_PR: - fprintf_fn (stream, "pr"); - break; - case A_SGR: - fprintf_fn (stream, "sgr"); - break; - case A_DBR: - fprintf_fn (stream, "dbr"); - break; - case F_REG_N: - fprintf_fn (stream, "fr%d", rn); - break; - case F_REG_M: - fprintf_fn (stream, "fr%d", rm); - break; - case DX_REG_N: - if (rn & 1) - { - fprintf_fn (stream, "xd%d", rn & ~1); - break; - } - d_reg_n: - case D_REG_N: - fprintf_fn (stream, "dr%d", rn); - break; - case DX_REG_M: - if (rm & 1) - { - fprintf_fn (stream, "xd%d", rm & ~1); - break; - } - case D_REG_M: - fprintf_fn (stream, "dr%d", rm); - break; - case FPSCR_M: - case FPSCR_N: - fprintf_fn (stream, "fpscr"); - break; - case FPUL_M: - case FPUL_N: - fprintf_fn (stream, "fpul"); - break; - case F_FR0: - fprintf_fn (stream, "fr0"); - break; - case V_REG_N: - fprintf_fn (stream, "fv%d", rn*4); - break; - case V_REG_M: - fprintf_fn (stream, "fv%d", rm*4); - break; - case XMTRX_M4: - fprintf_fn (stream, "xmtrx"); - break; - default: - abort(); - } - } - -#if 0 - /* This code prints instructions in delay slots on the same line - as the instruction which needs the delay slots. This can be - confusing, since other disassembler don't work this way, and - it means that the instructions are not all in a line. So I - disabled it. Ian. */ - if (!(info->flags & 1) - && (op->name[0] == 'j' - || (op->name[0] == 'b' - && (op->name[1] == 'r' - || op->name[1] == 's')) - || (op->name[0] == 'r' && op->name[1] == 't') - || (op->name[0] == 'b' && op->name[2] == '.'))) - { - info->flags |= 1; - fprintf_fn (stream, "\t(slot "); - print_insn_shx (memaddr + 2, info); - info->flags &= ~1; - fprintf_fn (stream, ")"); - return 4; - } -#endif - - if (disp_pc && strcmp (op->name, "mova") != 0) - { - int size; - bfd_byte bytes[4]; - - if (relmask == ~ (bfd_vma) 1) - size = 2; - else - size = 4; - status = info->read_memory_func (disp_pc_addr, bytes, size, info); - if (status == 0) - { - unsigned int val; - - if (size == 2) - { - if ((info->flags & LITTLE_BIT) != 0) - val = bfd_getl16 (bytes); - else - val = bfd_getb16 (bytes); - } - else - { - if ((info->flags & LITTLE_BIT) != 0) - val = bfd_getl32 (bytes); - else - val = bfd_getb32 (bytes); - } - fprintf_fn (stream, "\t! 0x%x", val); - } - } - - return 2; - fail: - ; - - } - fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); - return 2; -} - -int -print_insn_shl (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int r; - - info->flags = LITTLE_BIT; - r = print_insn_shx (memaddr, info); - return r; -} - -int -print_insn_sh (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int r; - - info->flags = 0; - r = print_insn_shx (memaddr, info); - return r; -} diff --git a/contrib/binutils/opcodes/sh-opc.h b/contrib/binutils/opcodes/sh-opc.h deleted file mode 100644 index 38bfbcde4b62e..0000000000000 --- a/contrib/binutils/opcodes/sh-opc.h +++ /dev/null @@ -1,830 +0,0 @@ -/* Definitions for SH opcodes. - Copyright (C) 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -typedef enum { - HEX_0, - HEX_1, - HEX_2, - HEX_3, - HEX_4, - HEX_5, - HEX_6, - HEX_7, - HEX_8, - HEX_9, - HEX_A, - HEX_B, - HEX_C, - HEX_D, - HEX_E, - HEX_F, - REG_N, - REG_M, - SDT_REG_N, - REG_NM, - REG_B, - BRANCH_12, - BRANCH_8, - DISP_8, - DISP_4, - IMM_4, - IMM_4BY2, - IMM_4BY4, - PCRELIMM_8BY2, - PCRELIMM_8BY4, - IMM_8, - IMM_8BY2, - IMM_8BY4, - PPI, - NOPX, - NOPY, - MOVX, - MOVY, - PSH, - PMUL, - PPI3, - PDC, - PPIC -} sh_nibble_type; - -typedef enum { - A_END, - A_BDISP12, - A_BDISP8, - A_DEC_M, - A_DEC_N, - A_DISP_GBR, - A_DISP_PC, - A_DISP_REG_M, - A_DISP_REG_N, - A_GBR, - A_IMM, - A_INC_M, - A_INC_N, - A_IND_M, - A_IND_N, - A_PMOD_N, - A_PMODY_N, - A_IND_R0_REG_M, - A_IND_R0_REG_N, - A_MACH, - A_MACL, - A_PR, - A_R0, - A_R0_GBR, - A_REG_M, - A_REG_N, - A_REG_B, - A_SR, - A_VBR, - A_MOD, - A_RE, - A_RS, - A_DSR, - DSP_REG_M, - DSP_REG_N, - DSP_REG_X, - DSP_REG_Y, - DSP_REG_E, - DSP_REG_F, - DSP_REG_G, - A_A0, - A_X0, - A_X1, - A_Y0, - A_Y1, - A_SSR, - A_SPC, - A_SGR, - A_DBR, - F_REG_N, - F_REG_M, - D_REG_N, - D_REG_M, - X_REG_N, /* Only used for argument parsing */ - X_REG_M, /* Only used for argument parsing */ - DX_REG_N, - DX_REG_M, - V_REG_N, - V_REG_M, - XMTRX_M4, - F_FR0, - FPUL_N, - FPUL_M, - FPSCR_N, - FPSCR_M -} sh_arg_type; - -typedef enum { - A_A1_NUM = 5, - A_A0_NUM = 7, - A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, - A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM -} sh_dsp_reg_nums; - -#define arch_sh1 0x0001 -#define arch_sh2 0x0002 -#define arch_sh3 0x0004 -#define arch_sh3e 0x0008 -#define arch_sh4 0x0010 -#define arch_sh_dsp 0x0100 -#define arch_sh3_dsp 0x0200 - -#define arch_sh1_up (arch_sh1 | arch_sh2_up) -#define arch_sh2_up (arch_sh2 | arch_sh3_up | arch_sh_dsp) -#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp) -#define arch_sh3e_up (arch_sh3e | arch_sh4_up) -#define arch_sh4_up arch_sh4 - -#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) -#define arch_sh3_dsp_up arch_sh3_dsp - -typedef struct { - char *name; - sh_arg_type arg[4]; - sh_nibble_type nibbles[4]; - int arch; -} sh_opcode_info; - -#ifdef DEFINE_TABLE - -sh_opcode_info sh_table[] = { - -/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}, arch_sh1_up}, - -/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up}, - -/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}, arch_sh1_up}, - -/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up}, - -/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up}, - -/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up}, - -/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up}, - -/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, - -/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, - -/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, - -/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, - -/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, - -/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, - -/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up}, - -/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}, arch_sh1_up}, - -/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up}, - -/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up}, - -/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up}, - -/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up}, - -/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, - -/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, - -/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up}, - -/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, - -/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, - -/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_up}, - -/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, - -/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_up}, - -/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, - -/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, - -/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_up}, - -/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, - -/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_up}, - -/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, - -/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_BDISP8},{HEX_8,HEX_E,BRANCH_8}, arch_sh_dsp_up}, - -/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_BDISP8},{HEX_8,HEX_C,BRANCH_8}, arch_sh_dsp_up}, - -/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up}, - -/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up}, - -/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up}, - -/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, - -/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up}, - -/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up}, - -/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh3e_up}, - -/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh3e_up}, - -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, - -/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}, arch_sh1_up}, - -/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up}, - -/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}, arch_sh1_up}, - -/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}, arch_sh1_up}, - -/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}, arch_sh1_up}, - -/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}, arch_sh1_up}, - -/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}, arch_sh1_up}, - -/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}, arch_sh1_up}, - -/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up}, - -/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}, arch_sh1_up}, - -/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}, arch_sh1_up}, - -/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up}, - -/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up}, - -/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}, arch_sh1_up}, - -/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}, arch_sh1_up}, - -/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, -/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up}, - - -/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, - -/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, -/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, - -/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, -/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, - -/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, -/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_up}, - -/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_up}, - -/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up}, - - -/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}, arch_sh1_up}, - -/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up}, - -/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, - -/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up}, - -/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up}, - -/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up}, - -/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up}, - -/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, - -/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, -/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, - -/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM_8}, arch_sh_dsp_up}, - -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_up}, - -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_up}, - -/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, - -/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up}, - -/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up}, - -/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up}, - -/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up}, - -/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up}, - -/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up}, - -/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up}, - -/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up}, - -/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_up}, - -/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, - -/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_up}, - -/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_up}, - -/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, - -/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up}, - -/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up}, - -/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_up}, - -/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_up}, - -/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh4_up}, - -/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up}, - -/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_up}, - -/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, - -/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up}, - -/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up}, - -/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up}, - -/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh3e_up}, - -/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up}, - -/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh3e_up}, - -/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh3e_up}, - -/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, - -/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}, arch_sh1_up}, - -/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}, arch_sh1_up}, - -/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, - -/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, - -/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, - -/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, - -/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, - -/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, - -/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, - -/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, - -/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, - -/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, - -/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, - -/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, - -/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, - -/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, - -/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, - -/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, - -/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, - -/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, - -/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, - -/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, - -/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, - -/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, - -/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, -/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, -/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{A_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, -/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{A_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, -/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{A_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, -/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_M,A_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, -/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_M,A_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, -/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_M,A_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, -/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{A_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, -/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{A_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, -/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{A_PMODY_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, -/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_M,A_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, -/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_M,A_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, -/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_M,A_PMODY_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, - -/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, -/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}, -/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}, -/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ -{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}, -/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}, -/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, -/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ -{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up}, -/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ -{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up}, -/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ -{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up}, -/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ -{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up}, - -{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, -{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, - -/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, -/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}, -/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, -/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}, -/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, -/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, -/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}, -/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}, -/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}, -/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ -{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, -/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */ -{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up}, -/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ -{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, -/* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ -{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up}, -/* 10001101xxyynnnn pclr <DSP_REG_N> */ -{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, -/* 10011101xxyynnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D}, arch_sh_dsp_up}, -/* 10111101xxyynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up}, -/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ -{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, -/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ -{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}, -/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ -{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}, -/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ -{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}, -/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ -{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}, -/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ -{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}, -/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ -{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, -/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ -{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, - -/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh3e_up}, -/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up}, - -/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh3e_up}, -/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up}, - -/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh3e_up}, -/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up}, - -/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up}, - -/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh3e_up}, -/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up}, - -/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, - -/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh3e_up}, - -/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh3e_up}, - -/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh3e_up}, - -/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh3e_up}, -/* 1111nnnn00101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh3e_up}, - -/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh3e_up}, -/* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, -/* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, - -/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, -/* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, - -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, - -/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, -/* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, - -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, - -/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, -/* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, - -/* 1111nnnnmmmm1010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, - -/* 1111nnnnmmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, - -/* 1111nnnnmmmm1011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, - -/* 1111nnnnmmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, - -/* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, - -/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, - -/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, - -/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, - -/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, - -/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, - -/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh3e_up}, -/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up}, - -/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up}, - -/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up}, - -/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh3e_up}, - -/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh3e_up}, -/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up}, - -/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh3e_up}, -/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up}, - -/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up}, - -{ 0 } -}; - -#endif diff --git a/contrib/binutils/opcodes/sparc-dis.c b/contrib/binutils/opcodes/sparc-dis.c deleted file mode 100644 index a595d0f3835ee..0000000000000 --- a/contrib/binutils/opcodes/sparc-dis.c +++ /dev/null @@ -1,973 +0,0 @@ -/* Print SPARC instructions. - Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> - -#include "sysdep.h" -#include "opcode/sparc.h" -#include "dis-asm.h" -#include "libiberty.h" -#include "opintl.h" - -/* Bitmask of v9 architectures. */ -#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ - | (1 << SPARC_OPCODE_ARCH_V9A)) -/* 1 if INSN is for v9 only. */ -#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) -/* 1 if INSN is for v9. */ -#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) - -/* The sorted opcode table. */ -static const struct sparc_opcode **sorted_opcodes; - -/* For faster lookup, after insns are sorted they are hashed. */ -/* ??? I think there is room for even more improvement. */ - -#define HASH_SIZE 256 -/* It is important that we only look at insn code bits as that is how the - opcode table is hashed. OPCODE_BITS is a table of valid bits for each - of the main types (0,1,2,3). */ -static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; -#define HASH_INSN(INSN) \ - ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) -struct opcode_hash { - struct opcode_hash *next; - const struct sparc_opcode *opcode; -}; -static struct opcode_hash *opcode_hash_table[HASH_SIZE]; - -static void build_hash_table - PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int)); -static int is_delayed_branch PARAMS ((unsigned long)); -static int compare_opcodes PARAMS ((const PTR, const PTR)); -static int compute_arch_mask PARAMS ((unsigned long)); - -/* Sign-extend a value which is N bits long. */ -#define SEX(value, bits) \ - ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ - >> ((8 * sizeof (int)) - bits) ) - -static char *reg_names[] = -{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", - "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", - "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", -/* psr, wim, tbr, fpsr, cpsr are v8 only. */ - "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" -}; - -#define freg_names (®_names[4 * 8]) - -/* These are ordered according to there register number in - rdpr and wrpr insns. */ -static char *v9_priv_reg_names[] = -{ - "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", - "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", - "wstate", "fq" - /* "ver" - special cased */ -}; - -/* These are ordered according to there register number in - rd and wr insns (-16). */ -static char *v9a_asr_reg_names[] = -{ - "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", - "softint", "tick_cmpr" -}; - -/* Macros used to extract instruction fields. Not all fields have - macros defined here, only those which are actually used. */ - -#define X_RD(i) (((i) >> 25) & 0x1f) -#define X_RS1(i) (((i) >> 14) & 0x1f) -#define X_LDST_I(i) (((i) >> 13) & 1) -#define X_ASI(i) (((i) >> 5) & 0xff) -#define X_RS2(i) (((i) >> 0) & 0x1f) -#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) -#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) -#define X_DISP22(i) (((i) >> 0) & 0x3fffff) -#define X_IMM22(i) X_DISP22 (i) -#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) - -/* These are for v9. */ -#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) -#define X_DISP19(i) (((i) >> 0) & 0x7ffff) -#define X_MEMBAR(i) ((i) & 0x7f) - -/* Here is the union which was used to extract instruction fields - before the shift and mask macros were written. - - union sparc_insn - { - unsigned long int code; - struct - { - unsigned int anop:2; - #define op ldst.anop - unsigned int anrd:5; - #define rd ldst.anrd - unsigned int op3:6; - unsigned int anrs1:5; - #define rs1 ldst.anrs1 - unsigned int i:1; - unsigned int anasi:8; - #define asi ldst.anasi - unsigned int anrs2:5; - #define rs2 ldst.anrs2 - #define shcnt rs2 - } ldst; - struct - { - unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; - unsigned int IMM13:13; - #define imm13 IMM13.IMM13 - } IMM13; - struct - { - unsigned int anop:2; - unsigned int a:1; - unsigned int cond:4; - unsigned int op2:3; - unsigned int DISP22:22; - #define disp22 branch.DISP22 - #define imm22 disp22 - } branch; - struct - { - unsigned int anop:2; - unsigned int a:1; - unsigned int z:1; - unsigned int rcond:3; - unsigned int op2:3; - unsigned int DISP16HI:2; - unsigned int p:1; - unsigned int _rs1:5; - unsigned int DISP16LO:14; - } branch16; - struct - { - unsigned int anop:2; - unsigned int adisp30:30; - #define disp30 call.adisp30 - } call; - }; - - */ - -/* Nonzero if INSN is the opcode for a delayed branch. */ -static int -is_delayed_branch (insn) - unsigned long insn; -{ - struct opcode_hash *op; - - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) - { - CONST struct sparc_opcode *opcode = op->opcode; - if ((opcode->match & insn) == opcode->match - && (opcode->lose & insn) == 0) - return (opcode->flags & F_DELAYED); - } - return 0; -} - -/* extern void qsort (); */ - -/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value - to compare_opcodes. */ -static unsigned int current_arch_mask; - -/* Print one instruction from MEMADDR on INFO->STREAM. - - We suffix the instruction with a comment that gives the absolute - address involved, as well as its symbolic form, if the instruction - is preceded by a findable `sethi' and it either adds an immediate - displacement to that register, or it is an `add' or `or' instruction - on that register. */ - -int -print_insn_sparc (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - FILE *stream = info->stream; - bfd_byte buffer[4]; - unsigned long insn; - register struct opcode_hash *op; - /* Nonzero of opcode table has been initialized. */ - static int opcodes_initialized = 0; - /* bfd mach number of last call. */ - static unsigned long current_mach = 0; - bfd_vma (*getword) PARAMS ((const unsigned char *)); - - if (!opcodes_initialized - || info->mach != current_mach) - { - int i; - - current_arch_mask = compute_arch_mask (info->mach); - - if (!opcodes_initialized) - sorted_opcodes = (const struct sparc_opcode **) - xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); - /* Reset the sorted table so we can resort it. */ - for (i = 0; i < sparc_num_opcodes; ++i) - sorted_opcodes[i] = &sparc_opcodes[i]; - qsort ((char *) sorted_opcodes, sparc_num_opcodes, - sizeof (sorted_opcodes[0]), compare_opcodes); - - build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); - current_mach = info->mach; - opcodes_initialized = 1; - } - - { - int status = - (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - } - - /* On SPARClite variants such as DANlite (sparc86x), instructions - are always big-endian even when the machine is in little-endian mode. */ - if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) - getword = bfd_getb32; - else - getword = bfd_getl32; - - insn = getword (buffer); - - info->insn_info_valid = 1; /* We do return this info */ - info->insn_type = dis_nonbranch; /* Assume non branch insn */ - info->branch_delay_insns = 0; /* Assume no delay */ - info->target = 0; /* Assume no target known */ - - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) - { - CONST struct sparc_opcode *opcode = op->opcode; - - /* If the insn isn't supported by the current architecture, skip it. */ - if (! (opcode->architecture & current_arch_mask)) - continue; - - if ((opcode->match & insn) == opcode->match - && (opcode->lose & insn) == 0) - { - /* Nonzero means that we have found an instruction which has - the effect of adding or or'ing the imm13 field to rs1. */ - int imm_added_to_rs1 = 0; - int imm_ored_to_rs1 = 0; - - /* Nonzero means that we have found a plus sign in the args - field of the opcode table. */ - int found_plus = 0; - - /* Nonzero means we have an annulled branch. */ - int is_annulled = 0; - - /* Do we have an `add' or `or' instruction combining an - immediate with rs1? */ - if (opcode->match == 0x80102000) /* or */ - imm_ored_to_rs1 = 1; - if (opcode->match == 0x80002000) /* add */ - imm_added_to_rs1 = 1; - - if (X_RS1 (insn) != X_RD (insn) - && strchr (opcode->args, 'r') != 0) - /* Can't do simple format if source and dest are different. */ - continue; - if (X_RS2 (insn) != X_RD (insn) - && strchr (opcode->args, 'O') != 0) - /* Can't do simple format if source and dest are different. */ - continue; - - (*info->fprintf_func) (stream, opcode->name); - - { - register CONST char *s; - - if (opcode->args[0] != ',') - (*info->fprintf_func) (stream, " "); - for (s = opcode->args; *s != '\0'; ++s) - { - while (*s == ',') - { - (*info->fprintf_func) (stream, ","); - ++s; - switch (*s) { - case 'a': - (*info->fprintf_func) (stream, "a"); - is_annulled = 1; - ++s; - continue; - case 'N': - (*info->fprintf_func) (stream, "pn"); - ++s; - continue; - - case 'T': - (*info->fprintf_func) (stream, "pt"); - ++s; - continue; - - default: - break; - } /* switch on arg */ - } /* while there are comma started args */ - - (*info->fprintf_func) (stream, " "); - - switch (*s) - { - case '+': - found_plus = 1; - - /* note fall-through */ - default: - (*info->fprintf_func) (stream, "%c", *s); - break; - - case '#': - (*info->fprintf_func) (stream, "0"); - break; - -#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) - case '1': - case 'r': - reg (X_RS1 (insn)); - break; - - case '2': - case 'O': - reg (X_RS2 (insn)); - break; - - case 'd': - reg (X_RD (insn)); - break; -#undef reg - -#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) -#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) - case 'e': - freg (X_RS1 (insn)); - break; - case 'v': /* double/even */ - case 'V': /* quad/multiple of 4 */ - fregx (X_RS1 (insn)); - break; - - case 'f': - freg (X_RS2 (insn)); - break; - case 'B': /* double/even */ - case 'R': /* quad/multiple of 4 */ - fregx (X_RS2 (insn)); - break; - - case 'g': - freg (X_RD (insn)); - break; - case 'H': /* double/even */ - case 'J': /* quad/multiple of 4 */ - fregx (X_RD (insn)); - break; -#undef freg -#undef fregx - -#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) - case 'b': - creg (X_RS1 (insn)); - break; - - case 'c': - creg (X_RS2 (insn)); - break; - - case 'D': - creg (X_RD (insn)); - break; -#undef creg - - case 'h': - (*info->fprintf_func) (stream, "%%hi(%#x)", - (0xFFFFFFFF - & ((int) X_IMM22 (insn) << 10))); - break; - - case 'i': /* 13 bit immediate */ - case 'I': /* 11 bit immediate */ - case 'j': /* 10 bit immediate */ - { - int imm; - - if (*s == 'i') - imm = X_SIMM (insn, 13); - else if (*s == 'I') - imm = X_SIMM (insn, 11); - else - imm = X_SIMM (insn, 10); - - /* Check to see whether we have a 1+i, and take - note of that fact. - - Note: because of the way we sort the table, - we will be matching 1+i rather than i+1, - so it is OK to assume that i is after +, - not before it. */ - if (found_plus) - imm_added_to_rs1 = 1; - - if (imm <= 9) - (*info->fprintf_func) (stream, "%d", imm); - else - (*info->fprintf_func) (stream, "%#x", imm); - } - break; - - case 'X': /* 5 bit unsigned immediate */ - case 'Y': /* 6 bit unsigned immediate */ - { - int imm = X_IMM (insn, *s == 'X' ? 5 : 6); - - if (imm <= 9) - (info->fprintf_func) (stream, "%d", imm); - else - (info->fprintf_func) (stream, "%#x", (unsigned) imm); - } - break; - - case 'K': - { - int mask = X_MEMBAR (insn); - int bit = 0x40, printed_one = 0; - const char *name; - - if (mask == 0) - (info->fprintf_func) (stream, "0"); - else - while (bit) - { - if (mask & bit) - { - if (printed_one) - (info->fprintf_func) (stream, "|"); - name = sparc_decode_membar (bit); - (info->fprintf_func) (stream, "%s", name); - printed_one = 1; - } - bit >>= 1; - } - break; - } - - case 'k': - info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'G': - info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; - (*info->print_address_func) (info->target, info); - break; - - case '6': - case '7': - case '8': - case '9': - (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); - break; - - case 'z': - (*info->fprintf_func) (stream, "%%icc"); - break; - - case 'Z': - (*info->fprintf_func) (stream, "%%xcc"); - break; - - case 'E': - (*info->fprintf_func) (stream, "%%ccr"); - break; - - case 's': - (*info->fprintf_func) (stream, "%%fprs"); - break; - - case 'o': - (*info->fprintf_func) (stream, "%%asi"); - break; - - case 'W': - (*info->fprintf_func) (stream, "%%tick"); - break; - - case 'P': - (*info->fprintf_func) (stream, "%%pc"); - break; - - case '?': - if (X_RS1 (insn) == 31) - (*info->fprintf_func) (stream, "%%ver"); - else if ((unsigned) X_RS1 (insn) < 16) - (*info->fprintf_func) (stream, "%%%s", - v9_priv_reg_names[X_RS1 (insn)]); - else - (*info->fprintf_func) (stream, "%%reserved"); - break; - - case '!': - if ((unsigned) X_RD (insn) < 15) - (*info->fprintf_func) (stream, "%%%s", - v9_priv_reg_names[X_RD (insn)]); - else - (*info->fprintf_func) (stream, "%%reserved"); - break; - - case '/': - if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23) - (*info->fprintf_func) (stream, "%%reserved"); - else - (*info->fprintf_func) (stream, "%%%s", - v9a_asr_reg_names[X_RS1 (insn)-16]); - break; - - case '_': - if (X_RD (insn) < 16 || X_RD (insn) > 23) - (*info->fprintf_func) (stream, "%%reserved"); - else - (*info->fprintf_func) (stream, "%%%s", - v9a_asr_reg_names[X_RD (insn)-16]); - break; - - case '*': - { - const char *name = sparc_decode_prefetch (X_RD (insn)); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "%d", X_RD (insn)); - break; - } - - case 'M': - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); - break; - - case 'm': - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); - break; - - case 'L': - info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'n': - (*info->fprintf_func) - (stream, "%#x", SEX (X_DISP22 (insn), 22)); - break; - - case 'l': - info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'A': - { - const char *name = sparc_decode_asi (X_ASI (insn)); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); - break; - } - - case 'C': - (*info->fprintf_func) (stream, "%%csr"); - break; - - case 'F': - (*info->fprintf_func) (stream, "%%fsr"); - break; - - case 'p': - (*info->fprintf_func) (stream, "%%psr"); - break; - - case 'q': - (*info->fprintf_func) (stream, "%%fq"); - break; - - case 'Q': - (*info->fprintf_func) (stream, "%%cq"); - break; - - case 't': - (*info->fprintf_func) (stream, "%%tbr"); - break; - - case 'w': - (*info->fprintf_func) (stream, "%%wim"); - break; - - case 'x': - (*info->fprintf_func) (stream, "%d", - ((X_LDST_I (insn) << 8) - + X_ASI (insn))); - break; - - case 'y': - (*info->fprintf_func) (stream, "%%y"); - break; - - case 'u': - case 'U': - { - int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); - const char *name = sparc_decode_sparclet_cpreg (val); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "%%cpreg(%d)", val); - break; - } - } - } - } - - /* If we are adding or or'ing something to rs1, then - check to see whether the previous instruction was - a sethi to the same register as in the sethi. - If so, attempt to print the result of the add or - or (in this context add and or do the same thing) - and its symbolic value. */ - if (imm_ored_to_rs1 || imm_added_to_rs1) - { - unsigned long prev_insn; - int errcode; - - errcode = - (*info->read_memory_func) - (memaddr - 4, buffer, sizeof (buffer), info); - prev_insn = getword (buffer); - - if (errcode == 0) - { - /* If it is a delayed branch, we need to look at the - instruction before the delayed branch. This handles - sequences such as - - sethi %o1, %hi(_foo), %o1 - call _printf - or %o1, %lo(_foo), %o1 - */ - - if (is_delayed_branch (prev_insn)) - { - errcode = (*info->read_memory_func) - (memaddr - 8, buffer, sizeof (buffer), info); - prev_insn = getword (buffer); - } - } - - /* If there was a problem reading memory, then assume - the previous instruction was not sethi. */ - if (errcode == 0) - { - /* Is it sethi to the same register? */ - if ((prev_insn & 0xc1c00000) == 0x01000000 - && X_RD (prev_insn) == X_RS1 (insn)) - { - (*info->fprintf_func) (stream, "\t! "); - info->target = - (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10); - if (imm_added_to_rs1) - info->target += X_SIMM (insn, 13); - else - info->target |= X_SIMM (insn, 13); - (*info->print_address_func) (info->target, info); - info->insn_type = dis_dref; - info->data_size = 4; /* FIXME!!! */ - } - } - } - - if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) - { - /* FIXME -- check is_annulled flag */ - if (opcode->flags & F_UNBR) - info->insn_type = dis_branch; - if (opcode->flags & F_CONDBR) - info->insn_type = dis_condbranch; - if (opcode->flags & F_JSR) - info->insn_type = dis_jsr; - if (opcode->flags & F_DELAYED) - info->branch_delay_insns = 1; - } - - return sizeof (buffer); - } - } - - info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ - (*info->fprintf_func) (stream, _("unknown")); - return sizeof (buffer); -} - -/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ - -static int -compute_arch_mask (mach) - unsigned long mach; -{ - switch (mach) - { - case 0 : - case bfd_mach_sparc : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); - case bfd_mach_sparc_sparclet : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); - case bfd_mach_sparc_sparclite : - case bfd_mach_sparc_sparclite_le : - /* sparclites insns are recognized by default (because that's how - they've always been treated, for better or worse). Kludge this by - indicating generic v8 is also selected. */ - return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) - | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); - case bfd_mach_sparc_v8plus : - case bfd_mach_sparc_v9 : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); - case bfd_mach_sparc_v8plusa : - case bfd_mach_sparc_v9a : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); - } - abort (); -} - -/* Compare opcodes A and B. */ - -static int -compare_opcodes (a, b) - const PTR a; - const PTR b; -{ - struct sparc_opcode *op0 = * (struct sparc_opcode **) a; - struct sparc_opcode *op1 = * (struct sparc_opcode **) b; - unsigned long int match0 = op0->match, match1 = op1->match; - unsigned long int lose0 = op0->lose, lose1 = op1->lose; - register unsigned int i; - - /* If one (and only one) insn isn't supported by the current architecture, - prefer the one that is. If neither are supported, but they're both for - the same architecture, continue processing. Otherwise (both unsupported - and for different architectures), prefer lower numbered arch's (fudged - by comparing the bitmasks). */ - if (op0->architecture & current_arch_mask) - { - if (! (op1->architecture & current_arch_mask)) - return -1; - } - else - { - if (op1->architecture & current_arch_mask) - return 1; - else if (op0->architecture != op1->architecture) - return op0->architecture - op1->architecture; - } - - /* If a bit is set in both match and lose, there is something - wrong with the opcode table. */ - if (match0 & lose0) - { - fprintf - (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), - op0->name, match0, lose0); - op0->lose &= ~op0->match; - lose0 = op0->lose; - } - - if (match1 & lose1) - { - fprintf - (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), - op1->name, match1, lose1); - op1->lose &= ~op1->match; - lose1 = op1->lose; - } - - /* Because the bits that are variable in one opcode are constant in - another, it is important to order the opcodes in the right order. */ - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (match0 & x) != 0; - int x1 = (match1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (lose0 & x) != 0; - int x1 = (lose1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - /* They are functionally equal. So as long as the opcode table is - valid, we can put whichever one first we want, on aesthetic grounds. */ - - /* Our first aesthetic ground is that aliases defer to real insns. */ - { - int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); - if (alias_diff != 0) - /* Put the one that isn't an alias first. */ - return alias_diff; - } - - /* Except for aliases, two "identical" instructions had - better have the same opcode. This is a sanity check on the table. */ - i = strcmp (op0->name, op1->name); - if (i) - { - if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ - return i; - else - fprintf (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), - op0->name, op1->name); - } - - /* Fewer arguments are preferred. */ - { - int length_diff = strlen (op0->args) - strlen (op1->args); - if (length_diff != 0) - /* Put the one with fewer arguments first. */ - return length_diff; - } - - /* Put 1+i before i+1. */ - { - char *p0 = (char *) strchr (op0->args, '+'); - char *p1 = (char *) strchr (op1->args, '+'); - - if (p0 && p1) - { - /* There is a plus in both operands. Note that a plus - sign cannot be the first character in args, - so the following [-1]'s are valid. */ - if (p0[-1] == 'i' && p1[1] == 'i') - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ - return 1; - if (p0[1] == 'i' && p1[-1] == 'i') - /* op0 is 1+i and op1 is i+1, so op0 goes first. */ - return -1; - } - } - - /* Put 1,i before i,1. */ - { - int i0 = strncmp (op0->args, "i,1", 3) == 0; - int i1 = strncmp (op1->args, "i,1", 3) == 0; - - if (i0 ^ i1) - return i0 - i1; - } - - /* They are, as far as we can tell, identical. - Since qsort may have rearranged the table partially, there is - no way to tell which one was first in the opcode table as - written, so just say there are equal. */ - /* ??? This is no longer true now that we sort a vector of pointers, - not the table itself. */ - return 0; -} - -/* Build a hash table from the opcode table. - OPCODE_TABLE is a sorted list of pointers into the opcode table. */ - -static void -build_hash_table (opcode_table, hash_table, num_opcodes) - const struct sparc_opcode **opcode_table; - struct opcode_hash **hash_table; - int num_opcodes; -{ - register int i; - int hash_count[HASH_SIZE]; - static struct opcode_hash *hash_buf = NULL; - - /* Start at the end of the table and work backwards so that each - chain is sorted. */ - - memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); - memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); - if (hash_buf != NULL) - free (hash_buf); - hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes); - for (i = num_opcodes - 1; i >= 0; --i) - { - register int hash = HASH_INSN (opcode_table[i]->match); - register struct opcode_hash *h = &hash_buf[i]; - h->next = hash_table[hash]; - h->opcode = opcode_table[i]; - hash_table[hash] = h; - ++hash_count[hash]; - } - -#if 0 /* for debugging */ - { - int min_count = num_opcodes, max_count = 0; - int total; - - for (i = 0; i < HASH_SIZE; ++i) - { - if (hash_count[i] < min_count) - min_count = hash_count[i]; - if (hash_count[i] > max_count) - max_count = hash_count[i]; - total += hash_count[i]; - } - - printf ("Opcode hash table stats: min %d, max %d, ave %f\n", - min_count, max_count, (double) total / HASH_SIZE); - } -#endif -} diff --git a/contrib/binutils/opcodes/sparc-opc.c b/contrib/binutils/opcodes/sparc-opc.c deleted file mode 100644 index a7132bb61f733..0000000000000 --- a/contrib/binutils/opcodes/sparc-opc.c +++ /dev/null @@ -1,2030 +0,0 @@ -/* Table of opcodes for the sparc. - Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 - Free Software Foundation, Inc. - -This file is part of the BFD library. - -BFD is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2, or (at your option) any later -version. - -BFD is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with this software; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* FIXME-someday: perhaps the ,a's and such should be embedded in the - instruction's name rather than the args. This would make gas faster, pinsn - slower, but would mess up some macros a bit. xoxorich. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/sparc.h" - -/* Some defines to make life easy. */ -#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) -#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) -#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) -#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) -#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) -#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) -#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) - -/* Bit masks of architectures supporting the insn. */ - -#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -/* v6 insns not supported on the sparclet */ -#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -/* Although not all insns are implemented in hardware, sparclite is defined - to be a superset of v8. Unimplemented insns trap and are then theoretically - implemented in software. - It's not clear that the same is true for sparclet, although the docs - suggest it is. Rather than complicating things, the sparclet assembler - recognizes all v8 insns. */ -#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -#define sparclet (MASK_SPARCLET) -#define sparclite (MASK_SPARCLITE) -#define v9 (MASK_V9 | MASK_V9A) -#define v9a (MASK_V9A) -/* v6 insns not supported by v9 */ -#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ - | MASK_SPARCLET | MASK_SPARCLITE) -/* v9a instructions which would appear to be aliases to v9's impdep's - otherwise */ -#define v9notv9a (MASK_V9) - -/* Table of opcode architectures. - The order is defined in opcode/sparc.h. */ - -const struct sparc_opcode_arch sparc_opcode_archs[] = { - { "v6", MASK_V6 }, - { "v7", MASK_V6 | MASK_V7 }, - { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, - { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, - { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, - /* ??? Don't some v8 priviledged insns conflict with v9? */ - { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, - /* v9 with ultrasparc additions */ - { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, - { NULL, 0 } -}; - -/* Given NAME, return it's architecture entry. */ - -enum sparc_opcode_arch_val -sparc_opcode_lookup_arch (name) - const char *name; -{ - const struct sparc_opcode_arch *p; - - for (p = &sparc_opcode_archs[0]; p->name; ++p) - { - if (strcmp (name, p->name) == 0) - return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); - } - - return SPARC_OPCODE_ARCH_BAD; -} - -/* Branch condition field. */ -#define COND(x) (((x)&0xf)<<25) - -/* v9: Move (MOVcc and FMOVcc) condition field. */ -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ - -/* v9: Move register (MOVRcc and FMOVRcc) condition field. */ -#define RCOND(x) (((x)&0x7)<<10) /* v9 */ - -#define CONDA (COND(0x8)) -#define CONDCC (COND(0xd)) -#define CONDCS (COND(0x5)) -#define CONDE (COND(0x1)) -#define CONDG (COND(0xa)) -#define CONDGE (COND(0xb)) -#define CONDGU (COND(0xc)) -#define CONDL (COND(0x3)) -#define CONDLE (COND(0x2)) -#define CONDLEU (COND(0x4)) -#define CONDN (COND(0x0)) -#define CONDNE (COND(0x9)) -#define CONDNEG (COND(0x6)) -#define CONDPOS (COND(0xe)) -#define CONDVC (COND(0xf)) -#define CONDVS (COND(0x7)) - -#define CONDNZ CONDNE -#define CONDZ CONDE -#define CONDGEU CONDCC -#define CONDLU CONDCS - -#define FCONDA (COND(0x8)) -#define FCONDE (COND(0x9)) -#define FCONDG (COND(0x6)) -#define FCONDGE (COND(0xb)) -#define FCONDL (COND(0x4)) -#define FCONDLE (COND(0xd)) -#define FCONDLG (COND(0x2)) -#define FCONDN (COND(0x0)) -#define FCONDNE (COND(0x1)) -#define FCONDO (COND(0xf)) -#define FCONDU (COND(0x7)) -#define FCONDUE (COND(0xa)) -#define FCONDUG (COND(0x5)) -#define FCONDUGE (COND(0xc)) -#define FCONDUL (COND(0x3)) -#define FCONDULE (COND(0xe)) - -#define FCONDNZ FCONDNE -#define FCONDZ FCONDE - -#define ICC (0) /* v9 */ -#define XCC (1<<12) /* v9 */ -#define FCC(x) (((x)&0x3)<<11) /* v9 */ -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ - -/* The order of the opcodes in the table is significant: - - * The assembler requires that all instances of the same mnemonic must - be consecutive. If they aren't, the assembler will bomb at runtime. - - * The disassembler should not care about the order of the opcodes. - -*/ - -/* Entries for commutative arithmetic operations. */ -/* ??? More entries can make use of this. */ -#define COMMUTEOP(opcode, op3, arch_mask) \ -{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } - -const struct sparc_opcode sparc_opcodes[] = { - -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ - -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ - -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ - -/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the - 'ld' pseudo-op in v9. */ -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ - -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ - -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ - -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ - -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ - -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ - -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ - -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ - -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ - -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ - -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ - -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ - -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ - -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ - -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ - -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ - -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ - -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ - -{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ - -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ - -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ - -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ - -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ - -{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ -{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ - -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ - -{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ -{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ - -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ - -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ - -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ - -{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ - -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ - -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ - -{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ -{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ - -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ - -{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ -{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ - -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ - -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ - -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ - -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ - -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ - -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ - -{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, -{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, - -{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ -{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ - -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, - -{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, - -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, - -/* IFLUSH was renamed to FLUSH in v8. */ -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, - -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, - -{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, - -{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, -{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, - -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ - -{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, -{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, -{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, - -{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, -{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, -{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, - -{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, - -{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, -{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, - -{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, -{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, - -{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS2_G0|ASI(~0),"2,d", 0, v9 }, -{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS2_G0, "i,d", 0, v9 }, - -{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ -{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ - -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ - -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ - -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ - -{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, - -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ -{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ - -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ -{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ -{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ -{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ - -{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ -{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ -{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ -{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ -{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ -{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ - -{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ -{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ -{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ -{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ -{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ -{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ -{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ -{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ -{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ -{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ -{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ -{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ -{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ -{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ -{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ -{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ - -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ -{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ -{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ -{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ - -{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ -{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ -{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ -{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ - -{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ -{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ -{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ - -{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ - -/* ??? This group seems wrong. A three operand move? */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ - -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ -{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ -{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ -{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ - -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ - -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ - -{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, - -{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ -{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ - -/* This is not a commutative instruction. */ -{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, - -{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ -{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ - -{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ -{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ - -{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, - -{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, - -{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, -{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, - -{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, -{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, - -{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, - -{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, - -{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ -{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ -{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ -{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ -{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ -{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ -{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ -{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ - -{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ -{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ - -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ - -{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, - -{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, -{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, - -{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, -{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, - -{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, - -{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, -{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, -{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, - -{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, -{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, - -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, - - -/* Conditional instructions. - - Because this part of the table was such a mess earlier, I have - macrofied it so that all the branches and traps are generated from - a single-line description of each condition value. John Gilmore. */ - -/* Define branches -- one annulled, one without, etc. */ -#define br(opcode, mask, lose, flags) \ - { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ - { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } - -#define brx(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ - { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ - { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } - -/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ -#define tr(opcode, mask, lose, flags) \ - { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ - { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ - { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ - { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ - { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ - { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ - { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ - { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ - { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ - { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ - { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ - { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ - -/* v9: We must put `brx' before `br', to ensure that we never match something - v9: against an expression unless it is an expression. Otherwise, we end - v9: up with undefined symbol tables entries, because they get added, but - v9: are not deleted if the pattern fails to match. */ - -/* Define both branches and traps based on condition mask */ -#define cond(bop, top, mask, flags) \ - brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ - br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ - tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) - -/* Define all the conditions, all the branches, all the traps. */ - -/* Standard branch, trap mnemonics */ -cond ("b", "ta", CONDA, F_UNBR), -/* Alternative form (just for assembly, not for disassembly) */ -cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), - -cond ("bcc", "tcc", CONDCC, F_CONDBR), -cond ("bcs", "tcs", CONDCS, F_CONDBR), -cond ("be", "te", CONDE, F_CONDBR), -cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), -cond ("bg", "tg", CONDG, F_CONDBR), -cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), -cond ("bge", "tge", CONDGE, F_CONDBR), -cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ -cond ("bgu", "tgu", CONDGU, F_CONDBR), -cond ("bl", "tl", CONDL, F_CONDBR), -cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), -cond ("ble", "tle", CONDLE, F_CONDBR), -cond ("bleu", "tleu", CONDLEU, F_CONDBR), -cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ -cond ("bn", "tn", CONDN, F_CONDBR), -cond ("bne", "tne", CONDNE, F_CONDBR), -cond ("bneg", "tneg", CONDNEG, F_CONDBR), -cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ -cond ("bpos", "tpos", CONDPOS, F_CONDBR), -cond ("bvc", "tvc", CONDVC, F_CONDBR), -cond ("bvs", "tvs", CONDVS, F_CONDBR), -cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ - -#undef cond -#undef br -#undef brr /* v9 */ -#undef tr - -#define brr(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } - -#define condr(bop, mask, flags) /* v9 */ \ - brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ - -/* v9 */ condr("brnz", 0x5, F_CONDBR), -/* v9 */ condr("brz", 0x1, F_CONDBR), -/* v9 */ condr("brgez", 0x7, F_CONDBR), -/* v9 */ condr("brlz", 0x3, F_CONDBR), -/* v9 */ condr("brlez", 0x2, F_CONDBR), -/* v9 */ condr("brgz", 0x6, F_CONDBR), - -#undef condr /* v9 */ -#undef brr /* v9 */ - -#define movr(opcode, mask, flags) /* v9 */ \ - { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ - { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } - -#define fmrrs(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } -#define fmrrd(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } -#define fmrrq(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } - -#define fmovrs(mop, mask, flags) /* v9 */ \ - fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ -#define fmovrd(mop, mask, flags) /* v9 */ \ - fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ -#define fmovrq(mop, mask, flags) /* v9 */ \ - fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ - -/* v9 */ movr("movrne", 0x5, 0), -/* v9 */ movr("movre", 0x1, 0), -/* v9 */ movr("movrgez", 0x7, 0), -/* v9 */ movr("movrlz", 0x3, 0), -/* v9 */ movr("movrlez", 0x2, 0), -/* v9 */ movr("movrgz", 0x6, 0), -/* v9 */ movr("movrnz", 0x5, F_ALIAS), -/* v9 */ movr("movrz", 0x1, F_ALIAS), - -/* v9 */ fmovrs("fmovrsne", 0x5, 0), -/* v9 */ fmovrs("fmovrse", 0x1, 0), -/* v9 */ fmovrs("fmovrsgez", 0x7, 0), -/* v9 */ fmovrs("fmovrslz", 0x3, 0), -/* v9 */ fmovrs("fmovrslez", 0x2, 0), -/* v9 */ fmovrs("fmovrsgz", 0x6, 0), -/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), -/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), - -/* v9 */ fmovrd("fmovrdne", 0x5, 0), -/* v9 */ fmovrd("fmovrde", 0x1, 0), -/* v9 */ fmovrd("fmovrdgez", 0x7, 0), -/* v9 */ fmovrd("fmovrdlz", 0x3, 0), -/* v9 */ fmovrd("fmovrdlez", 0x2, 0), -/* v9 */ fmovrd("fmovrdgz", 0x6, 0), -/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), -/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), - -/* v9 */ fmovrq("fmovrqne", 0x5, 0), -/* v9 */ fmovrq("fmovrqe", 0x1, 0), -/* v9 */ fmovrq("fmovrqgez", 0x7, 0), -/* v9 */ fmovrq("fmovrqlz", 0x3, 0), -/* v9 */ fmovrq("fmovrqlez", 0x2, 0), -/* v9 */ fmovrq("fmovrqgz", 0x6, 0), -/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), -/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), - -#undef movr /* v9 */ -#undef fmovr /* v9 */ -#undef fmrr /* v9 */ - -#define movicc(opcode, cond, flags) /* v9 */ \ - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } - -#define movfcc(opcode, fcond, flags) /* v9 */ \ - { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } - -#define movcc(opcode, cond, fcond, flags) /* v9 */ \ - movfcc (opcode, fcond, flags), /* v9 */ \ - movicc (opcode, cond, flags) /* v9 */ - -/* v9 */ movcc ("mova", CONDA, FCONDA, 0), -/* v9 */ movicc ("movcc", CONDCC, 0), -/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), -/* v9 */ movicc ("movcs", CONDCS, 0), -/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), -/* v9 */ movcc ("move", CONDE, FCONDE, 0), -/* v9 */ movcc ("movg", CONDG, FCONDG, 0), -/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), -/* v9 */ movicc ("movgu", CONDGU, 0), -/* v9 */ movcc ("movl", CONDL, FCONDL, 0), -/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), -/* v9 */ movicc ("movleu", CONDLEU, 0), -/* v9 */ movfcc ("movlg", FCONDLG, 0), -/* v9 */ movcc ("movn", CONDN, FCONDN, 0), -/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), -/* v9 */ movicc ("movneg", CONDNEG, 0), -/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ movfcc ("movo", FCONDO, 0), -/* v9 */ movicc ("movpos", CONDPOS, 0), -/* v9 */ movfcc ("movu", FCONDU, 0), -/* v9 */ movfcc ("movue", FCONDUE, 0), -/* v9 */ movfcc ("movug", FCONDUG, 0), -/* v9 */ movfcc ("movuge", FCONDUGE, 0), -/* v9 */ movfcc ("movul", FCONDUL, 0), -/* v9 */ movfcc ("movule", FCONDULE, 0), -/* v9 */ movicc ("movvc", CONDVC, 0), -/* v9 */ movicc ("movvs", CONDVS, 0), -/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), - -#undef movicc /* v9 */ -#undef movfcc /* v9 */ -#undef movcc /* v9 */ - -#define FM_SF 1 /* v9 - values for fpsize */ -#define FM_DF 2 /* v9 */ -#define FM_QF 3 /* v9 */ - -#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 } - -#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 } - -/* FIXME: use fmovicc/fmovfcc? */ /* v9 */ -#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 } - -/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0), -/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0), -/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0), -/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0), -/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0), -/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0), -/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0), -/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0), -/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0), -/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0), -/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0), -/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0), -/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0), -/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0), -/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0), -/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0), -/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0), -/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0), -/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0), -/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0), -/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0), -/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0), -/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0), -/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0), -/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0), -/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0), -/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0), -/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0), -/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0), -/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0), -/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0), -/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0), -/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0), -/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS), -/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS), -/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS), -/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0), -/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0), -/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0), -/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0), -/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0), -/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0), -/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0), -/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0), -/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0), -/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0), -/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0), -/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0), -/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0), -/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0), -/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0), -/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0), -/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0), -/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0), -/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0), -/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0), -/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0), -/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0), -/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0), -/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0), -/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0), -/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0), -/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0), -/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0), -/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0), -/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0), -/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0), -/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0), -/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0), -/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0), -/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0), -/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0), -/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0), -/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0), -/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0), -/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS), -/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS), -/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS), - -#undef fmovicc /* v9 */ -#undef fmovfcc /* v9 */ -#undef fmovcc /* v9 */ -#undef FM_DF /* v9 */ -#undef FM_QF /* v9 */ -#undef FM_SF /* v9 */ - -/* Coprocessor branches. */ -#define CBR(opcode, mask, lose, flags, arch) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch } - -/* Floating point branches. */ -#define FBR(opcode, mask, lose, flags) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 } - -/* V9 extended floating point branches. */ -#define FBRX(opcode, mask, lose, flags) /* v9 */ \ - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } - -/* v9: We must put `FBRX' before `FBR', to ensure that we never match - v9: something against an expression unless it is an expression. Otherwise, - v9: we end up with undefined symbol tables entries, because they get added, - v9: but are not deleted if the pattern fails to match. */ - -#define CONDFC(fop, cop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ - CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) - -#define CONDFCL(fop, cop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ - CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) - -#define CONDF(fop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) - -CONDFC ("fb", "cb", 0x8, 0), -CONDFCL ("fba", "cba", 0x8, F_ALIAS), -CONDFC ("fbe", "cb0", 0x9, 0), -CONDF ("fbz", 0x9, F_ALIAS), -CONDFC ("fbg", "cb2", 0x6, 0), -CONDFC ("fbge", "cb02", 0xb, 0), -CONDFC ("fbl", "cb1", 0x4, 0), -CONDFC ("fble", "cb01", 0xd, 0), -CONDFC ("fblg", "cb12", 0x2, 0), -CONDFCL ("fbn", "cbn", 0x0, 0), -CONDFC ("fbne", "cb123", 0x1, 0), -CONDF ("fbnz", 0x1, F_ALIAS), -CONDFC ("fbo", "cb012", 0xf, 0), -CONDFC ("fbu", "cb3", 0x7, 0), -CONDFC ("fbue", "cb03", 0xa, 0), -CONDFC ("fbug", "cb23", 0x5, 0), -CONDFC ("fbuge", "cb023", 0xc, 0), -CONDFC ("fbul", "cb13", 0x3, 0), -CONDFC ("fbule", "cb013", 0xe, 0), - -#undef CONDFC -#undef CONDFCL -#undef CONDF -#undef CBR -#undef FBR -#undef FBRX /* v9 */ - -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ - -{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ - -{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, -{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, -{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, -{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, - -{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, - -{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, - -{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, -{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, - -{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, -{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, - -/* This *is* a commutative instruction. */ -{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, -/* This *is* a commutative instruction. */ -{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, -{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, - -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ - -{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ -{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ - -/* FPop1 and FPop2 are not instructions. Don't accept them. */ - -{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, -{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, - -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, - -{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, -{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, - -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, - -{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, -{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, -{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, -{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, -{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, -{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, - -{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, -{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, -{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, -{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, -{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, -{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, - -{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, -{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, -{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, - -{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, -{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, -{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, - -{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, -{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, -{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, -{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, - -{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, -{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, -{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, -{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, -{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, -{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, - -#define CMPFCC(x) (((x)&0x3)<<25) - -{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, -{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, -{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, -{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, -{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, -{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, -{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, -{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, -{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, -{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, -{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, -{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, -{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, -{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, - -/* These Extended FPop (FIFO) instructions are new in the Fujitsu - MB86934, replacing the CPop instructions from v6 and later - processors. */ - -#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } -#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } -#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } - -EFPOP1_2 ("efitod", 0x0c8, "f,H"), -EFPOP1_2 ("efitos", 0x0c4, "f,g"), -EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), -EFPOP1_2 ("efstoi", 0x0d1, "f,g"), -EFPOP1_2 ("efstod", 0x0c9, "f,H"), -EFPOP1_2 ("efdtos", 0x0c6, "B,g"), -EFPOP1_2 ("efmovs", 0x001, "f,g"), -EFPOP1_2 ("efnegs", 0x005, "f,g"), -EFPOP1_2 ("efabss", 0x009, "f,g"), -EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), -EFPOP1_2 ("efsqrts", 0x029, "f,g"), -EFPOP1_3 ("efaddd", 0x042, "v,B,H"), -EFPOP1_3 ("efadds", 0x041, "e,f,g"), -EFPOP1_3 ("efsubd", 0x046, "v,B,H"), -EFPOP1_3 ("efsubs", 0x045, "e,f,g"), -EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), -EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), -EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), -EFPOP1_3 ("efmuls", 0x049, "e,f,g"), -EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), -EFPOP2_2 ("efcmpd", 0x052, "v,B"), -EFPOP2_2 ("efcmped", 0x056, "v,B"), -EFPOP2_2 ("efcmps", 0x051, "e,f"), -EFPOP2_2 ("efcmpes", 0x055, "e,f"), - -#undef EFPOP1_2 -#undef EFPOP1_3 -#undef EFPOP2_2 - -/* These are marked F_ALIAS, so that they won't conflict with sparclite insns - present. Otherwise, the F_ALIAS flag is ignored. */ -{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, -{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, - -/* sparclet specific insns */ - -COMMUTEOP ("umac", 0x3e, sparclet), -COMMUTEOP ("smac", 0x3f, sparclet), -COMMUTEOP ("umacd", 0x2e, sparclet), -COMMUTEOP ("smacd", 0x2f, sparclet), -COMMUTEOP ("umuld", 0x09, sparclet), -COMMUTEOP ("smuld", 0x0d, sparclet), - -{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, -{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, - -/* The manual isn't completely accurate on these insns. The `rs2' field is - treated as being 6 bits to account for 6 bit immediates to cpush. It is - assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ -#define BIT5 (1<<5) -{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, -{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, -{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, -{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, -{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, -{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, -{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, -#undef BIT5 - -/* sparclet coprocessor branch insns */ -#define SLCBCC2(opcode, mask, lose) \ - { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } -#define SLCBCC(opcode, mask) \ - SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) - -/* cbn,cba can't be defined here because they're defined elsewhere and GAS - requires all mnemonics of the same name to be consecutive. */ -/*SLCBCC("cbn", 0), - already defined */ -SLCBCC("cbe", 1), -SLCBCC("cbf", 2), -SLCBCC("cbef", 3), -SLCBCC("cbr", 4), -SLCBCC("cber", 5), -SLCBCC("cbfr", 6), -SLCBCC("cbefr", 7), -/*SLCBCC("cba", 8), - already defined */ -SLCBCC("cbne", 9), -SLCBCC("cbnf", 10), -SLCBCC("cbnef", 11), -SLCBCC("cbnr", 12), -SLCBCC("cbner", 13), -SLCBCC("cbnfr", 14), -SLCBCC("cbnefr", 15), - -#undef SLCBCC2 -#undef SLCBCC - -{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, -{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, -{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, -{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, - -/* v9 synthetic insns */ -{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ -{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ -{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ -{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ -{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ - -/* Ultrasparc extensions */ -{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, - -/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ -{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, -{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, -{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, -{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, -{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, -{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, -{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, -{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, - -{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, -{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, -{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, -{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, -{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, - -/* Note that the mixing of 32/64 bit regs is intentional. */ -{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, -{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, -{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, -{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, -{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, -{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, -{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, - -{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, -{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, -{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, - -{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, -{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, -{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, -{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, -{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, -{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, -{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, -{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, -{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, -{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, -{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, -{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, -{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, -{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, -{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, -{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, -{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, -{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, -{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, -{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, -{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, -{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, -{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, -{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, -{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, -{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, -{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, -{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, -{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, -{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, -{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, -{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, - -{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, -{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, -{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, -{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, -{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, -{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, -{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, -{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, - -{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, -{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, -{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, -{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, -{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, -{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, - -{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, - -{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, -{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, -{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, - -/* More v9 specific insns, these need to come last so they do not clash - with v9a instructions such as "edge8" which looks like impdep1. */ - -#define IMPDEP(name, code) \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ -{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } - -IMPDEP ("impdep1", 0x36), -IMPDEP ("impdep2", 0x37), - -#undef IMPDEP - -}; - -const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); - -/* Utilities for argument parsing. */ - -typedef struct -{ - int value; - const char *name; -} arg; - -/* Look up NAME in TABLE. */ - -static int lookup_name PARAMS ((const arg *, const char *)); -static const char *lookup_value PARAMS ((const arg *, int)); - -static int -lookup_name (table, name) - const arg *table; - const char *name; -{ - const arg *p; - - for (p = table; p->name; ++p) - if (strcmp (name, p->name) == 0) - return p->value; - - return -1; -} - -/* Look up VALUE in TABLE. */ - -static const char * -lookup_value (table, value) - const arg *table; - int value; -{ - const arg *p; - - for (p = table; p->name; ++p) - if (value == p->value) - return p->name; - - return (char *) 0; -} - -/* Handle ASI's. */ - -static arg asi_table[] = -{ - /* These are in the v9 architecture manual. */ - /* The shorter versions appear first, they're here because Sun's as has them. - Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the - UltraSPARC architecture manual). */ - { 0x04, "#ASI_N" }, - { 0x0c, "#ASI_N_L" }, - { 0x10, "#ASI_AIUP" }, - { 0x11, "#ASI_AIUS" }, - { 0x18, "#ASI_AIUP_L" }, - { 0x19, "#ASI_AIUS_L" }, - { 0x80, "#ASI_P" }, - { 0x81, "#ASI_S" }, - { 0x82, "#ASI_PNF" }, - { 0x83, "#ASI_SNF" }, - { 0x88, "#ASI_P_L" }, - { 0x89, "#ASI_S_L" }, - { 0x8a, "#ASI_PNF_L" }, - { 0x8b, "#ASI_SNF_L" }, - { 0x04, "#ASI_NUCLEUS" }, - { 0x0c, "#ASI_NUCLEUS_LITTLE" }, - { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, - { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, - { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, - { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, - { 0x80, "#ASI_PRIMARY" }, - { 0x81, "#ASI_SECONDARY" }, - { 0x82, "#ASI_PRIMARY_NOFAULT" }, - { 0x83, "#ASI_SECONDARY_NOFAULT" }, - { 0x88, "#ASI_PRIMARY_LITTLE" }, - { 0x89, "#ASI_SECONDARY_LITTLE" }, - { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, - { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, - /* These are UltraSPARC extensions. */ - /* FIXME: There are dozens of them. Not sure we want them all. - Most are for kernel building but some are for vis type stuff. */ - { 0, 0 } -}; - -/* Return the value for ASI NAME, or -1 if not found. */ - -int -sparc_encode_asi (name) - const char *name; -{ - return lookup_name (asi_table, name); -} - -/* Return the name for ASI value VALUE or NULL if not found. */ - -const char * -sparc_decode_asi (value) - int value; -{ - return lookup_value (asi_table, value); -} - -/* Handle membar masks. */ - -static arg membar_table[] = -{ - { 0x40, "#Sync" }, - { 0x20, "#MemIssue" }, - { 0x10, "#Lookaside" }, - { 0x08, "#StoreStore" }, - { 0x04, "#LoadStore" }, - { 0x02, "#StoreLoad" }, - { 0x01, "#LoadLoad" }, - { 0, 0 } -}; - -/* Return the value for membar arg NAME, or -1 if not found. */ - -int -sparc_encode_membar (name) - const char *name; -{ - return lookup_name (membar_table, name); -} - -/* Return the name for membar value VALUE or NULL if not found. */ - -const char * -sparc_decode_membar (value) - int value; -{ - return lookup_value (membar_table, value); -} - -/* Handle prefetch args. */ - -static arg prefetch_table[] = -{ - { 0, "#n_reads" }, - { 1, "#one_read" }, - { 2, "#n_writes" }, - { 3, "#one_write" }, - { 4, "#page" }, - { 0, 0 } -}; - -/* Return the value for prefetch arg NAME, or -1 if not found. */ - -int -sparc_encode_prefetch (name) - const char *name; -{ - return lookup_name (prefetch_table, name); -} - -/* Return the name for prefetch value VALUE or NULL if not found. */ - -const char * -sparc_decode_prefetch (value) - int value; -{ - return lookup_value (prefetch_table, value); -} - -/* Handle sparclet coprocessor registers. */ - -static arg sparclet_cpreg_table[] = -{ - { 0, "%ccsr" }, - { 1, "%ccfr" }, - { 2, "%cccrcr" }, - { 3, "%ccpr" }, - { 4, "%ccsr2" }, - { 5, "%cccrr" }, - { 6, "%ccrstr" }, - { 0, 0 } -}; - -/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ - -int -sparc_encode_sparclet_cpreg (name) - const char *name; -{ - return lookup_name (sparclet_cpreg_table, name); -} - -/* Return the name for sparclet cpreg value VALUE or NULL if not found. */ - -const char * -sparc_decode_sparclet_cpreg (value) - int value; -{ - return lookup_value (sparclet_cpreg_table, value); -} diff --git a/contrib/binutils/opcodes/stamp-h.in b/contrib/binutils/opcodes/stamp-h.in deleted file mode 100644 index 9788f70238c91..0000000000000 --- a/contrib/binutils/opcodes/stamp-h.in +++ /dev/null @@ -1 +0,0 @@ -timestamp diff --git a/contrib/binutils/opcodes/sysdep.h b/contrib/binutils/opcodes/sysdep.h deleted file mode 100644 index bb23e5fcf5d3c..0000000000000 --- a/contrib/binutils/opcodes/sysdep.h +++ /dev/null @@ -1,42 +0,0 @@ -/* Random host-dependent support code. - Copyright (C) 1995, 1997 Free Software Foundation, Inc. - Written by Ken Raeburn. - -This file is part of libopcodes, the opcodes library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* Do system-dependent stuff, mainly driven by autoconf-detected info. - - Well, some generic common stuff is done here too, like including - ansidecl.h. That's because the .h files in bfd/hosts files I'm - trying to replace often did that. If it can be dropped from this - file (check in a non-ANSI environment!), it should be. */ - -#include "config.h" - -#include <ansidecl.h> - -#ifdef HAVE_STDLIB_H -#include <stdlib.h> -#endif - -#ifdef HAVE_STRING_H -#include <string.h> -#else -#ifdef HAVE_STRINGS_H -#include <strings.h> -#endif -#endif diff --git a/contrib/binutils/opcodes/tic30-dis.c b/contrib/binutils/opcodes/tic30-dis.c deleted file mode 100644 index 5ccf893f2f2f4..0000000000000 --- a/contrib/binutils/opcodes/tic30-dis.c +++ /dev/null @@ -1,710 +0,0 @@ -/* Disassembly routines for TMS320C30 architecture - Copyright (C) 1998, 1999 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <errno.h> -#include <math.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/tic30.h" - -#define NORMAL_INSN 1 -#define PARALLEL_INSN 2 - -/* Gets the type of instruction based on the top 2 or 3 bits of the - instruction word. */ -#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) - -/* Instruction types. */ -#define TWO_OPERAND_1 0x00000000 -#define TWO_OPERAND_2 0x40000000 -#define THREE_OPERAND 0x20000000 -#define PAR_STORE 0xC0000000 -#define MUL_ADDS 0x80000000 -#define BRANCHES 0x60000000 - -/* Specific instruction id bits. */ -#define NORMAL_IDEN 0x1F800000 -#define PAR_STORE_IDEN 0x3E000000 -#define MUL_ADD_IDEN 0x2C000000 -#define BR_IMM_IDEN 0x1F000000 -#define BR_COND_IDEN 0x1C3F0000 - -/* Addressing modes. */ -#define AM_REGISTER 0x00000000 -#define AM_DIRECT 0x00200000 -#define AM_INDIRECT 0x00400000 -#define AM_IMM 0x00600000 - -#define P_FIELD 0x03000000 - -#define REG_AR0 0x08 -#define LDP_INSN 0x08700000 - -/* TMS320C30 program counter for current instruction. */ -static unsigned int _pc; - -struct instruction - { - int type; - template *tm; - partemplate *ptm; - }; - -int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); -int print_two_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_three_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_par_insn - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_branch - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int get_indirect_operand PARAMS ((unsigned short, int, char *)); -int get_register_operand PARAMS ((unsigned char, char *)); -int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *)); - -int -print_insn_tic30 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - unsigned long insn_word; - struct instruction insn = - {0, NULL, NULL}; - bfd_vma bufaddr = pc - info->buffer_vma; - /* Obtain the current instruction word from the buffer. */ - insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | - (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); - _pc = pc / 4; - /* Get the instruction refered to by the current instruction word - and print it out based on its type. */ - if (!get_tic30_instruction (insn_word, &insn)) - return -1; - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - if (!print_two_operand (info, insn_word, &insn)) - return -1; - break; - case THREE_OPERAND: - if (!print_three_operand (info, insn_word, &insn)) - return -1; - break; - case PAR_STORE: - case MUL_ADDS: - if (!print_par_insn (info, insn_word, &insn)) - return -1; - break; - case BRANCHES: - if (!print_branch (info, insn_word, &insn)) - return -1; - break; - } - return 4; -} - -int -get_tic30_instruction (insn_word, insn) - unsigned long insn_word; - struct instruction *insn; -{ - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - case THREE_OPERAND: - insn->type = NORMAL_INSN; - { - template *current_optab = (template *) tic30_optab; - for (; current_optab < tic30_optab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if (current_optab->operands == 0) - { - if (current_optab->base_opcode == insn_word) - { - insn->tm = current_optab; - break; - } - } - else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) - { - insn->tm = current_optab; - break; - } - } - } - } - break; - case PAR_STORE: - insn->type = PARALLEL_INSN; - { - partemplate *current_optab = (partemplate *) tic30_paroptab; - for (; current_optab < tic30_paroptab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN)) - { - insn->ptm = current_optab; - break; - } - } - } - } - break; - case MUL_ADDS: - insn->type = PARALLEL_INSN; - { - partemplate *current_optab = (partemplate *) tic30_paroptab; - for (; current_optab < tic30_paroptab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN)) - { - insn->ptm = current_optab; - break; - } - } - } - } - break; - case BRANCHES: - insn->type = NORMAL_INSN; - { - template *current_optab = (template *) tic30_optab; - for (; current_optab < tic30_optab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if (current_optab->operand_types[0] & Imm24) - { - if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN)) - { - insn->tm = current_optab; - break; - } - } - else if (current_optab->operands > 0) - { - if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN)) - { - insn->tm = current_optab; - break; - } - } - else - { - if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000))) - { - insn->tm = current_optab; - break; - } - } - } - } - } - break; - default: - return 0; - } - return 1; -} - -int -print_two_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char name[12]; - char operand[2][13] = - { - {0}, - {0}}; - float f_number; - - if (insn->tm == NULL) - return 0; - strcpy (name, insn->tm->name); - if (insn->tm->opcode_modifier == AddressMode) - { - int src_op, dest_op; - /* Determine whether instruction is a store or a normal instruction. */ - if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) - { - src_op = 1; - dest_op = 0; - } - else - { - src_op = 0; - dest_op = 1; - } - /* Get the destination register. */ - if (insn->tm->operands == 2) - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); - /* Get the source operand based on addressing mode. */ - switch (insn_word & AddressMode) - { - case AM_REGISTER: - /* Check for the NOP instruction before getting the operand. */ - if ((insn->tm->operand_types[0] & NotReq) == 0) - get_register_operand ((insn_word & 0x0000001F), operand[src_op]); - break; - case AM_DIRECT: - sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); - break; - case AM_INDIRECT: - get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); - break; - case AM_IMM: - /* Get the value of the immediate operand based on variable type. */ - switch (insn->tm->imm_arg_type) - { - case Imm_Float: - cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); - sprintf (operand[src_op], "%2.2f", f_number); - break; - case Imm_SInt: - sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); - break; - case Imm_UInt: - sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); - break; - default: - return 0; - } - /* Handle special case for LDP instruction. */ - if ((insn_word & 0xFFFFFF00) == LDP_INSN) - { - strcpy (name, "ldp"); - sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); - operand[1][0] = '\0'; - } - } - } - /* Handle case for stack and rotate instructions. */ - else if (insn->tm->operands == 1) - { - if (insn->tm->opcode_modifier == StackOp) - { - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); - } - } - /* Output instruction to stream. */ - info->fprintf_func (info->stream, " %s %s%c%s", name, - operand[0][0] ? operand[0] : "", - operand[1][0] ? ',' : ' ', - operand[1][0] ? operand[1] : ""); - return 1; -} - -int -print_three_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char operand[3][13] = - { - {0}, - {0}, - {0}}; - - if (insn->tm == NULL) - return 0; - switch (insn_word & AddressMode) - { - case AM_REGISTER: - get_register_operand ((insn_word & 0x000000FF), operand[0]); - get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); - break; - case AM_DIRECT: - get_register_operand ((insn_word & 0x000000FF), operand[0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); - break; - case AM_INDIRECT: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); - get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); - break; - case AM_IMM: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); - break; - default: - return 0; - } - if (insn->tm->operands == 3) - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); - info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, - operand[0], operand[1], - operand[2][0] ? ',' : ' ', - operand[2][0] ? operand[2] : ""); - return 1; -} - -int -print_par_insn (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - size_t i, len; - char *name1, *name2; - char operand[2][3][13] = - { - { - {0}, - {0}, - {0}}, - { - {0}, - {0}, - {0}}}; - - if (insn->ptm == NULL) - return 0; - /* Parse out the names of each of the parallel instructions from the - q_insn1_insn2 format. */ - name1 = (char *) strdup (insn->ptm->name + 2); - name2 = ""; - len = strlen (name1); - for (i = 0; i < len; i++) - { - if (name1[i] == '_') - { - name2 = &name1[i + 1]; - name1[i] = '\0'; - break; - } - } - /* Get the operands of the instruction based on the operand order. */ - switch (insn->ptm->oporder) - { - case OO_4op1: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); - break; - case OO_4op2: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); - break; - case OO_4op3: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); - break; - case OO_5op1: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); - break; - case OO_5op2: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); - break; - case OO_PField: - if (insn_word & 0x00800000) - get_register_operand (0x01, operand[0][2]); - else - get_register_operand (0x00, operand[0][2]); - if (insn_word & 0x00400000) - get_register_operand (0x03, operand[1][2]); - else - get_register_operand (0x02, operand[1][2]); - switch (insn_word & P_FIELD) - { - case 0x00000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); - break; - case 0x01000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - break; - case 0x02000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); - break; - case 0x03000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - break; - } - break; - default: - return 0; - } - info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, - operand[0][0], operand[0][1], - operand[0][2][0] ? ',' : ' ', - operand[0][2][0] ? operand[0][2] : ""); - info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, - operand[1][0], operand[1][1], - operand[1][2][0] ? ',' : ' ', - operand[1][2][0] ? operand[1][2] : ""); - free (name1); - return 1; -} - -int -print_branch (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char operand[2][13] = - { - {0}, - {0}}; - unsigned long address; - int print_label = 0; - - if (insn->tm == NULL) - return 0; - /* Get the operands for 24-bit immediate jumps. */ - if (insn->tm->operand_types[0] & Imm24) - { - address = insn_word & 0x00FFFFFF; - sprintf (operand[0], "0x%lX", address); - print_label = 1; - } - /* Get the operand for the trap instruction. */ - else if (insn->tm->operand_types[0] & IVector) - { - address = insn_word & 0x0000001F; - sprintf (operand[0], "0x%lX", address); - } - else - { - address = insn_word & 0x0000FFFF; - /* Get the operands for the DB instructions. */ - if (insn->tm->operands == 2) - { - get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); - if (insn_word & PCRel) - { - sprintf (operand[1], "%d", (short) address); - print_label = 1; - } - else - get_register_operand (insn_word & 0x0000001F, operand[1]); - } - /* Get the operands for the standard branches. */ - else if (insn->tm->operands == 1) - { - if (insn_word & PCRel) - { - address = (short) address; - sprintf (operand[0], "%ld", address); - print_label = 1; - } - else - get_register_operand (insn_word & 0x0000001F, operand[0]); - } - } - info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, - operand[0][0] ? operand[0] : "", - operand[1][0] ? ',' : ' ', - operand[1][0] ? operand[1] : ""); - /* Print destination of branch in relation to current symbol. */ - if (print_label && info->symbols) - { - asymbol *sym = *info->symbols; - - if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) - { - address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); - /* Check for delayed instruction, if so adjust destination. */ - if (insn_word & 0x00200000) - address += 2; - } - else - { - address -= ((sym->section->vma + sym->value) / 4); - } - if (address == 0) - info->fprintf_func (info->stream, " <%s>", sym->name); - else - info->fprintf_func (info->stream, " <%s %c %d>", sym->name, - ((short) address < 0) ? '-' : '+', - abs (address)); - } - return 1; -} - -int -get_indirect_operand (fragment, size, buffer) - unsigned short fragment; - int size; - char *buffer; -{ - unsigned char mod; - unsigned arnum; - unsigned char disp; - - if (buffer == NULL) - return 0; - /* Determine which bits identify the sections of the indirect operand based on the - size in bytes. */ - switch (size) - { - case 1: - mod = (fragment & 0x00F8) >> 3; - arnum = (fragment & 0x0007); - disp = 0; - break; - case 2: - mod = (fragment & 0xF800) >> 11; - arnum = (fragment & 0x0700) >> 8; - disp = (fragment & 0x00FF); - break; - default: - return 0; - } - { - const ind_addr_type *current_ind = tic30_indaddr_tab; - for (; current_ind < tic30_indaddrtab_end; current_ind++) - { - if (current_ind->modfield == mod) - { - if (current_ind->displacement == IMPLIED_DISP && size == 2) - { - continue; - } - else - { - size_t i, len; - int bufcnt; - - len = strlen (current_ind->syntax); - for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) - { - buffer[bufcnt] = current_ind->syntax[i]; - if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') - buffer[++bufcnt] = arnum + '0'; - if (buffer[bufcnt] == '(' && current_ind->displacement == DISP_REQUIRED) - { - sprintf (&buffer[bufcnt + 1], "%u", disp); - bufcnt += strlen (&buffer[bufcnt + 1]); - } - } - buffer[bufcnt + 1] = '\0'; - break; - } - } - } - } - return 1; -} - -int -get_register_operand (fragment, buffer) - unsigned char fragment; - char *buffer; -{ - const reg *current_reg = tic30_regtab; - - if (buffer == NULL) - return 0; - for (; current_reg < tic30_regtab_end; current_reg++) - { - if ((fragment & 0x1F) == current_reg->opcode) - { - strcpy (buffer, current_reg->name); - return 1; - } - } - return 0; -} - -int -cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat) - unsigned long tmsfloat; - int size; - float *ieeefloat; -{ - unsigned long exp, sign, mant; - - if (size == 2) - { - if ((tmsfloat & 0x0000F000) == 0x00008000) - tmsfloat = 0x80000000; - else - { - tmsfloat <<= 16; - tmsfloat = (long) tmsfloat >> 4; - } - } - exp = tmsfloat & 0xFF000000; - if (exp == 0x80000000) - { - *ieeefloat = 0.0; - return 1; - } - exp += 0x7F000000; - sign = (tmsfloat & 0x00800000) << 8; - mant = tmsfloat & 0x007FFFFF; - if (exp == 0xFF000000) - { - if (mant == 0) - *ieeefloat = ERANGE; - if (sign == 0) - *ieeefloat = 1.0 / 0.0; - else - *ieeefloat = -1.0 / 0.0; - return 1; - } - exp >>= 1; - if (sign) - { - mant = (~mant) & 0x007FFFFF; - mant += 1; - exp += mant & 0x00800000; - exp &= 0x7F800000; - mant &= 0x007FFFFF; - } - if (tmsfloat == 0x80000000) - sign = mant = exp = 0; - tmsfloat = sign | exp | mant; - *ieeefloat = *((float *) &tmsfloat); - return 1; -} diff --git a/contrib/binutils/opcodes/v850-dis.c b/contrib/binutils/opcodes/v850-dis.c deleted file mode 100644 index d817f80bcebc9..0000000000000 --- a/contrib/binutils/opcodes/v850-dis.c +++ /dev/null @@ -1,381 +0,0 @@ -/* Disassemble V850 instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#include <stdio.h> - -#include "sysdep.h" -#include "opcode/v850.h" -#include "dis-asm.h" -#include "opintl.h" - -static const char *const v850_reg_names[] = -{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" }; - -static const char *const v850_sreg_names[] = -{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", - "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", - "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", - "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", - "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", - "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" }; - -static const char *const v850_cc_names[] = -{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", - "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" }; - -static int -disassemble (memaddr, info, insn) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; -{ - struct v850_opcode * op = (struct v850_opcode *)v850_opcodes; - const struct v850_operand * operand; - int match = 0; - int short_op = ((insn & 0x0600) != 0x0600); - int bytes_read; - int target_processor; - - /* Special case: 32 bit MOV */ - if ((insn & 0xffe0) == 0x0620) - short_op = true; - - bytes_read = short_op ? 2 : 4; - - /* If this is a two byte insn, then mask off the high bits. */ - if (short_op) - insn &= 0xffff; - - switch (info->mach) - { - case 0: - default: - target_processor = PROCESSOR_V850; - break; - - case bfd_mach_v850e: - target_processor = PROCESSOR_V850E; - break; - - case bfd_mach_v850ea: - target_processor = PROCESSOR_V850EA; - break; - } - - /* Find the opcode. */ - while (op->name) - { - if ((op->mask & insn) == op->opcode - && (op->processors & target_processor)) - { - const unsigned char * opindex_ptr; - unsigned int opnum; - unsigned int memop; - - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); -/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/ - - memop = op->memop; - /* Now print the operands. - - MEMOP is the operand number at which a memory - address specification starts, or zero if this - instruction has no memory addresses. - - A memory address is always two arguments. - - This information allows us to determine when to - insert commas into the output stream as well as - when to insert disp[reg] expressions onto the - output stream. */ - - for (opindex_ptr = op->operands, opnum = 1; - *opindex_ptr != 0; - opindex_ptr++, opnum++) - { - long value; - int flag; - int status; - bfd_byte buffer[ 4 ]; - - operand = &v850_operands[*opindex_ptr]; - - if (operand->extract) - value = (operand->extract) (insn, 0); - else - { - if (operand->bits == -1) - value = (insn & operand->shift); - else - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - - if (operand->flags & V850_OPERAND_SIGNED) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); - } - - /* The first operand is always output without any - special handling. - - For the following arguments: - - If memop && opnum == memop + 1, then we need '[' since - we're about to output the register used in a memory - reference. - - If memop && opnum == memop + 2, then we need ']' since - we just finished the register in a memory reference. We - also need a ',' before this operand. - - Else we just need a comma. - - We may need to output a trailing ']' if the last operand - in an instruction is the register for a memory address. - - The exception (and there's always an exception) is the - "jmp" insn which needs square brackets around it's only - register argument. */ - - if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "["); - else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],"); - else if (memop == 1 && opnum == 1 - && (operand->flags & V850_OPERAND_REG)) - info->fprintf_func (info->stream, "["); - else if (opnum > 1) info->fprintf_func (info->stream, ", "); - - /* extract the flags, ignorng ones which do not effect disassembly output. */ - flag = operand->flags; - flag &= ~ V850_OPERAND_SIGNED; - flag &= ~ V850_OPERAND_RELAX; - flag &= - flag; - - switch (flag) - { - case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break; - case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break; - case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break; - case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break; - default: info->fprintf_func (info->stream, "%d", value); break; - case V850_OPERAND_DISP: - { - bfd_vma addr = value + memaddr; - - /* On the v850 the top 8 bits of an address are used by an overlay manager. - Thus it may happen that when we are looking for a symbol to match - against an address with some of its top bits set, the search fails to - turn up an exact match. In this case we try to find an exact match - against a symbol in the lower address space, and if we find one, we - use that address. We only do this for JARL instructions however, as - we do not want to misinterpret branch instructions. */ - if (operand->bits == 22) - { - if ( ! info->symbol_at_address_func (addr, info) - && ((addr & 0xFF000000) != 0) - && info->symbol_at_address_func (addr & 0x00FFFFFF, info)) - { - addr &= 0x00FFFFFF; - } - } - info->print_address_func (addr, info); - break; - } - - case V850E_PUSH_POP: - { - static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; - static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; - static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 }; - int * regs; - int i; - unsigned long int mask = 0; - int pc = false; - int sr = false; - - - switch (operand->shift) - { - case 0xffe00001: regs = list12_regs; break; - case 0xfff8000f: regs = list18_h_regs; break; - case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */ - default: - /* xgettext:c-format */ - fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift ); - abort(); - } - - for (i = 0; i < 32; i++) - { - if (value & (1 << i)) - { - switch (regs[ i ]) - { - default: mask |= (1 << regs[ i ]); break; - /* xgettext:c-format */ - case 0: fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort(); - case -1: pc = true; break; - case -2: sr = true; break; - } - } - } - - info->fprintf_func (info->stream, "{"); - - if (mask || pc || sr) - { - if (mask) - { - unsigned int bit; - int shown_one = false; - - for (bit = 0; bit < 32; bit++) - if (mask & (1 << bit)) - { - unsigned long int first = bit; - unsigned long int last; - - if (shown_one) - info->fprintf_func (info->stream, ", "); - else - shown_one = true; - - info->fprintf_func (info->stream, v850_reg_names[first]); - - for (bit++; bit < 32; bit++) - if ((mask & (1 << bit)) == 0) - break; - - last = bit; - - if (last > first + 1) - { - info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]); - } - } - } - - if (pc) - info->fprintf_func (info->stream, "%sPC", mask ? ", " : ""); - if (sr) - info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : ""); - } - - info->fprintf_func (info->stream, "}"); - } - break; - - case V850E_IMMEDIATE16: - status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info); - if (status == 0) - { - bytes_read += 2; - value = bfd_getl16 (buffer); - - /* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */ - if ((insn & 0x001fffc0) == 0x00130780) - value <<= 16; - - info->fprintf_func (info->stream, "0x%x", value); - } - else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } - break; - - case V850E_IMMEDIATE32: - status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info); - if (status == 0) - { - bytes_read += 4; - value = bfd_getl32 (buffer); - info->fprintf_func (info->stream, "0x%lx", value); - } - else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } - break; - } - - /* Handle jmp correctly. */ - if (memop == 1 && opnum == 1 - && ((operand->flags & V850_OPERAND_REG) != 0)) - (*info->fprintf_func) (info->stream, "]"); - } - - /* Close any square bracket we left open. */ - if (memop && opnum == memop + 2) - (*info->fprintf_func) (info->stream, "]"); - - /* All done. */ - break; - } - op++; - } - - if (!match) - { - if (short_op) - info->fprintf_func (info->stream, ".short\t0x%04x", insn); - else - info->fprintf_func (info->stream, ".long\t0x%08x", insn); - } - - return bytes_read; -} - -int -print_insn_v850 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info * info; -{ - int status; - bfd_byte buffer[ 4 ]; - unsigned long insn = 0; - - /* First figure out how big the opcode is. */ - - status = info->read_memory_func (memaddr, buffer, 2, info); - if (status == 0) - { - insn = bfd_getl16 (buffer); - - if ( (insn & 0x0600) == 0x0600 - && (insn & 0xffe0) != 0x0620) - { - /* If this is a 4 byte insn, read 4 bytes of stuff. */ - status = info->read_memory_func (memaddr, buffer, 4, info); - - if (status == 0) - insn = bfd_getl32 (buffer); - } - } - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - /* Make sure we tell our caller how many bytes we consumed. */ - return disassemble (memaddr, info, insn); -} diff --git a/contrib/binutils/opcodes/v850-opc.c b/contrib/binutils/opcodes/v850-opc.c deleted file mode 100644 index 874db1b6ee980..0000000000000 --- a/contrib/binutils/opcodes/v850-opc.c +++ /dev/null @@ -1,786 +0,0 @@ -/* Assemble V850 instructions. - Copyright (C) 1996 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "opcode/v850.h" -#include <stdio.h> -#include "opintl.h" - -/* regular opcode */ -#define OP(x) ((x & 0x3f) << 5) -#define OP_MASK OP (0x3f) - -/* conditional branch opcode */ -#define BOP(x) ((0x0b << 7) | (x & 0x0f)) -#define BOP_MASK ((0x0f << 7) | 0x0f) - -/* one-word opcodes */ -#define one(x) ((unsigned int) (x)) - -/* two-word opcodes */ -#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) - - - -/* The functions used to insert and extract complicated operands. */ - -/* Note: There is a conspiracy between these functions and - v850_insert_operand() in gas/config/tc-v850.c. Error messages - containing the string 'out of range' will be ignored unless a - specific command line option is given to GAS. */ - -static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); -static const char * out_of_range = N_ ("displacement value is out of range"); -static const char * not_aligned = N_ ("displacement value is not aligned"); - -static const char * immediate_out_of_range = N_ ("immediate value is out of range"); - -static unsigned long -insert_d9 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0xff || value < -0x100) - { - if ((value % 2) != 0) - * errmsg = _("branch value not in range and to odd offset"); - else - * errmsg = _("branch value out of range"); - } - else if ((value % 2) != 0) - * errmsg = _("branch to odd offset"); - - return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); -} - -static unsigned long -extract_d9 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); - - if ((insn & 0x8000) != 0) - ret -= 0x0200; - - return ret; -} - -static unsigned long -insert_d22 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x1fffff || value < -0x200000) - { - if ((value % 2) != 0) - * errmsg = _("branch value not in range and to an odd offset"); - else - * errmsg = _("branch value out of range"); - } - else if ((value % 2) != 0) - * errmsg = _("branch to odd offset"); - - return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); -} - -static unsigned long -extract_d22 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); - - return (unsigned long) ((ret << 10) >> 10); -} - -static unsigned long -insert_d16_15 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x7fff || value < -0x8000) - { - if ((value % 2) != 0) - * errmsg = _(not_valid); - else - * errmsg = _(out_of_range); - } - else if ((value % 2) != 0) - * errmsg = _(not_aligned); - - return insn | ((value & 0xfffe) << 16); -} - -static unsigned long -extract_d16_15 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = (insn & 0xfffe0000); - - return ret >> 16; -} - -static unsigned long -insert_d8_7 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0xff || value < 0) - { - if ((value % 2) != 0) - * errmsg = _(not_valid); - else - * errmsg = _(out_of_range); - } - else if ((value % 2) != 0) - * errmsg = _(not_aligned); - - value >>= 1; - - return (insn | (value & 0x7f)); -} - -static unsigned long -extract_d8_7 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = (insn & 0x7f); - - return ret << 1; -} - -static unsigned long -insert_d8_6 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0xff || value < 0) - { - if ((value % 4) != 0) - *errmsg = _(not_valid); - else - * errmsg = _(out_of_range); - } - else if ((value % 4) != 0) - * errmsg = _(not_aligned); - - value >>= 1; - - return (insn | (value & 0x7e)); -} - -static unsigned long -extract_d8_6 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = (insn & 0x7e); - - return ret << 1; -} - -static unsigned long -insert_d5_4 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x1f || value < 0) - { - if (value & 1) - * errmsg = _(not_valid); - else - *errmsg = _(out_of_range); - } - else if (value & 1) - * errmsg = _(not_aligned); - - value >>= 1; - - return (insn | (value & 0x0f)); -} - -static unsigned long -extract_d5_4 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = (insn & 0x0f); - - return ret << 1; -} - -static unsigned long -insert_d16_16 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; -{ - if (value > 0x7fff || value < -0x8000) - * errmsg = _(out_of_range); - - return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); -} - -static unsigned long -extract_d16_16 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = insn & 0xfffe0000; - - ret >>= 16; - - ret |= ((insn & 0x20) >> 5); - - return ret; -} - -static unsigned long -insert_i9 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; -{ - if (value > 0xff || value < -0x100) - * errmsg = _(immediate_out_of_range); - - return insn | ((value & 0x1e0) << 13) | (value & 0x1f); -} - -static unsigned long -extract_i9 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = insn & 0x003c0000; - - ret <<= 10; - ret >>= 23; - - ret |= (insn & 0x1f); - - return ret; -} - -static unsigned long -insert_u9 (insn, value, errmsg) - unsigned long insn; - unsigned long value; - const char ** errmsg; -{ - if (value > 0x1ff) - * errmsg = _(immediate_out_of_range); - - return insn | ((value & 0x1e0) << 13) | (value & 0x1f); -} - -static unsigned long -extract_u9 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = insn & 0x003c0000; - - ret >>= 13; - - ret |= (insn & 0x1f); - - return ret; -} - -static unsigned long -insert_spe (insn, value, errmsg) - unsigned long insn; - unsigned long value; - const char ** errmsg; -{ - if (value != 3) - * errmsg = _("invalid register for stack adjustment"); - - return insn & (~ 0x180000); -} - -static unsigned long -extract_spe (insn, invalid) - unsigned long insn; - int * invalid; -{ - return 3; -} - -static unsigned long -insert_i5div (insn, value, errmsg) - unsigned long insn; - unsigned long value; - const char ** errmsg; -{ - if (value > 0x1ff) - { - if (value & 1) - * errmsg = _("immediate value not in range and not even"); - else - * errmsg = _(immediate_out_of_range); - } - else if (value & 1) - * errmsg = _("immediate value must be even"); - - value = 32 - value; - - return insn | ((value & 0x1e) << 17); -} - -static unsigned long -extract_i5div (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = insn & 0x3c0000; - - ret >>= 17; - - ret = 32 - ret; - - return ret; -} - - -/* Warning: code in gas/config/tc-v850.c examines the contents of this array. - If you change any of the values here, be sure to look for side effects in - that code. */ -const struct v850_operand v850_operands[] = -{ -#define UNUSED 0 - { 0, 0, NULL, NULL, 0 }, - -/* The R1 field in a format 1, 6, 7, or 9 insn. */ -#define R1 (UNUSED + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG }, - -/* As above, but register 0 is not allowed. */ -#define R1_NOTR0 (R1 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ -#define R2 (R1_NOTR0 + 1) - { 5, 11, NULL, NULL, V850_OPERAND_REG }, - -/* As above, but register 0 is not allowed. */ -#define R2_NOTR0 (R2 + 1) - { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* The imm5 field in a format 2 insn. */ -#define I5 (R2_NOTR0 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The unsigned imm5 field in a format 2 insn. */ -#define I5U (I5 + 1) - { 5, 0, NULL, NULL, 0 }, - -/* The imm16 field in a format 6 insn. */ -#define I16 (I5U + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The signed disp7 field in a format 4 insn. */ -#define D7 (I16 + 1) - { 7, 0, NULL, NULL, 0}, - -/* The disp16 field in a format 6 insn. */ -#define D16_15 (D7 + 1) - { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, - -/* The 3 bit immediate field in format 8 insn. */ -#define B3 (D16_15 + 1) - { 3, 11, NULL, NULL, 0 }, - -/* The 4 bit condition code in a setf instruction */ -#define CCCC (B3 + 1) - { 4, 0, NULL, NULL, V850_OPERAND_CC }, - -/* The unsigned DISP8 field in a format 4 insn. */ -#define D8_7 (CCCC + 1) - { 7, 0, insert_d8_7, extract_d8_7, 0 }, - -/* The unsigned DISP8 field in a format 4 insn. */ -#define D8_6 (D8_7 + 1) - { 6, 1, insert_d8_6, extract_d8_6, 0 }, - -/* System register operands. */ -#define SR1 (D8_6 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SRG }, - -/* EP Register. */ -#define EP (SR1 + 1) - { 0, 0, NULL, NULL, V850_OPERAND_EP }, - -/* The imm16 field (unsigned) in a format 6 insn. */ -#define I16U (EP + 1) - { 16, 16, NULL, NULL, 0}, - -/* The R2 field as a system register. */ -#define SR2 (I16U + 1) - { 5, 11, NULL, NULL, V850_OPERAND_SRG }, - -/* The disp16 field in a format 8 insn. */ -#define D16 (SR2 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The DISP9 field in a format 3 insn, relaxable. */ -#define D9_RELAX (D16 + 1) - { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, - -/* The DISP22 field in a format 4 insn, relaxable. - This _must_ follow D9_RELAX; the assembler assumes that the longer - version immediately follows the shorter version for relaxing. */ -#define D22 (D9_RELAX + 1) - { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, - -/* The signed disp4 field in a format 4 insn. */ -#define D4 (D22 + 1) - { 4, 0, NULL, NULL, 0}, - -/* The unsigned disp5 field in a format 4 insn. */ -#define D5_4 (D4 + 1) - { 4, 0, insert_d5_4, extract_d5_4, 0 }, - -/* The disp16 field in an format 7 unsigned byte load insn. */ -#define D16_16 (D5_4 + 1) - { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, - -/* Third register in conditional moves. */ -#define R3 (D16_16 + 1) - { 5, 27, NULL, NULL, V850_OPERAND_REG }, - -/* Condition code in conditional moves. */ -#define MOVCC (R3 + 1) - { 4, 17, NULL, NULL, V850_OPERAND_CC }, - -/* The imm9 field in a multiply word. */ -#define I9 (MOVCC + 1) - { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, - -/* The unsigned imm9 field in a multiply word. */ -#define U9 (I9 + 1) - { 9, 0, insert_u9, extract_u9, 0 }, - -/* A list of registers in a prepare/dispose instruction. */ -#define LIST12 (U9 + 1) - { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, - -/* The IMM6 field in a call instruction. */ -#define I6 (LIST12 + 1) - { 6, 0, NULL, NULL, 0 }, - -/* The 16 bit immediate following a 32 bit instruction. */ -#define IMM16 (I6 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, - -/* The 32 bit immediate following a 32 bit instruction. */ -#define IMM32 (IMM16 + 1) - { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, - -/* The imm5 field in a push/pop instruction. */ -#define IMM5 (IMM32 + 1) - { 5, 1, NULL, NULL, 0 }, - -/* Reg2 in dispose instruction. */ -#define R2DISPOSE (IMM5 + 1) - { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* Stack pointer in prepare instruction. */ -#define SP (R2DISPOSE + 1) - { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, - -/* The IMM5 field in a divide N step instruction. */ -#define I5DIV (SP + 1) - { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, - - /* The list of registers in a PUSHMH/POPMH instruction. */ -#define LIST18_H (I5DIV + 1) - { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, - - /* The list of registers in a PUSHML/POPML instruction. */ -#define LIST18_L (LIST18_H + 1) - { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ -} ; - - -/* reg-reg instruction format (Format I) */ -#define IF1 {R1, R2} - -/* imm-reg instruction format (Format II) */ -#define IF2 {I5, R2} - -/* conditional branch instruction format (Format III) */ -#define IF3 {D9_RELAX} - -/* 3 operand instruction (Format VI) */ -#define IF6 {I16, R1, R2} - -/* 3 operand instruction (Format VI) */ -#define IF6U {I16U, R1, R2} - - - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - OPERANDS is the list of operands. - MEMOP specifies which operand (if any) is a memory operand. - PROCESSORS specifies which CPU(s) support the opcode. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. - - The table is also sorted by name. This is used by the assembler. - When parsing an instruction the assembler finds the first occurance - of the name of the instruciton in this table and then attempts to - match the instruction's arguments with description of the operands - associated with the entry it has just found in this table. If the - match fails the assembler looks at the next entry in this table. - If that entry has the same name as the previous entry, then it - tries to match the instruction against that entry and so on. This - is how the assembler copes with multiple, different formats of the - same instruction. */ - -const struct v850_opcode v850_opcodes[] = -{ -{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, - -{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, - -/* load/store instructions */ -{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, -{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, - -{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, -{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, - -{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1, PROCESSOR_V850EA }, -{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, -{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, - -{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1, PROCESSOR_V850EA }, -{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, -{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, -{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, -{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, -{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, -{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, - -{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, -{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, -{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, -{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, -{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, -{ "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, -{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, - -{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, -{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, -{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, - -/* byte swap/extend instructions */ -{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, - -/* jump table instructions */ -{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, -{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, -{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, - -/* arithmetic operation instructions */ -{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, -{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, - -{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, - -{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - -{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, - -{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, -{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, -{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, -{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, - -/* saturated operation instructions */ -{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - -/* logical operation instructions */ -{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, - -/* branch instructions */ - /* signed integer */ -{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ -{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ -{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ -{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - -/* Branch macros. - - We use the short form in the opcode/mask fields. The assembler - will twiddle bits as necessary if the long form is needed. */ - - /* signed integer */ -{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ -{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ -{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ -{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - -{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, -{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, - -/* bit manipulation instructions */ -{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, - -/* special instructions */ -{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, -{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, -{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, -{ 0, 0, 0, {0}, 0, 0 }, - -} ; - -const int v850_num_opcodes = - sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); - diff --git a/contrib/binutils/opcodes/z8k-dis.c b/contrib/binutils/opcodes/z8k-dis.c deleted file mode 100644 index 590f9d30bf0a8..0000000000000 --- a/contrib/binutils/opcodes/z8k-dis.c +++ /dev/null @@ -1,573 +0,0 @@ -/* Disassemble z8000 code. - Copyright 1992, 1993, 1995, 1998 Free Software Foundation, Inc. - -This file is part of GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" - -#define DEFINE_TABLE -#include "z8k-opc.h" - - -#include <setjmp.h> - - -typedef struct -{ - /* These are all indexed by nibble number (i.e only every other entry - of bytes is used, and every 4th entry of words). */ - unsigned char nibbles[24]; - unsigned char bytes[24]; - unsigned short words[24]; - - /* Nibble number of first word not yet fetched. */ - int max_fetched; - bfd_vma insn_start; - jmp_buf bailout; - - long tabl_index; - char instr_asmsrc[80]; - unsigned long arg_reg[0x0f]; - unsigned long immediate; - unsigned long displacement; - unsigned long address; - unsigned long cond_code; - unsigned long ctrl_code; - unsigned long flags; - unsigned long interrupts; -} -instr_data_s; - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, nibble) \ - ((nibble) < ((instr_data_s *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (nibble))) - -static int -fetch_data (info, nibble) - struct disassemble_info *info; - int nibble; -{ - unsigned char mybuf[20]; - int status; - instr_data_s *priv = (instr_data_s *)info->private_data; - - if ((nibble % 4) != 0) - abort (); - - status = (*info->read_memory_func) (priv->insn_start, - (bfd_byte *) mybuf, - nibble / 2, - info); - if (status != 0) - { - (*info->memory_error_func) (status, priv->insn_start, info); - longjmp (priv->bailout, 1); - } - - { - int i; - unsigned char *p = mybuf ; - - for (i = 0; i < nibble;) - { - priv->words[i] = (p[0] << 8) | p[1]; - - priv->bytes[i] = *p; - priv->nibbles[i++] = *p >> 4; - priv->nibbles[i++] = *p &0xf; - - ++p; - priv->bytes[i] = *p; - priv->nibbles[i++] = *p >> 4; - priv->nibbles[i++] = *p & 0xf; - - ++p; - } - } - priv->max_fetched = nibble; - return 1; -} - -static char *codes[16] = -{ - "f", - "lt", - "le", - "ule", - "ov/pe", - "mi", - "eq", - "c/ult", - "t", - "ge", - "gt", - "ugt", - "nov/po", - "pl", - "ne", - "nc/uge" -}; - -int z8k_lookup_instr PARAMS ((unsigned char*, disassemble_info *)); -static void output_instr - PARAMS ((instr_data_s *, unsigned long, disassemble_info *)); -static void unpack_instr PARAMS ((instr_data_s *, int, disassemble_info *)); -static void unparse_instr PARAMS ((instr_data_s *)); - -static int -print_insn_z8k (addr, info, is_segmented) - bfd_vma addr; - disassemble_info *info; - int is_segmented; -{ - instr_data_s instr_data; - - info->private_data = (PTR) &instr_data; - instr_data.max_fetched = 0; - instr_data.insn_start = addr; - if (setjmp (instr_data.bailout) != 0) - /* Error return. */ - return -1; - - instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info); - if (instr_data.tabl_index > 0) - { - unpack_instr (&instr_data, is_segmented, info); - unparse_instr (&instr_data); - output_instr (&instr_data, addr, info); - return z8k_table[instr_data.tabl_index].length; - } - else - { - FETCH_DATA (info, 4); - (*info->fprintf_func) (info->stream, ".word %02x%02x", - instr_data.bytes[0], instr_data.bytes[2]); - return 2; - } -} - -int -print_insn_z8001 (addr, info) - bfd_vma addr; - disassemble_info *info; -{ - return print_insn_z8k (addr, info, 1); -} - -int -print_insn_z8002 (addr, info) - bfd_vma addr; - disassemble_info *info; -{ - return print_insn_z8k (addr, info, 0); -} - -int -z8k_lookup_instr (nibbles, info) - unsigned char *nibbles; - disassemble_info *info; -{ - - int nibl_index, tabl_index; - int nibl_matched; - unsigned short instr_nibl; - unsigned short tabl_datum, datum_class, datum_value; - - nibl_matched = 0; - tabl_index = 0; - while (!nibl_matched && z8k_table[tabl_index].name) - { - nibl_matched = 1; - for (nibl_index = 0; nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched; nibl_index++) - { - if ((nibl_index % 4) == 0) - /* Fetch one word at a time. */ - FETCH_DATA (info, nibl_index + 4); - instr_nibl = nibbles[nibl_index]; - - tabl_datum = z8k_table[tabl_index].byte_info[nibl_index]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = ~CLASS_MASK & tabl_datum; - - switch (datum_class) - { - case CLASS_BIT: - if (datum_value != instr_nibl) - nibl_matched = 0; - break; - case CLASS_00II: - if (!((~instr_nibl) & 0x4)) - nibl_matched = 0; - break; - case CLASS_01II: - if (!(instr_nibl & 0x4)) - nibl_matched = 0; - break; - case CLASS_0CCC: - if (!((~instr_nibl) & 0x8)) - nibl_matched = 0; - break; - case CLASS_1CCC: - if (!(instr_nibl & 0x8)) - nibl_matched = 0; - break; - case CLASS_0DISP7: - if (!((~instr_nibl) & 0x8)) - nibl_matched = 0; - nibl_index += 1; - break; - case CLASS_1DISP7: - if (!(instr_nibl & 0x8)) - nibl_matched = 0; - nibl_index += 1; - break; - case CLASS_REGN0: - if (instr_nibl == 0) - nibl_matched = 0; - break; - case CLASS_BIT_1OR2: - if ((instr_nibl | 0x2) != (datum_value | 0x2)) - nibl_matched = 0; - break; - default: - break; - } - } - if (nibl_matched) - { - return tabl_index; - } - - tabl_index++; - } - return -1; - -} - -static void -output_instr (instr_data, addr, info) - instr_data_s *instr_data; - unsigned long addr; - disassemble_info *info; -{ - int loop, loop_limit; - char tmp_str[20]; - char out_str[100]; - - strcpy (out_str, "\t"); - - loop_limit = z8k_table[instr_data->tabl_index].length * 2; - FETCH_DATA (info, loop_limit); - for (loop = 0; loop < loop_limit; loop++) - { - sprintf (tmp_str, "%x", instr_data->nibbles[loop]); - strcat (out_str, tmp_str); - } - - while (loop++ < 8) - { - strcat (out_str, " "); - } - - strcat (out_str, instr_data->instr_asmsrc); - - (*info->fprintf_func) (info->stream, "%s", out_str); -} - -static void -unpack_instr (instr_data, is_segmented, info) - instr_data_s *instr_data; - int is_segmented; - disassemble_info *info; -{ - int nibl_count, loop; - unsigned short instr_nibl, instr_byte, instr_word; - long instr_long; - unsigned short tabl_datum, datum_class, datum_value; - - nibl_count = 0; - loop = 0; - while (z8k_table[instr_data->tabl_index].byte_info[loop] != 0) - { - FETCH_DATA (info, nibl_count + 4 - (nibl_count % 4)); - instr_nibl = instr_data->nibbles[nibl_count]; - instr_byte = instr_data->bytes[nibl_count]; - instr_word = instr_data->words[nibl_count]; - - tabl_datum = z8k_table[instr_data->tabl_index].byte_info[loop]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = tabl_datum & ~CLASS_MASK; - - switch (datum_class) - { - case CLASS_X: - instr_data->address = instr_nibl; - break; - case CLASS_BA: - instr_data->displacement = instr_nibl; - break; - case CLASS_BX: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_DISP: - switch (datum_value) - { - case ARG_DISP16: - instr_data->displacement = instr_word; - nibl_count += 3; - break; - case ARG_DISP12: - instr_data->displacement = instr_word & 0x0fff; - nibl_count += 2; - break; - default: - break; - } - break; - case CLASS_IMM: - switch (datum_value) - { - case ARG_IMM4: - instr_data->immediate = instr_nibl; - break; - case ARG_NIM8: - instr_data->immediate = (-instr_byte); - nibl_count += 1; - break; - case ARG_IMM8: - instr_data->immediate = instr_byte; - nibl_count += 1; - break; - case ARG_IMM16: - instr_data->immediate = instr_word; - nibl_count += 3; - break; - case ARG_IMM32: - FETCH_DATA (info, nibl_count + 8); - instr_long = (instr_data->words[nibl_count] << 16) - | (instr_data->words[nibl_count + 4]); - instr_data->immediate = instr_long; - nibl_count += 7; - break; - case ARG_IMMN: - instr_data->immediate = instr_nibl - 1; - break; - case ARG_IMM4M1: - instr_data->immediate = instr_nibl + 1; - break; - case ARG_IMM_1: - instr_data->immediate = 1; - break; - case ARG_IMM_2: - instr_data->immediate = 2; - break; - case ARG_IMM2: - instr_data->immediate = instr_nibl & 0x3; - break; - default: - break; - } - break; - case CLASS_CC: - instr_data->cond_code = instr_nibl; - break; - case CLASS_CTRL: - instr_data->ctrl_code = instr_nibl; - break; - case CLASS_DA: - case CLASS_ADDRESS: - if (is_segmented) - { - if (instr_nibl & 0x8) - { - FETCH_DATA (info, nibl_count + 8); - instr_long = (instr_data->words[nibl_count] << 16) - | (instr_data->words[nibl_count + 4]); - instr_data->address = ((instr_word & 0x7f00) << 8) + - (instr_long & 0xffff); - nibl_count += 7; - } - else - { - instr_data->address = ((instr_word & 0x7f00) << 8) + - (instr_word & 0x00ff); - nibl_count += 3; - } - } - else - { - instr_data->address = instr_word; - nibl_count += 3; - } - break; - case CLASS_0CCC: - instr_data->cond_code = instr_nibl & 0x7; - break; - case CLASS_1CCC: - instr_data->cond_code = instr_nibl & 0x7; - break; - case CLASS_0DISP7: - instr_data->displacement = instr_byte & 0x7f; - nibl_count += 1; - break; - case CLASS_1DISP7: - instr_data->displacement = instr_byte & 0x7f; - nibl_count += 1; - break; - case CLASS_01II: - instr_data->interrupts = instr_nibl & 0x3; - break; - case CLASS_00II: - instr_data->interrupts = instr_nibl & 0x3; - break; - case CLASS_BIT: - /* do nothing */ - break; - case CLASS_IR: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_FLAGS: - instr_data->flags = instr_nibl; - break; - case CLASS_REG: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_BYTE: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_WORD: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_QUAD: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_LONG: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REGN0: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - default: - break; - } - - loop += 1; - nibl_count += 1; - } -} - -static void -unparse_instr (instr_data) - instr_data_s *instr_data; -{ - unsigned short tabl_datum, datum_class, datum_value; - int loop, loop_limit; - char out_str[80], tmp_str[25]; - - sprintf (out_str, "\t%s\t", z8k_table[instr_data->tabl_index].name); - - loop_limit = z8k_table[instr_data->tabl_index].noperands; - for (loop = 0; loop < loop_limit; loop++) - { - if (loop) - strcat (out_str, ","); - - tabl_datum = z8k_table[instr_data->tabl_index].arg_info[loop]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = tabl_datum & ~CLASS_MASK; - - switch (datum_class) - { - case CLASS_X: - sprintf (tmp_str, "0x%0lx(R%ld)", instr_data->address, - instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_BA: - sprintf (tmp_str, "r%ld(#%lx)", instr_data->arg_reg[datum_value], - instr_data->immediate); - strcat (out_str, tmp_str); - break; - case CLASS_BX: - sprintf (tmp_str, "r%ld(R%ld)", instr_data->arg_reg[datum_value], - instr_data->arg_reg[ARG_RX]); - strcat (out_str, tmp_str); - break; - case CLASS_DISP: - sprintf (tmp_str, "#0x%0lx", instr_data->displacement); - strcat (out_str, tmp_str); - break; - case CLASS_IMM: - sprintf (tmp_str, "#0x%0lx", instr_data->immediate); - strcat (out_str, tmp_str); - break; - case CLASS_CC: - sprintf (tmp_str, "%s", codes[instr_data->cond_code]); - strcat (out_str, tmp_str); - break; - case CLASS_CTRL: - sprintf (tmp_str, "0x%0lx", instr_data->ctrl_code); - strcat (out_str, tmp_str); - break; - case CLASS_DA: - case CLASS_ADDRESS: - sprintf (tmp_str, "#0x%0lx", instr_data->address); - strcat (out_str, tmp_str); - break; - case CLASS_IR: - sprintf (tmp_str, "@R%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_FLAGS: - sprintf (tmp_str, "0x%0lx", instr_data->flags); - strcat (out_str, tmp_str); - break; - case CLASS_REG_BYTE: - if (instr_data->arg_reg[datum_value] >= 0x8) - { - sprintf (tmp_str, "rl%ld", - instr_data->arg_reg[datum_value] - 0x8); - } - else - { - sprintf (tmp_str, "rh%ld", instr_data->arg_reg[datum_value]); - } - strcat (out_str, tmp_str); - break; - case CLASS_REG_WORD: - sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_QUAD: - sprintf (tmp_str, "rq%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_LONG: - sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - default: - break; - } - } - - strcpy (instr_data->instr_asmsrc, out_str); -} diff --git a/contrib/binutils/opcodes/z8k-opc.h b/contrib/binutils/opcodes/z8k-opc.h deleted file mode 100644 index 379a3a3c64771..0000000000000 --- a/contrib/binutils/opcodes/z8k-opc.h +++ /dev/null @@ -1,4438 +0,0 @@ - /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */ -#define ARG_MASK 0x0f -#define ARG_SRC 0x01 -#define ARG_DST 0x02 -#define ARG_RS 0x01 -#define ARG_RD 0x02 -#define ARG_RA 0x03 -#define ARG_RB 0x04 -#define ARG_RR 0x05 -#define ARG_RX 0x06 -#define ARG_IMM4 0x01 -#define ARG_IMM8 0x02 -#define ARG_IMM16 0x03 -#define ARG_IMM32 0x04 -#define ARG_IMMN 0x05 -#define ARG_IMMNMINUS1 0x05 -#define ARG_IMM_1 0x06 -#define ARG_IMM_2 0x07 -#define ARG_DISP16 0x08 -#define ARG_NIM8 0x09 -#define ARG_IMM2 0x0a -#define ARG_IMM1OR2 0x0b -#define ARG_DISP12 0x0b -#define ARG_DISP8 0x0c -#define ARG_IMM4M1 0x0d -#define CLASS_MASK 0x1fff0 -#define CLASS_X 0x10 -#define CLASS_BA 0x20 -#define CLASS_DA 0x30 -#define CLASS_BX 0x40 -#define CLASS_DISP 0x50 -#define CLASS_IMM 0x60 -#define CLASS_CC 0x70 -#define CLASS_CTRL 0x80 -#define CLASS_ADDRESS 0xd0 -#define CLASS_0CCC 0xe0 -#define CLASS_1CCC 0xf0 -#define CLASS_0DISP7 0x100 -#define CLASS_1DISP7 0x200 -#define CLASS_01II 0x300 -#define CLASS_00II 0x400 -#define CLASS_BIT 0x500 -#define CLASS_FLAGS 0x600 -#define CLASS_IR 0x700 -#define CLASS_DISP8 0x800 -#define CLASS_BIT_1OR2 0x900 -#define CLASS_REG 0x7000 -#define CLASS_REG_BYTE 0x2000 -#define CLASS_REG_WORD 0x3000 -#define CLASS_REG_QUAD 0x4000 -#define CLASS_REG_LONG 0x5000 -#define CLASS_REGN0 0x8000 -#define CLASS_PR 0x10000 -#define OPC_adc 0 -#define OPC_adcb 1 -#define OPC_add 2 -#define OPC_addb 3 -#define OPC_addl 4 -#define OPC_and 5 -#define OPC_andb 6 -#define OPC_bit 7 -#define OPC_bitb 8 -#define OPC_call 9 -#define OPC_calr 10 -#define OPC_clr 11 -#define OPC_clrb 12 -#define OPC_com 13 -#define OPC_comb 14 -#define OPC_comflg 15 -#define OPC_cp 16 -#define OPC_cpb 17 -#define OPC_cpd 18 -#define OPC_cpdb 19 -#define OPC_cpdr 20 -#define OPC_cpdrb 21 -#define OPC_cpi 22 -#define OPC_cpib 23 -#define OPC_cpir 24 -#define OPC_cpirb 25 -#define OPC_cpl 26 -#define OPC_cpsd 27 -#define OPC_cpsdb 28 -#define OPC_cpsdr 29 -#define OPC_cpsdrb 30 -#define OPC_cpsi 31 -#define OPC_cpsib 32 -#define OPC_cpsir 33 -#define OPC_cpsirb 34 -#define OPC_dab 35 -#define OPC_dbjnz 36 -#define OPC_dec 37 -#define OPC_decb 38 -#define OPC_di 39 -#define OPC_div 40 -#define OPC_divl 41 -#define OPC_djnz 42 -#define OPC_ei 43 -#define OPC_ex 44 -#define OPC_exb 45 -#define OPC_exts 46 -#define OPC_extsb 47 -#define OPC_extsl 48 -#define OPC_halt 49 -#define OPC_in 50 -#define OPC_inb 51 -#define OPC_inc 52 -#define OPC_incb 53 -#define OPC_ind 54 -#define OPC_indb 55 -#define OPC_inib 56 -#define OPC_inibr 57 -#define OPC_iret 58 -#define OPC_jp 59 -#define OPC_jr 60 -#define OPC_ld 61 -#define OPC_lda 62 -#define OPC_ldar 63 -#define OPC_ldb 64 -#define OPC_ldctl 65 -#define OPC_ldir 66 -#define OPC_ldirb 67 -#define OPC_ldk 68 -#define OPC_ldl 69 -#define OPC_ldm 70 -#define OPC_ldps 71 -#define OPC_ldr 72 -#define OPC_ldrb 73 -#define OPC_ldrl 74 -#define OPC_mbit 75 -#define OPC_mreq 76 -#define OPC_mres 77 -#define OPC_mset 78 -#define OPC_mult 79 -#define OPC_multl 80 -#define OPC_neg 81 -#define OPC_negb 82 -#define OPC_nop 83 -#define OPC_or 84 -#define OPC_orb 85 -#define OPC_out 86 -#define OPC_outb 87 -#define OPC_outd 88 -#define OPC_outdb 89 -#define OPC_outib 90 -#define OPC_outibr 91 -#define OPC_pop 92 -#define OPC_popl 93 -#define OPC_push 94 -#define OPC_pushl 95 -#define OPC_res 96 -#define OPC_resb 97 -#define OPC_resflg 98 -#define OPC_ret 99 -#define OPC_rl 100 -#define OPC_rlb 101 -#define OPC_rlc 102 -#define OPC_rlcb 103 -#define OPC_rldb 104 -#define OPC_rr 105 -#define OPC_rrb 106 -#define OPC_rrc 107 -#define OPC_rrcb 108 -#define OPC_rrdb 109 -#define OPC_sbc 110 -#define OPC_sbcb 111 -#define OPC_sda 112 -#define OPC_sdab 113 -#define OPC_sdal 114 -#define OPC_sdl 115 -#define OPC_sdlb 116 -#define OPC_sdll 117 -#define OPC_set 118 -#define OPC_setb 119 -#define OPC_setflg 120 -#define OPC_sinb 121 -#define OPC_sind 122 -#define OPC_sindb 123 -#define OPC_sinib 124 -#define OPC_sinibr 125 -#define OPC_sla 126 -#define OPC_slab 127 -#define OPC_slal 128 -#define OPC_sll 129 -#define OPC_sllb 130 -#define OPC_slll 131 -#define OPC_sout 132 -#define OPC_soutb 133 -#define OPC_soutd 134 -#define OPC_soutdb 135 -#define OPC_soutib 136 -#define OPC_soutibr 137 -#define OPC_sra 138 -#define OPC_srab 139 -#define OPC_sral 140 -#define OPC_srl 141 -#define OPC_srlb 142 -#define OPC_srll 143 -#define OPC_sub 144 -#define OPC_subb 145 -#define OPC_subl 146 -#define OPC_tcc 147 -#define OPC_tccb 148 -#define OPC_test 149 -#define OPC_testb 150 -#define OPC_testl 151 -#define OPC_trdb 152 -#define OPC_trdrb 153 -#define OPC_trib 154 -#define OPC_trirb 155 -#define OPC_trtdrb 156 -#define OPC_trtib 157 -#define OPC_trtirb 158 -#define OPC_trtdb 159 -#define OPC_tset 160 -#define OPC_tsetb 161 -#define OPC_xor 162 -#define OPC_xorb 163 -#define OPC_ldd 164 -#define OPC_lddb 165 -#define OPC_lddr 166 -#define OPC_lddrb 167 -#define OPC_ldi 168 -#define OPC_ldib 169 -#define OPC_sc 170 -#define OPC_bpt 171 -#define OPC_ext0e 172 -#define OPC_ext0f 172 -#define OPC_ext8e 172 -#define OPC_ext8f 172 -#define OPC_rsvd36 172 -#define OPC_rsvd38 172 -#define OPC_rsvd78 172 -#define OPC_rsvd7e 172 -#define OPC_rsvd9d 172 -#define OPC_rsvd9f 172 -#define OPC_rsvdb9 172 -#define OPC_rsvdbf 172 -#define OPC_outi 173 -typedef struct { -#ifdef NICENAMES -char *nicename; -int type; -int cycles; -int flags; -#endif -char *name; -unsigned char opcode; -void (*func)(); -unsigned int arg_info[4]; -unsigned int byte_info[10]; -int noperands; -int length; -int idx; -} opcode_entry_type; -#ifdef DEFINE_TABLE -opcode_entry_type z8k_table[] = { - - -/* 1011 0101 ssss dddd *** adc rd,rs */ -{ -#ifdef NICENAMES -"adc rd,rs",16,5, -0x3c, -#endif -"adc",OPC_adc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,0}, - - -/* 1011 0100 ssss dddd *** adcb rbd,rbs */ -{ -#ifdef NICENAMES -"adcb rbd,rbs",8,5, -0x3f, -#endif -"adcb",OPC_adcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,1}, - - -/* 0000 0001 ssN0 dddd *** add rd,@rs */ -{ -#ifdef NICENAMES -"add rd,@rs",16,7, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2}, - - -/* 0100 0001 0000 dddd address_src *** add rd,address_src */ -{ -#ifdef NICENAMES -"add rd,address_src",16,9, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,3}, - - -/* 0100 0001 ssN0 dddd address_src *** add rd,address_src(rs) */ -{ -#ifdef NICENAMES -"add rd,address_src(rs)",16,10, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,4}, - - -/* 0000 0001 0000 dddd imm16 *** add rd,imm16 */ -{ -#ifdef NICENAMES -"add rd,imm16",16,7, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,5}, - - -/* 1000 0001 ssss dddd *** add rd,rs */ -{ -#ifdef NICENAMES -"add rd,rs",16,4, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6}, - - -/* 0000 0000 ssN0 dddd *** addb rbd,@rs */ -{ -#ifdef NICENAMES -"addb rbd,@rs",8,7, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,7}, - - -/* 0100 0000 0000 dddd address_src *** addb rbd,address_src */ -{ -#ifdef NICENAMES -"addb rbd,address_src",8,9, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,8}, - - -/* 0100 0000 ssN0 dddd address_src *** addb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"addb rbd,address_src(rs)",8,10, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,9}, - - -/* 0000 0000 0000 dddd imm8 imm8 *** addb rbd,imm8 */ -{ -#ifdef NICENAMES -"addb rbd,imm8",8,7, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,10}, - - -/* 1000 0000 ssss dddd *** addb rbd,rbs */ -{ -#ifdef NICENAMES -"addb rbd,rbs",8,4, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,11}, - - -/* 0001 0110 ssN0 dddd *** addl rrd,@rs */ -{ -#ifdef NICENAMES -"addl rrd,@rs",32,14, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,12}, - - -/* 0101 0110 0000 dddd address_src *** addl rrd,address_src */ -{ -#ifdef NICENAMES -"addl rrd,address_src",32,15, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,13}, - - -/* 0101 0110 ssN0 dddd address_src *** addl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"addl rrd,address_src(rs)",32,16, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,14}, - - -/* 0001 0110 0000 dddd imm32 *** addl rrd,imm32 */ -{ -#ifdef NICENAMES -"addl rrd,imm32",32,14, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,15}, - - -/* 1001 0110 ssss dddd *** addl rrd,rrs */ -{ -#ifdef NICENAMES -"addl rrd,rrs",32,8, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,16}, - - -/* 0000 0111 ssN0 dddd *** and rd,@rs */ -{ -#ifdef NICENAMES -"and rd,@rs",16,7, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17}, - - -/* 0100 0111 0000 dddd address_src *** and rd,address_src */ -{ -#ifdef NICENAMES -"and rd,address_src",16,9, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, - - -/* 0100 0111 ssN0 dddd address_src *** and rd,address_src(rs) */ -{ -#ifdef NICENAMES -"and rd,address_src(rs)",16,10, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, - - -/* 0000 0111 0000 dddd imm16 *** and rd,imm16 */ -{ -#ifdef NICENAMES -"and rd,imm16",16,7, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,20}, - - -/* 1000 0111 ssss dddd *** and rd,rs */ -{ -#ifdef NICENAMES -"and rd,rs",16,4, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,21}, - - -/* 0000 0110 ssN0 dddd *** andb rbd,@rs */ -{ -#ifdef NICENAMES -"andb rbd,@rs",8,7, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,22}, - - -/* 0100 0110 0000 dddd address_src *** andb rbd,address_src */ -{ -#ifdef NICENAMES -"andb rbd,address_src",8,9, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,23}, - - -/* 0100 0110 ssN0 dddd address_src *** andb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"andb rbd,address_src(rs)",8,10, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,24}, - - -/* 0000 0110 0000 dddd imm8 imm8 *** andb rbd,imm8 */ -{ -#ifdef NICENAMES -"andb rbd,imm8",8,7, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,25}, - - -/* 1000 0110 ssss dddd *** andb rbd,rbs */ -{ -#ifdef NICENAMES -"andb rbd,rbs",8,4, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,26}, - - -/* 0010 0111 ddN0 imm4 *** bit @rd,imm4 */ -{ -#ifdef NICENAMES -"bit @rd,imm4",16,8, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,27}, - - -/* 0110 0111 ddN0 imm4 address_dst *** bit address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"bit address_dst(rd),imm4",16,11, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,28}, - - -/* 0110 0111 0000 imm4 address_dst *** bit address_dst,imm4 */ -{ -#ifdef NICENAMES -"bit address_dst,imm4",16,10, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+7,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,29}, - - -/* 1010 0111 dddd imm4 *** bit rd,imm4 */ -{ -#ifdef NICENAMES -"bit rd,imm4",16,4, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+7,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,30}, - - -/* 0010 0111 0000 ssss 0000 dddd 0000 0000 *** bit rd,rs */ -{ -#ifdef NICENAMES -"bit rd,rs",16,10, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,31}, - - -/* 0010 0110 ddN0 imm4 *** bitb @rd,imm4 */ -{ -#ifdef NICENAMES -"bitb @rd,imm4",8,8, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,32}, - - -/* 0110 0110 ddN0 imm4 address_dst *** bitb address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"bitb address_dst(rd),imm4",8,11, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,33}, - - -/* 0110 0110 0000 imm4 address_dst *** bitb address_dst,imm4 */ -{ -#ifdef NICENAMES -"bitb address_dst,imm4",8,10, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+6,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,34}, - - -/* 1010 0110 dddd imm4 *** bitb rbd,imm4 */ -{ -#ifdef NICENAMES -"bitb rbd,imm4",8,4, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+6,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,35}, - - -/* 0010 0110 0000 ssss 0000 dddd 0000 0000 *** bitb rbd,rs */ -{ -#ifdef NICENAMES -"bitb rbd,rs",8,10, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,36}, - - -/* 0011 0110 0000 0000 *** bpt */ -{ -#ifdef NICENAMES -"bpt",8,2, -0x00, -#endif -"bpt",OPC_bpt,0,{0}, - {CLASS_BIT+3,CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,37}, - - -/* 0001 1111 ddN0 0000 *** call @rd */ -{ -#ifdef NICENAMES -"call @rd",32,10, -0x00, -#endif -"call",OPC_call,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,38}, - - -/* 0101 1111 0000 0000 address_dst *** call address_dst */ -{ -#ifdef NICENAMES -"call address_dst",32,12, -0x00, -#endif -"call",OPC_call,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,39}, - - -/* 0101 1111 ddN0 0000 address_dst *** call address_dst(rd) */ -{ -#ifdef NICENAMES -"call address_dst(rd)",32,13, -0x00, -#endif -"call",OPC_call,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,40}, - - -/* 1101 disp12 *** calr disp12 */ -{ -#ifdef NICENAMES -"calr disp12",16,10, -0x00, -#endif -"calr",OPC_calr,0,{CLASS_DISP,}, - {CLASS_BIT+0xd,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,41}, - - -/* 0000 1101 ddN0 1000 *** clr @rd */ -{ -#ifdef NICENAMES -"clr @rd",16,8, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,42}, - - -/* 0100 1101 0000 1000 address_dst *** clr address_dst */ -{ -#ifdef NICENAMES -"clr address_dst",16,11, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,43}, - - -/* 0100 1101 ddN0 1000 address_dst *** clr address_dst(rd) */ -{ -#ifdef NICENAMES -"clr address_dst(rd)",16,12, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,44}, - - -/* 1000 1101 dddd 1000 *** clr rd */ -{ -#ifdef NICENAMES -"clr rd",16,7, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,45}, - - -/* 0000 1100 ddN0 1000 *** clrb @rd */ -{ -#ifdef NICENAMES -"clrb @rd",8,8, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,46}, - - -/* 0100 1100 0000 1000 address_dst *** clrb address_dst */ -{ -#ifdef NICENAMES -"clrb address_dst",8,11, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,47}, - - -/* 0100 1100 ddN0 1000 address_dst *** clrb address_dst(rd) */ -{ -#ifdef NICENAMES -"clrb address_dst(rd)",8,12, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,48}, - - -/* 1000 1100 dddd 1000 *** clrb rbd */ -{ -#ifdef NICENAMES -"clrb rbd",8,7, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,49}, - - -/* 0000 1101 ddN0 0000 *** com @rd */ -{ -#ifdef NICENAMES -"com @rd",16,12, -0x18, -#endif -"com",OPC_com,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,50}, - - -/* 0100 1101 0000 0000 address_dst *** com address_dst */ -{ -#ifdef NICENAMES -"com address_dst",16,15, -0x18, -#endif -"com",OPC_com,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,51}, - - -/* 0100 1101 ddN0 0000 address_dst *** com address_dst(rd) */ -{ -#ifdef NICENAMES -"com address_dst(rd)",16,16, -0x18, -#endif -"com",OPC_com,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,52}, - - -/* 1000 1101 dddd 0000 *** com rd */ -{ -#ifdef NICENAMES -"com rd",16,7, -0x18, -#endif -"com",OPC_com,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53}, - - -/* 0000 1100 ddN0 0000 *** comb @rd */ -{ -#ifdef NICENAMES -"comb @rd",8,12, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,54}, - - -/* 0100 1100 0000 0000 address_dst *** comb address_dst */ -{ -#ifdef NICENAMES -"comb address_dst",8,15, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,55}, - - -/* 0100 1100 ddN0 0000 address_dst *** comb address_dst(rd) */ -{ -#ifdef NICENAMES -"comb address_dst(rd)",8,16, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,56}, - - -/* 1000 1100 dddd 0000 *** comb rbd */ -{ -#ifdef NICENAMES -"comb rbd",8,7, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,57}, - - -/* 1000 1101 flags 0101 *** comflg flags */ -{ -#ifdef NICENAMES -"comflg flags",16,7, -0x3c, -#endif -"comflg",OPC_comflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+5,0,0,0,0,0,},1,2,58}, - - -/* 0000 1101 ddN0 0001 imm16 *** cp @rd,imm16 */ -{ -#ifdef NICENAMES -"cp @rd,imm16",16,11, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,59}, - - -/* 0100 1101 ddN0 0001 address_dst imm16 *** cp address_dst(rd),imm16 */ -{ -#ifdef NICENAMES -"cp address_dst(rd),imm16",16,15, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,60}, - - -/* 0100 1101 0000 0001 address_dst imm16 *** cp address_dst,imm16 */ -{ -#ifdef NICENAMES -"cp address_dst,imm16",16,14, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,61}, - - -/* 0000 1011 ssN0 dddd *** cp rd,@rs */ -{ -#ifdef NICENAMES -"cp rd,@rs",16,7, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,62}, - - -/* 0100 1011 0000 dddd address_src *** cp rd,address_src */ -{ -#ifdef NICENAMES -"cp rd,address_src",16,9, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,63}, - - -/* 0100 1011 ssN0 dddd address_src *** cp rd,address_src(rs) */ -{ -#ifdef NICENAMES -"cp rd,address_src(rs)",16,10, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,64}, - - -/* 0000 1011 0000 dddd imm16 *** cp rd,imm16 */ -{ -#ifdef NICENAMES -"cp rd,imm16",16,7, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,65}, - - -/* 1000 1011 ssss dddd *** cp rd,rs */ -{ -#ifdef NICENAMES -"cp rd,rs",16,4, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,66}, - - -/* 0000 1100 ddN0 0001 imm8 imm8 *** cpb @rd,imm8 */ -{ -#ifdef NICENAMES -"cpb @rd,imm8",8,11, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,67}, - - -/* 0100 1100 ddN0 0001 address_dst imm8 imm8 *** cpb address_dst(rd),imm8 */ -{ -#ifdef NICENAMES -"cpb address_dst(rd),imm8",8,15, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,68}, - - -/* 0100 1100 0000 0001 address_dst imm8 imm8 *** cpb address_dst,imm8 */ -{ -#ifdef NICENAMES -"cpb address_dst,imm8",8,14, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,69}, - - -/* 0000 1010 ssN0 dddd *** cpb rbd,@rs */ -{ -#ifdef NICENAMES -"cpb rbd,@rs",8,7, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,70}, - - -/* 0100 1010 0000 dddd address_src *** cpb rbd,address_src */ -{ -#ifdef NICENAMES -"cpb rbd,address_src",8,9, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, - - -/* 0100 1010 ssN0 dddd address_src *** cpb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"cpb rbd,address_src(rs)",8,10, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, - - -/* 0000 1010 0000 dddd imm8 imm8 *** cpb rbd,imm8 */ -{ -#ifdef NICENAMES -"cpb rbd,imm8",8,7, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,73}, - - -/* 1000 1010 ssss dddd *** cpb rbd,rbs */ -{ -#ifdef NICENAMES -"cpb rbd,rbs",8,4, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, - - -/* 1011 1011 ssN0 1000 0000 rrrr dddd cccc *** cpd rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpd rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpd",OPC_cpd,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,75}, - - -/* 1011 1010 ssN0 1000 0000 rrrr dddd cccc *** cpdb rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpdb rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpdb",OPC_cpdb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,76}, - - -/* 1011 1011 ssN0 1100 0000 rrrr dddd cccc *** cpdr rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpdr rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpdr",OPC_cpdr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,77}, - - -/* 1011 1010 ssN0 1100 0000 rrrr dddd cccc *** cpdrb rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpdrb rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpdrb",OPC_cpdrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,78}, - - -/* 1011 1011 ssN0 0000 0000 rrrr dddd cccc *** cpi rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpi rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpi",OPC_cpi,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,79}, - - -/* 1011 1010 ssN0 0000 0000 rrrr dddd cccc *** cpib rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpib rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpib",OPC_cpib,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,80}, - - -/* 1011 1011 ssN0 0100 0000 rrrr dddd cccc *** cpir rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpir rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpir",OPC_cpir,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,81}, - - -/* 1011 1010 ssN0 0100 0000 rrrr dddd cccc *** cpirb rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpirb rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpirb",OPC_cpirb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,82}, - - -/* 0001 0000 ssN0 dddd *** cpl rrd,@rs */ -{ -#ifdef NICENAMES -"cpl rrd,@rs",32,14, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,83}, - - -/* 0101 0000 0000 dddd address_src *** cpl rrd,address_src */ -{ -#ifdef NICENAMES -"cpl rrd,address_src",32,15, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,84}, - - -/* 0101 0000 ssN0 dddd address_src *** cpl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"cpl rrd,address_src(rs)",32,16, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,85}, - - -/* 0001 0000 0000 dddd imm32 *** cpl rrd,imm32 */ -{ -#ifdef NICENAMES -"cpl rrd,imm32",32,14, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,86}, - - -/* 1001 0000 ssss dddd *** cpl rrd,rrs */ -{ -#ifdef NICENAMES -"cpl rrd,rrs",32,8, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,87}, - - -/* 1011 1011 ssN0 1010 0000 rrrr ddN0 cccc *** cpsd @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsd @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsd",OPC_cpsd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,88}, - - -/* 1011 1010 ssN0 1010 0000 rrrr ddN0 cccc *** cpsdb @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsdb @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsdb",OPC_cpsdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,89}, - - -/* 1011 1011 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdr @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsdr @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsdr",OPC_cpsdr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,90}, - - -/* 1011 1010 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdrb @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsdrb @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsdrb",OPC_cpsdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,91}, - - -/* 1011 1011 ssN0 0010 0000 rrrr ddN0 cccc *** cpsi @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsi @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsi",OPC_cpsi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,92}, - - -/* 1011 1010 ssN0 0010 0000 rrrr ddN0 cccc *** cpsib @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsib @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsib",OPC_cpsib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,93}, - - -/* 1011 1011 ssN0 0110 0000 rrrr ddN0 cccc *** cpsir @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsir @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsir",OPC_cpsir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,94}, - - -/* 1011 1010 ssN0 0110 0000 rrrr ddN0 cccc *** cpsirb @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsirb @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsirb",OPC_cpsirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,95}, - - -/* 1011 0000 dddd 0000 *** dab rbd */ -{ -#ifdef NICENAMES -"dab rbd",8,5, -0x38, -#endif -"dab",OPC_dab,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,96}, - - -/* 1111 dddd 0disp7 *** dbjnz rbd,disp7 */ -{ -#ifdef NICENAMES -"dbjnz rbd,disp7",16,11, -0x00, -#endif -"dbjnz",OPC_dbjnz,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,97}, - - -/* 0010 1011 ddN0 imm4m1 *** dec @rd,imm4m1 */ -{ -#ifdef NICENAMES -"dec @rd,imm4m1",16,11, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,98}, - - -/* 0110 1011 ddN0 imm4m1 address_dst *** dec address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"dec address_dst(rd),imm4m1",16,14, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,99}, - - -/* 0110 1011 0000 imm4m1 address_dst *** dec address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"dec address_dst,imm4m1",16,13, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,100}, - - -/* 1010 1011 dddd imm4m1 *** dec rd,imm4m1 */ -{ -#ifdef NICENAMES -"dec rd,imm4m1",16,4, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,101}, - - -/* 0010 1010 ddN0 imm4m1 *** decb @rd,imm4m1 */ -{ -#ifdef NICENAMES -"decb @rd,imm4m1",8,11, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,102}, - - -/* 0110 1010 ddN0 imm4m1 address_dst *** decb address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"decb address_dst(rd),imm4m1",8,14, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,103}, - - -/* 0110 1010 0000 imm4m1 address_dst *** decb address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"decb address_dst,imm4m1",8,13, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,104}, - - -/* 1010 1010 dddd imm4m1 *** decb rbd,imm4m1 */ -{ -#ifdef NICENAMES -"decb rbd,imm4m1",8,4, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,105}, - - -/* 0111 1100 0000 00ii *** di i2 */ -{ -#ifdef NICENAMES -"di i2",16,7, -0x00, -#endif -"di",OPC_di,0,{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,106}, - - -/* 0001 1011 ssN0 dddd *** div rrd,@rs */ -{ -#ifdef NICENAMES -"div rrd,@rs",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,107}, - - -/* 0101 1011 0000 dddd address_src *** div rrd,address_src */ -{ -#ifdef NICENAMES -"div rrd,address_src",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,108}, - - -/* 0101 1011 ssN0 dddd address_src *** div rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"div rrd,address_src(rs)",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,109}, - - -/* 0001 1011 0000 dddd imm16 *** div rrd,imm16 */ -{ -#ifdef NICENAMES -"div rrd,imm16",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,110}, - - -/* 1001 1011 ssss dddd *** div rrd,rs */ -{ -#ifdef NICENAMES -"div rrd,rs",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,111}, - - -/* 0001 1010 ssN0 dddd *** divl rqd,@rs */ -{ -#ifdef NICENAMES -"divl rqd,@rs",32,744, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,112}, - - -/* 0101 1010 0000 dddd address_src *** divl rqd,address_src */ -{ -#ifdef NICENAMES -"divl rqd,address_src",32,745, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,113}, - - -/* 0101 1010 ssN0 dddd address_src *** divl rqd,address_src(rs) */ -{ -#ifdef NICENAMES -"divl rqd,address_src(rs)",32,746, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,114}, - - -/* 0001 1010 0000 dddd imm32 *** divl rqd,imm32 */ -{ -#ifdef NICENAMES -"divl rqd,imm32",32,744, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,115}, - - -/* 1001 1010 ssss dddd *** divl rqd,rrs */ -{ -#ifdef NICENAMES -"divl rqd,rrs",32,744, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,116}, - - -/* 1111 dddd 1disp7 *** djnz rd,disp7 */ -{ -#ifdef NICENAMES -"djnz rd,disp7",16,11, -0x00, -#endif -"djnz",OPC_djnz,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,117}, - - -/* 0111 1100 0000 01ii *** ei i2 */ -{ -#ifdef NICENAMES -"ei i2",16,7, -0x00, -#endif -"ei",OPC_ei,0,{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,118}, - - -/* 0010 1101 ssN0 dddd *** ex rd,@rs */ -{ -#ifdef NICENAMES -"ex rd,@rs",16,12, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,119}, - - -/* 0110 1101 0000 dddd address_src *** ex rd,address_src */ -{ -#ifdef NICENAMES -"ex rd,address_src",16,15, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,120}, - - -/* 0110 1101 ssN0 dddd address_src *** ex rd,address_src(rs) */ -{ -#ifdef NICENAMES -"ex rd,address_src(rs)",16,16, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,121}, - - -/* 1010 1101 ssss dddd *** ex rd,rs */ -{ -#ifdef NICENAMES -"ex rd,rs",16,6, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,122}, - - -/* 0010 1100 ssN0 dddd *** exb rbd,@rs */ -{ -#ifdef NICENAMES -"exb rbd,@rs",8,12, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,123}, - - -/* 0110 1100 0000 dddd address_src *** exb rbd,address_src */ -{ -#ifdef NICENAMES -"exb rbd,address_src",8,15, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,124}, - - -/* 0110 1100 ssN0 dddd address_src *** exb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"exb rbd,address_src(rs)",8,16, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,125}, - - -/* 1010 1100 ssss dddd *** exb rbd,rbs */ -{ -#ifdef NICENAMES -"exb rbd,rbs",8,6, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,126}, - - -/* 0000 1110 imm8 *** ext0e imm8 */ -{ -#ifdef NICENAMES -"ext0e imm8",8,10, -0x00, -#endif -"ext0e",OPC_ext0e,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,127}, - - -/* 0000 1111 imm8 *** ext0f imm8 */ -{ -#ifdef NICENAMES -"ext0f imm8",8,10, -0x00, -#endif -"ext0f",OPC_ext0f,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,128}, - - -/* 1000 1110 imm8 *** ext8e imm8 */ -{ -#ifdef NICENAMES -"ext8e imm8",8,10, -0x00, -#endif -"ext8e",OPC_ext8e,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+8,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,129}, - - -/* 1000 1111 imm8 *** ext8f imm8 */ -{ -#ifdef NICENAMES -"ext8f imm8",8,10, -0x00, -#endif -"ext8f",OPC_ext8f,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+8,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,130}, - - -/* 1011 0001 dddd 1010 *** exts rrd */ -{ -#ifdef NICENAMES -"exts rrd",16,11, -0x00, -#endif -"exts",OPC_exts,0,{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0xa,0,0,0,0,0,},1,2,131}, - - -/* 1011 0001 dddd 0000 *** extsb rd */ -{ -#ifdef NICENAMES -"extsb rd",8,11, -0x00, -#endif -"extsb",OPC_extsb,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,132}, - - -/* 1011 0001 dddd 0111 *** extsl rqd */ -{ -#ifdef NICENAMES -"extsl rqd",32,11, -0x00, -#endif -"extsl",OPC_extsl,0,{CLASS_REG_QUAD+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,133}, - - -/* 0111 1010 0000 0000 *** halt */ -{ -#ifdef NICENAMES -"halt",16,8, -0x00, -#endif -"halt",OPC_halt,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,134}, - - -/* 0011 1101 ssN0 dddd *** in rd,@rs */ -{ -#ifdef NICENAMES -"in rd,@rs",16,10, -0x00, -#endif -"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,135}, - - -/* 0011 1101 dddd 0100 imm16 *** in rd,imm16 */ -{ -#ifdef NICENAMES -"in rd,imm16",16,12, -0x00, -#endif -"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,136}, - - -/* 0011 1100 ssN0 dddd *** inb rbd,@rs */ -{ -#ifdef NICENAMES -"inb rbd,@rs",8,12, -0x00, -#endif -"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,137}, - - -/* 0011 1010 dddd 0100 imm16 *** inb rbd,imm16 */ -{ -#ifdef NICENAMES -"inb rbd,imm16",8,10, -0x00, -#endif -"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,138}, - - -/* 0010 1001 ddN0 imm4m1 *** inc @rd,imm4m1 */ -{ -#ifdef NICENAMES -"inc @rd,imm4m1",16,11, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,139}, - - -/* 0110 1001 ddN0 imm4m1 address_dst *** inc address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"inc address_dst(rd),imm4m1",16,14, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,140}, - - -/* 0110 1001 0000 imm4m1 address_dst *** inc address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"inc address_dst,imm4m1",16,13, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,141}, - - -/* 1010 1001 dddd imm4m1 *** inc rd,imm4m1 */ -{ -#ifdef NICENAMES -"inc rd,imm4m1",16,4, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,142}, - - -/* 0010 1000 ddN0 imm4m1 *** incb @rd,imm4m1 */ -{ -#ifdef NICENAMES -"incb @rd,imm4m1",8,11, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,143}, - - -/* 0110 1000 ddN0 imm4m1 address_dst *** incb address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"incb address_dst(rd),imm4m1",8,14, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,144}, - - -/* 0110 1000 0000 imm4m1 address_dst *** incb address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"incb address_dst,imm4m1",8,13, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,145}, - - -/* 1010 1000 dddd imm4m1 *** incb rbd,imm4m1 */ -{ -#ifdef NICENAMES -"incb rbd,imm4m1",8,4, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,146}, - - -/* 0011 1011 ssN0 1000 0000 aaaa ddN0 1000 *** ind @rd,@rs,ra */ -{ -#ifdef NICENAMES -"ind @rd,@rs,ra",16,21, -0x04, -#endif -"ind",OPC_ind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,147}, - - -/* 0011 1010 ssN0 1000 0000 aaaa ddN0 1000 *** indb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"indb @rd,@rs,rba",8,21, -0x04, -#endif -"indb",OPC_indb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,148}, - - -/* 0011 1010 ssN0 0000 0000 aaaa ddN0 1000 *** inib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"inib @rd,@rs,ra",8,21, -0x04, -#endif -"inib",OPC_inib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,149}, - - -/* 0011 1010 ssN0 0000 0000 aaaa ddN0 0000 *** inibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"inibr @rd,@rs,ra",16,21, -0x04, -#endif -"inibr",OPC_inibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,150}, - - -/* 0111 1011 0000 0000 *** iret */ -{ -#ifdef NICENAMES -"iret",16,13, -0x3f, -#endif -"iret",OPC_iret,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,151}, - - -/* 0001 1110 ddN0 cccc *** jp cc,@rd */ -{ -#ifdef NICENAMES -"jp cc,@rd",16,10, -0x00, -#endif -"jp",OPC_jp,0,{CLASS_CC,CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,152}, - - -/* 0101 1110 0000 cccc address_dst *** jp cc,address_dst */ -{ -#ifdef NICENAMES -"jp cc,address_dst",16,7, -0x00, -#endif -"jp",OPC_jp,0,{CLASS_CC,CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,153}, - - -/* 0101 1110 ddN0 cccc address_dst *** jp cc,address_dst(rd) */ -{ -#ifdef NICENAMES -"jp cc,address_dst(rd)",16,8, -0x00, -#endif -"jp",OPC_jp,0,{CLASS_CC,CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,154}, - - -/* 1110 cccc disp8 *** jr cc,disp8 */ -{ -#ifdef NICENAMES -"jr cc,disp8",16,6, -0x00, -#endif -"jr",OPC_jr,0,{CLASS_CC,CLASS_DISP,}, - {CLASS_BIT+0xe,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,155}, - - -/* 0000 1101 ddN0 0101 imm16 *** ld @rd,imm16 */ -{ -#ifdef NICENAMES -"ld @rd,imm16",16,7, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,156}, - - -/* 0010 1111 ddN0 ssss *** ld @rd,rs */ -{ -#ifdef NICENAMES -"ld @rd,rs",16,8, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,157}, - - -/* 0100 1101 ddN0 0101 address_dst imm16 *** ld address_dst(rd),imm16 */ -{ -#ifdef NICENAMES -"ld address_dst(rd),imm16",16,15, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,158}, - - -/* 0110 1111 ddN0 ssss address_dst *** ld address_dst(rd),rs */ -{ -#ifdef NICENAMES -"ld address_dst(rd),rs",16,12, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,159}, - - -/* 0100 1101 0000 0101 address_dst imm16 *** ld address_dst,imm16 */ -{ -#ifdef NICENAMES -"ld address_dst,imm16",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,160}, - - -/* 0110 1111 0000 ssss address_dst *** ld address_dst,rs */ -{ -#ifdef NICENAMES -"ld address_dst,rs",16,11, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,161}, - - -/* 0011 0011 ddN0 ssss imm16 *** ld rd(imm16),rs */ -{ -#ifdef NICENAMES -"ld rd(imm16),rs",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,162}, - - -/* 0111 0011 ddN0 ssss 0000 xxxx 0000 0000 *** ld rd(rx),rs */ -{ -#ifdef NICENAMES -"ld rd(rx),rs",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,163}, - - -/* 0010 0001 ssN0 dddd *** ld rd,@rs */ -{ -#ifdef NICENAMES -"ld rd,@rs",16,7, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,164}, - - -/* 0110 0001 0000 dddd address_src *** ld rd,address_src */ -{ -#ifdef NICENAMES -"ld rd,address_src",16,9, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,165}, - - -/* 0110 0001 ssN0 dddd address_src *** ld rd,address_src(rs) */ -{ -#ifdef NICENAMES -"ld rd,address_src(rs)",16,10, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,166}, - - -/* 0010 0001 0000 dddd imm16 *** ld rd,imm16 */ -{ -#ifdef NICENAMES -"ld rd,imm16",16,7, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,167}, - - -/* 1010 0001 ssss dddd *** ld rd,rs */ -{ -#ifdef NICENAMES -"ld rd,rs",16,3, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,168}, - - -/* 0011 0001 ssN0 dddd imm16 *** ld rd,rs(imm16) */ -{ -#ifdef NICENAMES -"ld rd,rs(imm16)",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,169}, - - -/* 0111 0001 ssN0 dddd 0000 xxxx 0000 0000 *** ld rd,rs(rx) */ -{ -#ifdef NICENAMES -"ld rd,rs(rx)",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,170}, - - -/* 0111 0110 0000 dddd address_src *** lda prd,address_src */ -{ -#ifdef NICENAMES -"lda prd,address_src",16,12, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,171}, - - -/* 0111 0110 ssN0 dddd address_src *** lda prd,address_src(rs) */ -{ -#ifdef NICENAMES -"lda prd,address_src(rs)",16,13, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,172}, - - -/* 0011 0100 ssN0 dddd imm16 *** lda prd,rs(imm16) */ -{ -#ifdef NICENAMES -"lda prd,rs(imm16)",16,15, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,173}, - - -/* 0111 0100 ssN0 dddd 0000 xxxx 0000 0000 *** lda prd,rs(rx) */ -{ -#ifdef NICENAMES -"lda prd,rs(rx)",16,15, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,174}, - - -/* 0011 0100 0000 dddd disp16 *** ldar prd,disp16 */ -{ -#ifdef NICENAMES -"ldar prd,disp16",16,15, -0x00, -#endif -"ldar",OPC_ldar,0,{CLASS_PR+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,175}, - - -/* 0000 1100 ddN0 0101 imm8 imm8 *** ldb @rd,imm8 */ -{ -#ifdef NICENAMES -"ldb @rd,imm8",8,7, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,176}, - - -/* 0010 1110 ddN0 ssss *** ldb @rd,rbs */ -{ -#ifdef NICENAMES -"ldb @rd,rbs",8,8, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,177}, - - -/* 0100 1100 ddN0 0101 address_dst imm8 imm8 *** ldb address_dst(rd),imm8 */ -{ -#ifdef NICENAMES -"ldb address_dst(rd),imm8",8,15, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,178}, - - -/* 0110 1110 ddN0 ssss address_dst *** ldb address_dst(rd),rbs */ -{ -#ifdef NICENAMES -"ldb address_dst(rd),rbs",8,12, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,179}, - - -/* 0100 1100 0000 0101 address_dst imm8 imm8 *** ldb address_dst,imm8 */ -{ -#ifdef NICENAMES -"ldb address_dst,imm8",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,180}, - - -/* 0110 1110 0000 ssss address_dst *** ldb address_dst,rbs */ -{ -#ifdef NICENAMES -"ldb address_dst,rbs",8,11, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,181}, - - -/* 0010 0000 ssN0 dddd *** ldb rbd,@rs */ -{ -#ifdef NICENAMES -"ldb rbd,@rs",8,7, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,182}, - - -/* 0110 0000 0000 dddd address_src *** ldb rbd,address_src */ -{ -#ifdef NICENAMES -"ldb rbd,address_src",8,9, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, - - -/* 0110 0000 ssN0 dddd address_src *** ldb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"ldb rbd,address_src(rs)",8,10, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, - - -/* 1100 dddd imm8 *** ldb rbd,imm8 */ -{ -#ifdef NICENAMES -"ldb rbd,imm8",8,5, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,185}, - - -/* 1010 0000 ssss dddd *** ldb rbd,rbs */ -{ -#ifdef NICENAMES -"ldb rbd,rbs",8,3, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,186}, - - -/* 0011 0000 ssN0 dddd imm16 *** ldb rbd,rs(imm16) */ -{ -#ifdef NICENAMES -"ldb rbd,rs(imm16)",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,187}, - - -/* 0111 0000 ssN0 dddd 0000 xxxx 0000 0000 *** ldb rbd,rs(rx) */ -{ -#ifdef NICENAMES -"ldb rbd,rs(rx)",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,188}, - - -/* 0011 0010 ddN0 ssss imm16 *** ldb rd(imm16),rbs */ -{ -#ifdef NICENAMES -"ldb rd(imm16),rbs",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,189}, - - -/* 0111 0010 ddN0 ssss 0000 xxxx 0000 0000 *** ldb rd(rx),rbs */ -{ -#ifdef NICENAMES -"ldb rd(rx),rbs",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,190}, - - -/* 0111 1101 ssss 1ccc *** ldctl ctrl,rs */ -{ -#ifdef NICENAMES -"ldctl ctrl,rs",32,7, -0x00, -#endif -"ldctl",OPC_ldctl,0,{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,191}, - - -/* 0111 1101 dddd 0ccc *** ldctl rd,ctrl */ -{ -#ifdef NICENAMES -"ldctl rd,ctrl",32,7, -0x00, -#endif -"ldctl",OPC_ldctl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,}, - {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,192}, - - -/* 1011 1011 ssN0 1001 0000 rrrr ddN0 1000 *** ldd @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldd @rd,@rs,rr",16,11, -0x04, -#endif -"ldd",OPC_ldd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,193}, - - -/* 1011 1010 ssN0 1001 0000 rrrr ddN0 1000 *** lddb @rd,@rs,rr */ -{ -#ifdef NICENAMES -"lddb @rd,@rs,rr",8,11, -0x04, -#endif -"lddb",OPC_lddb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,194}, - - -/* 1011 1011 ssN0 1001 0000 rrrr ddN0 0000 *** lddr @rd,@rs,rr */ -{ -#ifdef NICENAMES -"lddr @rd,@rs,rr",16,11, -0x04, -#endif -"lddr",OPC_lddr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,195}, - - -/* 1011 1010 ssN0 1001 0000 rrrr ddN0 0000 *** lddrb @rd,@rs,rr */ -{ -#ifdef NICENAMES -"lddrb @rd,@rs,rr",8,11, -0x04, -#endif -"lddrb",OPC_lddrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,196}, - - -/* 1011 1011 ssN0 0001 0000 rrrr ddN0 1000 *** ldi @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldi @rd,@rs,rr",16,11, -0x04, -#endif -"ldi",OPC_ldi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,197}, - - -/* 1011 1010 ssN0 0001 0000 rrrr ddN0 1000 *** ldib @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldib @rd,@rs,rr",8,11, -0x04, -#endif -"ldib",OPC_ldib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,198}, - - -/* 1011 1011 ssN0 0001 0000 rrrr ddN0 0000 *** ldir @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldir @rd,@rs,rr",16,11, -0x04, -#endif -"ldir",OPC_ldir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,199}, - - -/* 1011 1010 ssN0 0001 0000 rrrr ddN0 0000 *** ldirb @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldirb @rd,@rs,rr",8,11, -0x04, -#endif -"ldirb",OPC_ldirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,200}, - - -/* 1011 1101 dddd imm4 *** ldk rd,imm4 */ -{ -#ifdef NICENAMES -"ldk rd,imm4",16,5, -0x00, -#endif -"ldk",OPC_ldk,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,201}, - - -/* 0001 1101 ddN0 ssss *** ldl @rd,rrs */ -{ -#ifdef NICENAMES -"ldl @rd,rrs",32,11, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,202}, - - -/* 0101 1101 ddN0 ssss address_dst *** ldl address_dst(rd),rrs */ -{ -#ifdef NICENAMES -"ldl address_dst(rd),rrs",32,14, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,203}, - - -/* 0101 1101 0000 ssss address_dst *** ldl address_dst,rrs */ -{ -#ifdef NICENAMES -"ldl address_dst,rrs",32,15, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_DA+(ARG_DST),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,204}, - - -/* 0011 0111 ddN0 ssss imm16 *** ldl rd(imm16),rrs */ -{ -#ifdef NICENAMES -"ldl rd(imm16),rrs",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,205}, - - -/* 0111 0111 ddN0 ssss 0000 xxxx 0000 0000 *** ldl rd(rx),rrs */ -{ -#ifdef NICENAMES -"ldl rd(rx),rrs",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,206}, - - -/* 0001 0100 ssN0 dddd *** ldl rrd,@rs */ -{ -#ifdef NICENAMES -"ldl rrd,@rs",32,11, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,207}, - - -/* 0101 0100 0000 dddd address_src *** ldl rrd,address_src */ -{ -#ifdef NICENAMES -"ldl rrd,address_src",32,12, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,208}, - - -/* 0101 0100 ssN0 dddd address_src *** ldl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"ldl rrd,address_src(rs)",32,13, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,209}, - - -/* 0001 0100 0000 dddd imm32 *** ldl rrd,imm32 */ -{ -#ifdef NICENAMES -"ldl rrd,imm32",32,11, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,210}, - - -/* 1001 0100 ssss dddd *** ldl rrd,rrs */ -{ -#ifdef NICENAMES -"ldl rrd,rrs",32,5, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,211}, - - -/* 0011 0101 ssN0 dddd imm16 *** ldl rrd,rs(imm16) */ -{ -#ifdef NICENAMES -"ldl rrd,rs(imm16)",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,212}, - - -/* 0111 0101 ssN0 dddd 0000 xxxx 0000 0000 *** ldl rrd,rs(rx) */ -{ -#ifdef NICENAMES -"ldl rrd,rs(rx)",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,213}, - - -/* 0001 1100 ddN0 1001 0000 ssss 0000 nminus1 *** ldm @rd,rs,n */ -{ -#ifdef NICENAMES -"ldm @rd,rs,n",16,11, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,214}, - - -/* 0101 1100 ddN0 1001 0000 ssss 0000 nminus1 address_dst *** ldm address_dst(rd),rs,n */ -{ -#ifdef NICENAMES -"ldm address_dst(rd),rs,n",16,15, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_DST),},3,6,215}, - - -/* 0101 1100 0000 1001 0000 ssss 0000 nminus1 address_dst *** ldm address_dst,rs,n */ -{ -#ifdef NICENAMES -"ldm address_dst,rs,n",16,14, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_DST),},3,6,216}, - - -/* 0001 1100 ssN0 0001 0000 dddd 0000 nminus1 *** ldm rd,@rs,n */ -{ -#ifdef NICENAMES -"ldm rd,@rs,n",16,11, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,217}, - - -/* 0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address_src *** ldm rd,address_src(rs),n */ -{ -#ifdef NICENAMES -"ldm rd,address_src(rs),n",16,15, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_SRC),},3,6,218}, - - -/* 0101 1100 0000 0001 0000 dddd 0000 nminus1 address_src *** ldm rd,address_src,n */ -{ -#ifdef NICENAMES -"ldm rd,address_src,n",16,14, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_SRC),},3,6,219}, - - -/* 0011 1001 ssN0 0000 *** ldps @rs */ -{ -#ifdef NICENAMES -"ldps @rs",16,12, -0x3f, -#endif -"ldps",OPC_ldps,0,{CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,220}, - - -/* 0111 1001 0000 0000 address_src *** ldps address_src */ -{ -#ifdef NICENAMES -"ldps address_src",16,16, -0x3f, -#endif -"ldps",OPC_ldps,0,{CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,221}, - - -/* 0111 1001 ssN0 0000 address_src *** ldps address_src(rs) */ -{ -#ifdef NICENAMES -"ldps address_src(rs)",16,17, -0x3f, -#endif -"ldps",OPC_ldps,0,{CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,222}, - - -/* 0011 0011 0000 ssss disp16 *** ldr disp16,rs */ -{ -#ifdef NICENAMES -"ldr disp16,rs",16,14, -0x00, -#endif -"ldr",OPC_ldr,0,{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,223}, - - -/* 0011 0001 0000 dddd disp16 *** ldr rd,disp16 */ -{ -#ifdef NICENAMES -"ldr rd,disp16",16,14, -0x00, -#endif -"ldr",OPC_ldr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,224}, - - -/* 0011 0010 0000 ssss disp16 *** ldrb disp16,rbs */ -{ -#ifdef NICENAMES -"ldrb disp16,rbs",8,14, -0x00, -#endif -"ldrb",OPC_ldrb,0,{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,225}, - - -/* 0011 0000 0000 dddd disp16 *** ldrb rbd,disp16 */ -{ -#ifdef NICENAMES -"ldrb rbd,disp16",8,14, -0x00, -#endif -"ldrb",OPC_ldrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,226}, - - -/* 0011 0111 0000 ssss disp16 *** ldrl disp16,rrs */ -{ -#ifdef NICENAMES -"ldrl disp16,rrs",32,17, -0x00, -#endif -"ldrl",OPC_ldrl,0,{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,227}, - - -/* 0011 0101 0000 dddd disp16 *** ldrl rrd,disp16 */ -{ -#ifdef NICENAMES -"ldrl rrd,disp16",32,17, -0x00, -#endif -"ldrl",OPC_ldrl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,228}, - - -/* 0111 1011 0000 1010 *** mbit */ -{ -#ifdef NICENAMES -"mbit",16,7, -0x38, -#endif -"mbit",OPC_mbit,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0xa,0,0,0,0,0,},0,2,229}, - - -/* 0111 1011 dddd 1101 *** mreq rd */ -{ -#ifdef NICENAMES -"mreq rd",16,12, -0x18, -#endif -"mreq",OPC_mreq,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,0,0,0,0,0,},1,2,230}, - - -/* 0111 1011 0000 1001 *** mres */ -{ -#ifdef NICENAMES -"mres",16,5, -0x00, -#endif -"mres",OPC_mres,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,231}, - - -/* 0111 1011 0000 1000 *** mset */ -{ -#ifdef NICENAMES -"mset",16,5, -0x00, -#endif -"mset",OPC_mset,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,232}, - - -/* 0001 1001 ssN0 dddd *** mult rrd,@rs */ -{ -#ifdef NICENAMES -"mult rrd,@rs",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,233}, - - -/* 0101 1001 0000 dddd address_src *** mult rrd,address_src */ -{ -#ifdef NICENAMES -"mult rrd,address_src",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,234}, - - -/* 0101 1001 ssN0 dddd address_src *** mult rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"mult rrd,address_src(rs)",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,235}, - - -/* 0001 1001 0000 dddd imm16 *** mult rrd,imm16 */ -{ -#ifdef NICENAMES -"mult rrd,imm16",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,236}, - - -/* 1001 1001 ssss dddd *** mult rrd,rs */ -{ -#ifdef NICENAMES -"mult rrd,rs",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,237}, - - -/* 0001 1000 ssN0 dddd *** multl rqd,@rs */ -{ -#ifdef NICENAMES -"multl rqd,@rs",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,238}, - - -/* 0101 1000 0000 dddd address_src *** multl rqd,address_src */ -{ -#ifdef NICENAMES -"multl rqd,address_src",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,239}, - - -/* 0101 1000 ssN0 dddd address_src *** multl rqd,address_src(rs) */ -{ -#ifdef NICENAMES -"multl rqd,address_src(rs)",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,240}, - - -/* 0001 1000 0000 dddd imm32 *** multl rqd,imm32 */ -{ -#ifdef NICENAMES -"multl rqd,imm32",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,241}, - - -/* 1001 1000 ssss dddd *** multl rqd,rrs */ -{ -#ifdef NICENAMES -"multl rqd,rrs",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,242}, - - -/* 0000 1101 ddN0 0010 *** neg @rd */ -{ -#ifdef NICENAMES -"neg @rd",16,12, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,243}, - - -/* 0100 1101 0000 0010 address_dst *** neg address_dst */ -{ -#ifdef NICENAMES -"neg address_dst",16,15, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,244}, - - -/* 0100 1101 ddN0 0010 address_dst *** neg address_dst(rd) */ -{ -#ifdef NICENAMES -"neg address_dst(rd)",16,16, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,245}, - - -/* 1000 1101 dddd 0010 *** neg rd */ -{ -#ifdef NICENAMES -"neg rd",16,7, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,246}, - - -/* 0000 1100 ddN0 0010 *** negb @rd */ -{ -#ifdef NICENAMES -"negb @rd",8,12, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,247}, - - -/* 0100 1100 0000 0010 address_dst *** negb address_dst */ -{ -#ifdef NICENAMES -"negb address_dst",8,15, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,248}, - - -/* 0100 1100 ddN0 0010 address_dst *** negb address_dst(rd) */ -{ -#ifdef NICENAMES -"negb address_dst(rd)",8,16, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,249}, - - -/* 1000 1100 dddd 0010 *** negb rbd */ -{ -#ifdef NICENAMES -"negb rbd",8,7, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,250}, - - -/* 1000 1101 0000 0111 *** nop */ -{ -#ifdef NICENAMES -"nop",16,7, -0x00, -#endif -"nop",OPC_nop,0,{0}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,251}, - - -/* 0000 0101 ssN0 dddd *** or rd,@rs */ -{ -#ifdef NICENAMES -"or rd,@rs",16,7, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,252}, - - -/* 0100 0101 0000 dddd address_src *** or rd,address_src */ -{ -#ifdef NICENAMES -"or rd,address_src",16,9, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,253}, - - -/* 0100 0101 ssN0 dddd address_src *** or rd,address_src(rs) */ -{ -#ifdef NICENAMES -"or rd,address_src(rs)",16,10, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,254}, - - -/* 0000 0101 0000 dddd imm16 *** or rd,imm16 */ -{ -#ifdef NICENAMES -"or rd,imm16",16,7, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,255}, - - -/* 1000 0101 ssss dddd *** or rd,rs */ -{ -#ifdef NICENAMES -"or rd,rs",16,4, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,256}, - - -/* 0000 0100 ssN0 dddd *** orb rbd,@rs */ -{ -#ifdef NICENAMES -"orb rbd,@rs",8,7, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,257}, - - -/* 0100 0100 0000 dddd address_src *** orb rbd,address_src */ -{ -#ifdef NICENAMES -"orb rbd,address_src",8,9, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,258}, - - -/* 0100 0100 ssN0 dddd address_src *** orb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"orb rbd,address_src(rs)",8,10, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,259}, - - -/* 0000 0100 0000 dddd imm8 imm8 *** orb rbd,imm8 */ -{ -#ifdef NICENAMES -"orb rbd,imm8",8,7, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,260}, - - -/* 1000 0100 ssss dddd *** orb rbd,rbs */ -{ -#ifdef NICENAMES -"orb rbd,rbs",8,4, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,261}, - - -/* 0011 1111 ddN0 ssss *** out @rd,rs */ -{ -#ifdef NICENAMES -"out @rd,rs",16,0, -0x04, -#endif -"out",OPC_out,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,262}, - - -/* 0011 1011 ssss 0110 imm16 *** out imm16,rs */ -{ -#ifdef NICENAMES -"out imm16,rs",16,0, -0x04, -#endif -"out",OPC_out,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,263}, - - -/* 0011 1110 ddN0 ssss *** outb @rd,rbs */ -{ -#ifdef NICENAMES -"outb @rd,rbs",8,0, -0x04, -#endif -"outb",OPC_outb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,264}, - - -/* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */ -{ -#ifdef NICENAMES -"outb imm16,rbs",8,0, -0x04, -#endif -"outb",OPC_outb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,265}, - - -/* 0011 1011 ssN0 1010 0000 aaaa ddN0 1000 *** outd @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outd @rd,@rs,ra",16,0, -0x04, -#endif -"outd",OPC_outd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,266}, - - -/* 0011 1010 ssN0 1010 0000 aaaa ddN0 1000 *** outdb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"outdb @rd,@rs,rba",16,0, -0x04, -#endif -"outdb",OPC_outdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,267}, - - -/* 0011 1011 ssN0 0010 0000 aaaa ddN0 1000 *** outi @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outi @rd,@rs,ra",16,0, -0x04, -#endif -"outi",OPC_outi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,268}, - - -/* 0011 1010 ssN0 0010 0000 aaaa ddN0 1000 *** outib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outib @rd,@rs,ra",16,0, -0x04, -#endif -"outib",OPC_outib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,269}, - - -/* 0011 1010 ssN0 0010 0000 aaaa ddN0 0000 *** outibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outibr @rd,@rs,ra",16,0, -0x04, -#endif -"outibr",OPC_outibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,270}, - - -/* 0001 0111 ssN0 ddN0 *** pop @rd,@rs */ -{ -#ifdef NICENAMES -"pop @rd,@rs",16,12, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,271}, - - -/* 0101 0111 ssN0 ddN0 address_dst *** pop address_dst(rd),@rs */ -{ -#ifdef NICENAMES -"pop address_dst(rd),@rs",16,16, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,272}, - - -/* 0101 0111 ssN0 0000 address_dst *** pop address_dst,@rs */ -{ -#ifdef NICENAMES -"pop address_dst,@rs",16,16, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,273}, - - -/* 1001 0111 ssN0 dddd *** pop rd,@rs */ -{ -#ifdef NICENAMES -"pop rd,@rs",16,8, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,274}, - - -/* 0001 0101 ssN0 ddN0 *** popl @rd,@rs */ -{ -#ifdef NICENAMES -"popl @rd,@rs",32,19, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,275}, - - -/* 0101 0101 ssN0 ddN0 address_dst *** popl address_dst(rd),@rs */ -{ -#ifdef NICENAMES -"popl address_dst(rd),@rs",32,23, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,276}, - - -/* 0101 0101 ssN0 0000 address_dst *** popl address_dst,@rs */ -{ -#ifdef NICENAMES -"popl address_dst,@rs",32,23, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,277}, - - -/* 1001 0101 ssN0 dddd *** popl rrd,@rs */ -{ -#ifdef NICENAMES -"popl rrd,@rs",32,12, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,278}, - - -/* 0001 0011 ddN0 ssN0 *** push @rd,@rs */ -{ -#ifdef NICENAMES -"push @rd,@rs",16,13, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,279}, - - -/* 0101 0011 ddN0 0000 address_src *** push @rd,address_src */ -{ -#ifdef NICENAMES -"push @rd,address_src",16,14, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,280}, - - -/* 0101 0011 ddN0 ssN0 address_src *** push @rd,address_src(rs) */ -{ -#ifdef NICENAMES -"push @rd,address_src(rs)",16,14, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,281}, - - -/* 0000 1101 ddN0 1001 imm16 *** push @rd,imm16 */ -{ -#ifdef NICENAMES -"push @rd,imm16",16,12, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,282}, - - -/* 1001 0011 ddN0 ssss *** push @rd,rs */ -{ -#ifdef NICENAMES -"push @rd,rs",16,9, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,283}, - - -/* 0001 0001 ddN0 ssN0 *** pushl @rd,@rs */ -{ -#ifdef NICENAMES -"pushl @rd,@rs",32,20, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,284}, - - -/* 0101 0001 ddN0 0000 address_src *** pushl @rd,address_src */ -{ -#ifdef NICENAMES -"pushl @rd,address_src",32,21, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,285}, - - -/* 0101 0001 ddN0 ssN0 address_src *** pushl @rd,address_src(rs) */ -{ -#ifdef NICENAMES -"pushl @rd,address_src(rs)",32,21, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,286}, - - -/* 1001 0001 ddN0 ssss *** pushl @rd,rrs */ -{ -#ifdef NICENAMES -"pushl @rd,rrs",32,12, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,287}, - - -/* 0010 0011 ddN0 imm4 *** res @rd,imm4 */ -{ -#ifdef NICENAMES -"res @rd,imm4",16,11, -0x00, -#endif -"res",OPC_res,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,288}, - - -/* 0110 0011 ddN0 imm4 address_dst *** res address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"res address_dst(rd),imm4",16,14, -0x00, -#endif -"res",OPC_res,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,289}, - - -/* 0110 0011 0000 imm4 address_dst *** res address_dst,imm4 */ -{ -#ifdef NICENAMES -"res address_dst,imm4",16,13, -0x00, -#endif -"res",OPC_res,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,290}, - - -/* 1010 0011 dddd imm4 *** res rd,imm4 */ -{ -#ifdef NICENAMES -"res rd,imm4",16,4, -0x00, -#endif -"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,291}, - - -/* 0010 0011 0000 ssss 0000 dddd 0000 0000 *** res rd,rs */ -{ -#ifdef NICENAMES -"res rd,rs",16,10, -0x00, -#endif -"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,292}, - - -/* 0010 0010 ddN0 imm4 *** resb @rd,imm4 */ -{ -#ifdef NICENAMES -"resb @rd,imm4",8,11, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,293}, - - -/* 0110 0010 ddN0 imm4 address_dst *** resb address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"resb address_dst(rd),imm4",8,14, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,294}, - - -/* 0110 0010 0000 imm4 address_dst *** resb address_dst,imm4 */ -{ -#ifdef NICENAMES -"resb address_dst,imm4",8,13, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,295}, - - -/* 1010 0010 dddd imm4 *** resb rbd,imm4 */ -{ -#ifdef NICENAMES -"resb rbd,imm4",8,4, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,296}, - - -/* 0010 0010 0000 ssss 0000 dddd 0000 0000 *** resb rbd,rs */ -{ -#ifdef NICENAMES -"resb rbd,rs",8,10, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,297}, - - -/* 1000 1101 flags 0011 *** resflg flags */ -{ -#ifdef NICENAMES -"resflg flags",16,7, -0x3c, -#endif -"resflg",OPC_resflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+3,0,0,0,0,0,},1,2,298}, - - -/* 1001 1110 0000 cccc *** ret cc */ -{ -#ifdef NICENAMES -"ret cc",16,10, -0x00, -#endif -"ret",OPC_ret,0,{CLASS_CC,}, - {CLASS_BIT+9,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,299}, - - -/* 1011 0011 dddd 00I0 *** rl rd,imm1or2 */ -{ -#ifdef NICENAMES -"rl rd,imm1or2",16,6, -0x3c, -#endif -"rl",OPC_rl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,300}, - - -/* 1011 0010 dddd 00I0 *** rlb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rlb rbd,imm1or2",8,6, -0x3c, -#endif -"rlb",OPC_rlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,301}, - - -/* 1011 0011 dddd 10I0 *** rlc rd,imm1or2 */ -{ -#ifdef NICENAMES -"rlc rd,imm1or2",16,6, -0x3c, -#endif -"rlc",OPC_rlc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,302}, - - -/* 1011 0010 dddd 10I0 *** rlcb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rlcb rbd,imm1or2",8,9, -0x10, -#endif -"rlcb",OPC_rlcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,303}, - - -/* 1011 1110 aaaa bbbb *** rldb rbb,rba */ -{ -#ifdef NICENAMES -"rldb rbb,rba",8,9, -0x10, -#endif -"rldb",OPC_rldb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+0xe,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,304}, - - -/* 1011 0011 dddd 01I0 *** rr rd,imm1or2 */ -{ -#ifdef NICENAMES -"rr rd,imm1or2",16,6, -0x3c, -#endif -"rr",OPC_rr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,305}, - - -/* 1011 0010 dddd 01I0 *** rrb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rrb rbd,imm1or2",8,6, -0x3c, -#endif -"rrb",OPC_rrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,306}, - - -/* 1011 0011 dddd 11I0 *** rrc rd,imm1or2 */ -{ -#ifdef NICENAMES -"rrc rd,imm1or2",16,6, -0x3c, -#endif -"rrc",OPC_rrc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,307}, - - -/* 1011 0010 dddd 11I0 *** rrcb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rrcb rbd,imm1or2",8,9, -0x10, -#endif -"rrcb",OPC_rrcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,308}, - - -/* 1011 1100 aaaa bbbb *** rrdb rbb,rba */ -{ -#ifdef NICENAMES -"rrdb rbb,rba",8,9, -0x10, -#endif -"rrdb",OPC_rrdb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+0xc,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,309}, - - -/* 0011 0110 imm8 *** rsvd36 */ -{ -#ifdef NICENAMES -"rsvd36",8,10, -0x00, -#endif -"rsvd36",OPC_rsvd36,0,{0}, - {CLASS_BIT+3,CLASS_BIT+6,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,310}, - - -/* 0011 1000 imm8 *** rsvd38 */ -{ -#ifdef NICENAMES -"rsvd38",8,10, -0x00, -#endif -"rsvd38",OPC_rsvd38,0,{0}, - {CLASS_BIT+3,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,311}, - - -/* 0111 1000 imm8 *** rsvd78 */ -{ -#ifdef NICENAMES -"rsvd78",8,10, -0x00, -#endif -"rsvd78",OPC_rsvd78,0,{0}, - {CLASS_BIT+7,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,312}, - - -/* 0111 1110 imm8 *** rsvd7e */ -{ -#ifdef NICENAMES -"rsvd7e",8,10, -0x00, -#endif -"rsvd7e",OPC_rsvd7e,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,313}, - - -/* 1001 1101 imm8 *** rsvd9d */ -{ -#ifdef NICENAMES -"rsvd9d",8,10, -0x00, -#endif -"rsvd9d",OPC_rsvd9d,0,{0}, - {CLASS_BIT+9,CLASS_BIT+0xd,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,314}, - - -/* 1001 1111 imm8 *** rsvd9f */ -{ -#ifdef NICENAMES -"rsvd9f",8,10, -0x00, -#endif -"rsvd9f",OPC_rsvd9f,0,{0}, - {CLASS_BIT+9,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,315}, - - -/* 1011 1001 imm8 *** rsvdb9 */ -{ -#ifdef NICENAMES -"rsvdb9",8,10, -0x00, -#endif -"rsvdb9",OPC_rsvdb9,0,{0}, - {CLASS_BIT+0xb,CLASS_BIT+9,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,316}, - - -/* 1011 1111 imm8 *** rsvdbf */ -{ -#ifdef NICENAMES -"rsvdbf",8,10, -0x00, -#endif -"rsvdbf",OPC_rsvdbf,0,{0}, - {CLASS_BIT+0xb,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,317}, - - -/* 1011 0111 ssss dddd *** sbc rd,rs */ -{ -#ifdef NICENAMES -"sbc rd,rs",16,5, -0x3c, -#endif -"sbc",OPC_sbc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,318}, - - -/* 1011 0110 ssss dddd *** sbcb rbd,rbs */ -{ -#ifdef NICENAMES -"sbcb rbd,rbs",8,5, -0x3f, -#endif -"sbcb",OPC_sbcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,319}, - - -/* 0111 1111 imm8 *** sc imm8 */ -{ -#ifdef NICENAMES -"sc imm8",8,33, -0x3f, -#endif -"sc",OPC_sc,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+7,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,320}, - - -/* 1011 0011 dddd 1011 0000 ssss 0000 0000 *** sda rd,rs */ -{ -#ifdef NICENAMES -"sda rd,rs",16,15, -0x3c, -#endif -"sda",OPC_sda,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,321}, - - -/* 1011 0010 dddd 1011 0000 ssss 0000 0000 *** sdab rbd,rs */ -{ -#ifdef NICENAMES -"sdab rbd,rs",8,15, -0x3c, -#endif -"sdab",OPC_sdab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,322}, - - -/* 1011 0011 dddd 1111 0000 ssss 0000 0000 *** sdal rrd,rs */ -{ -#ifdef NICENAMES -"sdal rrd,rs",32,15, -0x3c, -#endif -"sdal",OPC_sdal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,323}, - - -/* 1011 0011 dddd 0011 0000 ssss 0000 0000 *** sdl rd,rs */ -{ -#ifdef NICENAMES -"sdl rd,rs",16,15, -0x38, -#endif -"sdl",OPC_sdl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,324}, - - -/* 1011 0010 dddd 0011 0000 ssss 0000 0000 *** sdlb rbd,rs */ -{ -#ifdef NICENAMES -"sdlb rbd,rs",8,15, -0x38, -#endif -"sdlb",OPC_sdlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,325}, - - -/* 1011 0011 dddd 0111 0000 ssss 0000 0000 *** sdll rrd,rs */ -{ -#ifdef NICENAMES -"sdll rrd,rs",32,15, -0x38, -#endif -"sdll",OPC_sdll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,326}, - - -/* 0010 0101 ddN0 imm4 *** set @rd,imm4 */ -{ -#ifdef NICENAMES -"set @rd,imm4",16,11, -0x00, -#endif -"set",OPC_set,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,327}, - - -/* 0110 0101 ddN0 imm4 address_dst *** set address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"set address_dst(rd),imm4",16,14, -0x00, -#endif -"set",OPC_set,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,328}, - - -/* 0110 0101 0000 imm4 address_dst *** set address_dst,imm4 */ -{ -#ifdef NICENAMES -"set address_dst,imm4",16,13, -0x00, -#endif -"set",OPC_set,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,329}, - - -/* 1010 0101 dddd imm4 *** set rd,imm4 */ -{ -#ifdef NICENAMES -"set rd,imm4",16,4, -0x00, -#endif -"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,330}, - - -/* 0010 0101 0000 ssss 0000 dddd 0000 0000 *** set rd,rs */ -{ -#ifdef NICENAMES -"set rd,rs",16,10, -0x00, -#endif -"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,331}, - - -/* 0010 0100 ddN0 imm4 *** setb @rd,imm4 */ -{ -#ifdef NICENAMES -"setb @rd,imm4",8,11, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,332}, - - -/* 0110 0100 ddN0 imm4 address_dst *** setb address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"setb address_dst(rd),imm4",8,14, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,333}, - - -/* 0110 0100 0000 imm4 address_dst *** setb address_dst,imm4 */ -{ -#ifdef NICENAMES -"setb address_dst,imm4",8,13, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,334}, - - -/* 1010 0100 dddd imm4 *** setb rbd,imm4 */ -{ -#ifdef NICENAMES -"setb rbd,imm4",8,4, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,335}, - - -/* 0010 0100 0000 ssss 0000 dddd 0000 0000 *** setb rbd,rs */ -{ -#ifdef NICENAMES -"setb rbd,rs",8,10, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,336}, - - -/* 1000 1101 flags 0001 *** setflg flags */ -{ -#ifdef NICENAMES -"setflg flags",16,7, -0x3c, -#endif -"setflg",OPC_setflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+1,0,0,0,0,0,},1,2,337}, - - -/* 0011 1010 dddd 0101 imm16 *** sinb rbd,imm16 */ -{ -#ifdef NICENAMES -"sinb rbd,imm16",8,0, -0x00, -#endif -"sinb",OPC_sinb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,338}, - - -/* 0011 1011 dddd 0101 imm16 *** sinb rd,imm16 */ -{ -#ifdef NICENAMES -"sinb rd,imm16",8,0, -0x00, -#endif -"sinb",OPC_sinb,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,339}, - - -/* 0011 1011 ssN0 1000 0001 aaaa ddN0 1000 *** sind @rd,@rs,ra */ -{ -#ifdef NICENAMES -"sind @rd,@rs,ra",16,0, -0x00, -#endif -"sind",OPC_sind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,340}, - - -/* 0011 1010 ssN0 1000 0001 aaaa ddN0 1000 *** sindb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"sindb @rd,@rs,rba",8,0, -0x00, -#endif -"sindb",OPC_sindb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,341}, - - -/* 0011 1010 ssN0 0001 0000 aaaa ddN0 1000 *** sinib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"sinib @rd,@rs,ra",8,0, -0x00, -#endif -"sinib",OPC_sinib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,342}, - - -/* 0011 1010 ssN0 0001 0000 aaaa ddN0 0000 *** sinibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"sinibr @rd,@rs,ra",16,0, -0x00, -#endif -"sinibr",OPC_sinibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,343}, - - -/* 1011 0011 dddd 1001 0000 0000 imm8 *** sla rd,imm8 */ -{ -#ifdef NICENAMES -"sla rd,imm8",16,13, -0x3c, -#endif -"sla",OPC_sla,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,344}, - - -/* 1011 0010 dddd 1001 0000 0000 imm8 *** slab rbd,imm8 */ -{ -#ifdef NICENAMES -"slab rbd,imm8",8,13, -0x3c, -#endif -"slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,345}, - - -/* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */ -{ -#ifdef NICENAMES -"slal rrd,imm8",32,13, -0x3c, -#endif -"slal",OPC_slal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,346}, - - -/* 1011 0011 dddd 0001 0000 0000 imm8 *** sll rd,imm8 */ -{ -#ifdef NICENAMES -"sll rd,imm8",16,13, -0x38, -#endif -"sll",OPC_sll,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,347}, - - -/* 1011 0010 dddd 0001 0000 0000 imm8 *** sllb rbd,imm8 */ -{ -#ifdef NICENAMES -"sllb rbd,imm8",8,13, -0x38, -#endif -"sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,348}, - - -/* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */ -{ -#ifdef NICENAMES -"slll rrd,imm8",32,13, -0x38, -#endif -"slll",OPC_slll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,349}, - - -/* 0011 1011 ssss 0111 imm16 *** sout imm16,rs */ -{ -#ifdef NICENAMES -"sout imm16,rs",16,0, -0x00, -#endif -"sout",OPC_sout,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,350}, - - -/* 0011 1010 ssss 0111 imm16 *** soutb imm16,rbs */ -{ -#ifdef NICENAMES -"soutb imm16,rbs",8,0, -0x00, -#endif -"soutb",OPC_soutb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,351}, - - -/* 0011 1011 ssN0 1011 0000 aaaa ddN0 1000 *** soutd @rd,@rs,ra */ -{ -#ifdef NICENAMES -"soutd @rd,@rs,ra",16,0, -0x00, -#endif -"soutd",OPC_soutd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,352}, - - -/* 0011 1010 ssN0 1011 0000 aaaa ddN0 1000 *** soutdb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"soutdb @rd,@rs,rba",8,0, -0x00, -#endif -"soutdb",OPC_soutdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,353}, - - -/* 0011 1010 ssN0 0011 0000 aaaa ddN0 1000 *** soutib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"soutib @rd,@rs,ra",8,0, -0x00, -#endif -"soutib",OPC_soutib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,354}, - - -/* 0011 1010 ssN0 0011 0000 aaaa ddN0 0000 *** soutibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"soutibr @rd,@rs,ra",16,0, -0x00, -#endif -"soutibr",OPC_soutibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,355}, - - -/* 1011 0011 dddd 1001 1111 1111 nim8 *** sra rd,imm8 */ -{ -#ifdef NICENAMES -"sra rd,imm8",16,13, -0x3c, -#endif -"sra",OPC_sra,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,356}, - - -/* 1011 0010 dddd 1001 0000 0000 nim8 *** srab rbd,imm8 */ -{ -#ifdef NICENAMES -"srab rbd,imm8",8,13, -0x3c, -#endif -"srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_NIM8),0,0,},2,4,357}, - - -/* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */ -{ -#ifdef NICENAMES -"sral rrd,imm8",32,13, -0x3c, -#endif -"sral",OPC_sral,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,358}, - - -/* 1011 0011 dddd 0001 1111 1111 nim8 *** srl rd,imm8 */ -{ -#ifdef NICENAMES -"srl rd,imm8",16,13, -0x3c, -#endif -"srl",OPC_srl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,359}, - - -/* 1011 0010 dddd 0001 0000 0000 nim8 *** srlb rbd,imm8 */ -{ -#ifdef NICENAMES -"srlb rbd,imm8",8,13, -0x3c, -#endif -"srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_NIM8),0,0,},2,4,360}, - - -/* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */ -{ -#ifdef NICENAMES -"srll rrd,imm8",32,13, -0x3c, -#endif -"srll",OPC_srll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,361}, - - -/* 0000 0011 ssN0 dddd *** sub rd,@rs */ -{ -#ifdef NICENAMES -"sub rd,@rs",16,7, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,362}, - - -/* 0100 0011 0000 dddd address_src *** sub rd,address_src */ -{ -#ifdef NICENAMES -"sub rd,address_src",16,9, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,363}, - - -/* 0100 0011 ssN0 dddd address_src *** sub rd,address_src(rs) */ -{ -#ifdef NICENAMES -"sub rd,address_src(rs)",16,10, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,364}, - - -/* 0000 0011 0000 dddd imm16 *** sub rd,imm16 */ -{ -#ifdef NICENAMES -"sub rd,imm16",16,7, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,365}, - - -/* 1000 0011 ssss dddd *** sub rd,rs */ -{ -#ifdef NICENAMES -"sub rd,rs",16,4, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,366}, - - -/* 0000 0010 ssN0 dddd *** subb rbd,@rs */ -{ -#ifdef NICENAMES -"subb rbd,@rs",8,7, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,367}, - - -/* 0100 0010 0000 dddd address_src *** subb rbd,address_src */ -{ -#ifdef NICENAMES -"subb rbd,address_src",8,9, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,368}, - - -/* 0100 0010 ssN0 dddd address_src *** subb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"subb rbd,address_src(rs)",8,10, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,369}, - - -/* 0000 0010 0000 dddd imm8 imm8 *** subb rbd,imm8 */ -{ -#ifdef NICENAMES -"subb rbd,imm8",8,7, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,370}, - - -/* 1000 0010 ssss dddd *** subb rbd,rbs */ -{ -#ifdef NICENAMES -"subb rbd,rbs",8,4, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,371}, - - -/* 0001 0010 ssN0 dddd *** subl rrd,@rs */ -{ -#ifdef NICENAMES -"subl rrd,@rs",32,14, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,372}, - - -/* 0101 0010 0000 dddd address_src *** subl rrd,address_src */ -{ -#ifdef NICENAMES -"subl rrd,address_src",32,15, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,373}, - - -/* 0101 0010 ssN0 dddd address_src *** subl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"subl rrd,address_src(rs)",32,16, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,374}, - - -/* 0001 0010 0000 dddd imm32 *** subl rrd,imm32 */ -{ -#ifdef NICENAMES -"subl rrd,imm32",32,14, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,375}, - - -/* 1001 0010 ssss dddd *** subl rrd,rrs */ -{ -#ifdef NICENAMES -"subl rrd,rrs",32,8, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,376}, - - -/* 1010 1111 dddd cccc *** tcc cc,rd */ -{ -#ifdef NICENAMES -"tcc cc,rd",16,5, -0x00, -#endif -"tcc",OPC_tcc,0,{CLASS_CC,CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+0xa,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,377}, - - -/* 1010 1110 dddd cccc *** tccb cc,rbd */ -{ -#ifdef NICENAMES -"tccb cc,rbd",8,5, -0x00, -#endif -"tccb",OPC_tccb,0,{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+0xa,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,378}, - - -/* 0000 1101 ddN0 0100 *** test @rd */ -{ -#ifdef NICENAMES -"test @rd",16,8, -0x18, -#endif -"test",OPC_test,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,379}, - - -/* 0100 1101 0000 0100 address_dst *** test address_dst */ -{ -#ifdef NICENAMES -"test address_dst",16,11, -0x00, -#endif -"test",OPC_test,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,380}, - - -/* 0100 1101 ddN0 0100 address_dst *** test address_dst(rd) */ -{ -#ifdef NICENAMES -"test address_dst(rd)",16,12, -0x00, -#endif -"test",OPC_test,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,381}, - - -/* 1000 1101 dddd 0100 *** test rd */ -{ -#ifdef NICENAMES -"test rd",16,7, -0x00, -#endif -"test",OPC_test,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,382}, - - -/* 0000 1100 ddN0 0100 *** testb @rd */ -{ -#ifdef NICENAMES -"testb @rd",8,8, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,383}, - - -/* 0100 1100 0000 0100 address_dst *** testb address_dst */ -{ -#ifdef NICENAMES -"testb address_dst",8,11, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,384}, - - -/* 0100 1100 ddN0 0100 address_dst *** testb address_dst(rd) */ -{ -#ifdef NICENAMES -"testb address_dst(rd)",8,12, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,385}, - - -/* 1000 1100 dddd 0100 *** testb rbd */ -{ -#ifdef NICENAMES -"testb rbd",8,7, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,386}, - - -/* 0001 1100 ddN0 1000 *** testl @rd */ -{ -#ifdef NICENAMES -"testl @rd",32,13, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,387}, - - -/* 0101 1100 0000 1000 address_dst *** testl address_dst */ -{ -#ifdef NICENAMES -"testl address_dst",32,16, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,388}, - - -/* 0101 1100 ddN0 1000 address_dst *** testl address_dst(rd) */ -{ -#ifdef NICENAMES -"testl address_dst(rd)",32,17, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,389}, - - -/* 1001 1100 dddd 1000 *** testl rrd */ -{ -#ifdef NICENAMES -"testl rrd",32,13, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+9,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,390}, - - -/* 1011 1000 ddN0 1000 0000 aaaa ssN0 0000 *** trdb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"trdb @rd,@rs,rba",8,25, -0x1c, -#endif -"trdb",OPC_trdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,391}, - - -/* 1011 1000 ddN0 1100 0000 aaaa ssN0 0000 *** trdrb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"trdrb @rd,@rs,rba",8,25, -0x1c, -#endif -"trdrb",OPC_trdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,392}, - - -/* 1011 1000 ddN0 0000 0000 rrrr ssN0 0000 *** trib @rd,@rs,rbr */ -{ -#ifdef NICENAMES -"trib @rd,@rs,rbr",8,25, -0x1c, -#endif -"trib",OPC_trib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,393}, - - -/* 1011 1000 ddN0 0100 0000 rrrr ssN0 0000 *** trirb @rd,@rs,rbr */ -{ -#ifdef NICENAMES -"trirb @rd,@rs,rbr",8,25, -0x1c, -#endif -"trirb",OPC_trirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,394}, - - -/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtdb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtdb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtdb",OPC_trtdb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,395}, - - -/* 1011 1000 aaN0 1110 0000 rrrr bbN0 1110 *** trtdrb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtdrb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtdrb",OPC_trtdrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,396}, - - -/* 1011 1000 aaN0 0010 0000 rrrr bbN0 0000 *** trtib @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtib @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtib",OPC_trtib,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,397}, - - -/* 1011 1000 aaN0 0110 0000 rrrr bbN0 1110 *** trtirb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtirb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtirb",OPC_trtirb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,398}, - - -/* 0000 1101 ddN0 0110 *** tset @rd */ -{ -#ifdef NICENAMES -"tset @rd",16,11, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,399}, - - -/* 0100 1101 0000 0110 address_dst *** tset address_dst */ -{ -#ifdef NICENAMES -"tset address_dst",16,14, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,400}, - - -/* 0100 1101 ddN0 0110 address_dst *** tset address_dst(rd) */ -{ -#ifdef NICENAMES -"tset address_dst(rd)",16,15, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,401}, - - -/* 1000 1101 dddd 0110 *** tset rd */ -{ -#ifdef NICENAMES -"tset rd",16,7, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,402}, - - -/* 0000 1100 ddN0 0110 *** tsetb @rd */ -{ -#ifdef NICENAMES -"tsetb @rd",8,11, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,403}, - - -/* 0100 1100 0000 0110 address_dst *** tsetb address_dst */ -{ -#ifdef NICENAMES -"tsetb address_dst",8,14, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,404}, - - -/* 0100 1100 ddN0 0110 address_dst *** tsetb address_dst(rd) */ -{ -#ifdef NICENAMES -"tsetb address_dst(rd)",8,15, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,405}, - - -/* 1000 1100 dddd 0110 *** tsetb rbd */ -{ -#ifdef NICENAMES -"tsetb rbd",8,7, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,406}, - - -/* 0000 1001 ssN0 dddd *** xor rd,@rs */ -{ -#ifdef NICENAMES -"xor rd,@rs",16,7, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,407}, - - -/* 0100 1001 0000 dddd address_src *** xor rd,address_src */ -{ -#ifdef NICENAMES -"xor rd,address_src",16,9, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,408}, - - -/* 0100 1001 ssN0 dddd address_src *** xor rd,address_src(rs) */ -{ -#ifdef NICENAMES -"xor rd,address_src(rs)",16,10, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,409}, - - -/* 0000 1001 0000 dddd imm16 *** xor rd,imm16 */ -{ -#ifdef NICENAMES -"xor rd,imm16",16,7, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,410}, - - -/* 1000 1001 ssss dddd *** xor rd,rs */ -{ -#ifdef NICENAMES -"xor rd,rs",16,4, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,411}, - - -/* 0000 1000 ssN0 dddd *** xorb rbd,@rs */ -{ -#ifdef NICENAMES -"xorb rbd,@rs",8,7, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,412}, - - -/* 0100 1000 0000 dddd address_src *** xorb rbd,address_src */ -{ -#ifdef NICENAMES -"xorb rbd,address_src",8,9, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,413}, - - -/* 0100 1000 ssN0 dddd address_src *** xorb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"xorb rbd,address_src(rs)",8,10, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,414}, - - -/* 0000 1000 0000 dddd imm8 imm8 *** xorb rbd,imm8 */ -{ -#ifdef NICENAMES -"xorb rbd,imm8",8,7, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,415}, - - -/* 1000 1000 ssss dddd *** xorb rbd,rbs */ -{ -#ifdef NICENAMES -"xorb rbd,rbs",8,4, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,416}, - - -/* 1000 1000 ssss dddd *** xorb rbd,rbs */ -{ -#ifdef NICENAMES -"xorb rbd,rbs",8,4, -0x01, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,417}, -0,0}; -#endif diff --git a/contrib/binutils/opcodes/z8kgen.c b/contrib/binutils/opcodes/z8kgen.c deleted file mode 100644 index 44df0b2ec0d42..0000000000000 --- a/contrib/binutils/opcodes/z8kgen.c +++ /dev/null @@ -1,1312 +0,0 @@ -/* -This file is part of GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -/* This program generates z8k-opc.h */ - -#include "sysdep.h" - -#define BYTE_INFO_LEN 10 - -struct op -{ - char *flags; - int cycles; - char type; - char *bits; - char *name; - char *flavor; -}; - -#define iswhite(x) ((x) == ' ' || (x) == '\t') -struct op opt[] = -{ - "------", 10, 8, "0000 1110 imm8", "ext0e imm8", 0, - "------", 10, 8, "0000 1111 imm8", "ext0f imm8", 0, - "------", 10, 8, "1000 1110 imm8", "ext8e imm8", 0, - "------", 10, 8, "1000 1111 imm8", "ext8f imm8", 0, - - "------", 10, 8, "0011 0110 imm8", "rsvd36", 0, - "------", 10, 8, "0011 1000 imm8", "rsvd38", 0, - "------", 10, 8, "0111 1000 imm8", "rsvd78", 0, - "------", 10, 8, "0111 1110 imm8", "rsvd7e", 0, - - "------", 10, 8, "1001 1101 imm8", "rsvd9d", 0, - "------", 10, 8, "1001 1111 imm8", "rsvd9f", 0, - - "------", 10, 8, "1011 1001 imm8", "rsvdb9", 0, - "------", 10, 8, "1011 1111 imm8", "rsvdbf", 0, - - "---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 1000", "ldd @rs,@rd,rr", 0, - "---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 0000", "lddr @rs,@rd,rr", 0, - "---V--", 11, 8, "1011 1011 ssN0 1001 0000 rrrr ddN0 0000", "lddrb @rs,@rd,rr", 0, - "---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 0000", "ldir @rd,@rs,rr", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0000 0000 rrrr dddd cccc", "cpi rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0100 0000 rrrr dddd cccc", "cpir rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1100 0000 rrrr dddd cccc", "cpdr rd,@rs,rr,cc", 0, - "---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 1000", "ldi @rd,@rs,rr", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1000 0000 rrrr dddd cccc", "cpd rd,@rs,rr,cc", 0, - "---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 0000", "ldirb @rd,@rs,rr", 0, - "---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 1000", "lddb @rs,@rd,rr", 0, - "---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 1000", "ldib @rd,@rs,rr", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1000 0000 rrrr dddd cccc", "cpdb rbd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1100 0000 rrrr dddd cccc", "cpdrb rbd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0000 0000 rrrr dddd cccc", "cpib rbd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0100 0000 rrrr dddd cccc", "cpirb rbd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1010 0000 rrrr ddN0 cccc", "cpsd @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1010 0000 rrrr ddN0 cccc", "cpsdb @rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdr @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdrb @rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0010 0000 rrrr ddN0 cccc", "cpsi @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0010 0000 rrrr ddN0 cccc", "cpsib @rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0110 0000 rrrr ddN0 cccc", "cpsir @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0110 0000 rrrr ddN0 cccc", "cpsirb @rd,@rs,rr,cc", 0, - - "------", 2, 8, "0011 0110 0000 0000", "bpt", 0, - "CZSV--", 5, 16, "1011 0101 ssss dddd", "adc rd,rs", 0, - "CZSVDH", 5, 8, "1011 0100 ssss dddd", "adcb rbd,rbs", 0, - "CZSV--", 7, 16, "0000 0001 ssN0 dddd", "add rd,@rs", 0, -"CZSV--", 9, 16, "0100 0001 0000 dddd address_src", "add rd,address_src", 0, - "CZSV--", 10, 16, "0100 0001 ssN0 dddd address_src", "add rd,address_src(rs)", 0, - "CZSV--", 7, 16, "0000 0001 0000 dddd imm16", "add rd,imm16", 0, - "CZSV--", 4, 16, "1000 0001 ssss dddd", "add rd,rs", 0, - "CZSVDH", 7, 8, "0000 0000 ssN0 dddd", "addb rbd,@rs", 0, -"CZSVDH", 9, 8, "0100 0000 0000 dddd address_src", "addb rbd,address_src", 0, - "CZSVDH", 10, 8, "0100 0000 ssN0 dddd address_src", "addb rbd,address_src(rs)", 0, - "CZSVDH", 7, 8, "0000 0000 0000 dddd imm8 imm8", "addb rbd,imm8", 0, - "CZSVDH", 4, 8, "1000 0000 ssss dddd", "addb rbd,rbs", 0, - "CZSV--", 14, 32, "0001 0110 ssN0 dddd", "addl rrd,@rs", 0, - "CZSV--", 15, 32, "0101 0110 0000 dddd address_src", "addl rrd,address_src", 0, - "CZSV--", 16, 32, "0101 0110 ssN0 dddd address_src", "addl rrd,address_src(rs)", 0, - "CZSV--", 14, 32, "0001 0110 0000 dddd imm32", "addl rrd,imm32", 0, - "CZSV--", 8, 32, "1001 0110 ssss dddd", "addl rrd,rrs", 0, - - "-ZS---", 7, 16, "0000 0111 ssN0 dddd", "and rd,@rs", 0, -"-ZS---", 9, 16, "0100 0111 0000 dddd address_src", "and rd,address_src", 0, - "-ZS---", 10, 16, "0100 0111 ssN0 dddd address_src", "and rd,address_src(rs)", 0, - "-ZS---", 7, 16, "0000 0111 0000 dddd imm16", "and rd,imm16", 0, - "-ZS---", 4, 16, "1000 0111 ssss dddd", "and rd,rs", 0, - "-ZSP--", 7, 8, "0000 0110 ssN0 dddd", "andb rbd,@rs", 0, -"-ZSP--", 9, 8, "0100 0110 0000 dddd address_src", "andb rbd,address_src", 0, - "-ZSP--", 10, 8, "0100 0110 ssN0 dddd address_src", "andb rbd,address_src(rs)", 0, - "-ZSP--", 7, 8, "0000 0110 0000 dddd imm8 imm8", "andb rbd,imm8", 0, - "-ZSP--", 4, 8, "1000 0110 ssss dddd", "andb rbd,rbs", 0, - - "-Z----", 8, 16, "0010 0111 ddN0 imm4", "bit @rd,imm4", 0, - "-Z----", 11, 16, "0110 0111 ddN0 imm4 address_dst", "bit address_dst(rd),imm4", 0, - "-Z----", 10, 16, "0110 0111 0000 imm4 address_dst", "bit address_dst,imm4", 0, - "-Z----", 4, 16, "1010 0111 dddd imm4", "bit rd,imm4", 0, -"-Z----", 10, 16, "0010 0111 0000 ssss 0000 dddd 0000 0000", "bit rd,rs", 0, - - "-Z----", 8, 8, "0010 0110 ddN0 imm4", "bitb @rd,imm4", 0, - "-Z----", 11, 8, "0110 0110 ddN0 imm4 address_dst", "bitb address_dst(rd),imm4", 0, - "-Z----", 10, 8, "0110 0110 0000 imm4 address_dst", "bitb address_dst,imm4", 0, - "-Z----", 4, 8, "1010 0110 dddd imm4", "bitb rbd,imm4", 0, -"-Z----", 10, 8, "0010 0110 0000 ssss 0000 dddd 0000 0000", "bitb rbd,rs", 0, - - "------", 10, 32, "0001 1111 ddN0 0000", "call @rd", 0, - "------", 12, 32, "0101 1111 0000 0000 address_dst", "call address_dst", 0, - "------", 13, 32, "0101 1111 ddN0 0000 address_dst", "call address_dst(rd)", 0, - "------", 10, 16, "1101 disp12", "calr disp12", 0, - - "------", 8, 16, "0000 1101 ddN0 1000", "clr @rd", 0, - "------", 11, 16, "0100 1101 0000 1000 address_dst", "clr address_dst", 0, - "------", 12, 16, "0100 1101 ddN0 1000 address_dst", "clr address_dst(rd)", 0, - "------", 7, 16, "1000 1101 dddd 1000", "clr rd", 0, - "------", 8, 8, "0000 1100 ddN0 1000", "clrb @rd", 0, - "------", 11, 8, "0100 1100 0000 1000 address_dst", "clrb address_dst", 0, - "------", 12, 8, "0100 1100 ddN0 1000 address_dst", "clrb address_dst(rd)", 0, - "------", 7, 8, "1000 1100 dddd 1000", "clrb rbd", 0, - "-ZS---", 12, 16, "0000 1101 ddN0 0000", "com @rd", 0, - "-ZS---", 15, 16, "0100 1101 0000 0000 address_dst", "com address_dst", 0, - "-ZS---", 16, 16, "0100 1101 ddN0 0000 address_dst", "com address_dst(rd)", 0, - "-ZS---", 7, 16, "1000 1101 dddd 0000", "com rd", 0, - "-ZSP--", 12, 8, "0000 1100 ddN0 0000", "comb @rd", 0, - "-ZSP--", 15, 8, "0100 1100 0000 0000 address_dst", "comb address_dst", 0, - "-ZSP--", 16, 8, "0100 1100 ddN0 0000 address_dst", "comb address_dst(rd)", 0, - "-ZSP--", 7, 8, "1000 1100 dddd 0000", "comb rbd", 0, - "CZSP--", 7, 16, "1000 1101 imm4 0101", "comflg flags", 0, - - "CZSV--", 11, 16, "0000 1101 ddN0 0001 imm16", "cp @rd,imm16", 0, - "CZSV--", 15, 16, "0100 1101 ddN0 0001 address_dst imm16", "cp address_dst(rd),imm16", 0, - "CZSV--", 14, 16, "0100 1101 0000 0001 address_dst imm16", "cp address_dst,imm16", 0, - - "CZSV--", 7, 16, "0000 1011 ssN0 dddd", "cp rd,@rs", 0, - "CZSV--", 9, 16, "0100 1011 0000 dddd address_src", "cp rd,address_src", 0, - "CZSV--", 10, 16, "0100 1011 ssN0 dddd address_src", "cp rd,address_src(rs)", 0, - "CZSV--", 7, 16, "0000 1011 0000 dddd imm16", "cp rd,imm16", 0, - "CZSV--", 4, 16, "1000 1011 ssss dddd", "cp rd,rs", 0, - - "CZSV--", 11, 8, "0000 1100 ddN0 0001 imm8 imm8", "cpb @rd,imm8", 0, - "CZSV--", 15, 8, "0100 1100 ddN0 0001 address_dst imm8 imm8", "cpb address_dst(rd),imm8", 0, - "CZSV--", 14, 8, "0100 1100 0000 0001 address_dst imm8 imm8", "cpb address_dst,imm8", 0, - "CZSV--", 7, 8, "0000 1010 ssN0 dddd", "cpb rbd,@rs", 0, -"CZSV--", 9, 8, "0100 1010 0000 dddd address_src", "cpb rbd,address_src", 0, - "CZSV--", 10, 8, "0100 1010 ssN0 dddd address_src", "cpb rbd,address_src(rs)", 0, - "CZSV--", 7, 8, "0000 1010 0000 dddd imm8 imm8", "cpb rbd,imm8", 0, - "CZSV--", 4, 8, "1000 1010 ssss dddd", "cpb rbd,rbs", 0, - - "CZSV--", 14, 32, "0001 0000 ssN0 dddd", "cpl rrd,@rs", 0, - "CZSV--", 15, 32, "0101 0000 0000 dddd address_src", "cpl rrd,address_src", 0, - "CZSV--", 16, 32, "0101 0000 ssN0 dddd address_src", "cpl rrd,address_src(rs)", 0, - "CZSV--", 14, 32, "0001 0000 0000 dddd imm32", "cpl rrd,imm32", 0, - "CZSV--", 8, 32, "1001 0000 ssss dddd", "cpl rrd,rrs", 0, - - "CZS---", 5, 8, "1011 0000 dddd 0000", "dab rbd", 0, - "------", 11, 16, "1111 dddd 1disp7", "dbjnz rbd,disp7", 0, - "-ZSV--", 11, 16, "0010 1011 ddN0 imm4m1", "dec @rd,imm4m1", 0, - "-ZSV--", 14, 16, "0110 1011 ddN0 imm4m1 address_dst", "dec address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 16, "0110 1011 0000 imm4m1 address_dst", "dec address_dst,imm4m1", 0, - "-ZSV--", 4, 16, "1010 1011 dddd imm4m1", "dec rd,imm4m1", 0, - "-ZSV--", 11, 8, "0010 1010 ddN0 imm4m1", "decb @rd,imm4m1", 0, - "-ZSV--", 14, 8, "0110 1010 ddN0 imm4m1 address_dst", "decb address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 8, "0110 1010 0000 imm4m1 address_dst", "decb address_dst,imm4m1", 0, - "-ZSV--", 4, 8, "1010 1010 dddd imm4m1", "decb rbd,imm4m1", 0, - - "------", 7, 16, "0111 1100 0000 00ii", "di i2", 0, - "CZSV--", 107, 16, "0001 1011 ssN0 dddd", "div rrd,@rs", 0, - "CZSV--", 107, 16, "0101 1011 0000 dddd address_src", "div rrd,address_src", 0, - "CZSV--", 107, 16, "0101 1011 ssN0 dddd address_src", "div rrd,address_src(rs)", 0, - "CZSV--", 107, 16, "0001 1011 0000 dddd imm16", "div rrd,imm16", 0, - "CZSV--", 107, 16, "1001 1011 ssss dddd", "div rrd,rs", 0, - "CZSV--", 744, 32, "0001 1010 ssN0 dddd", "divl rqd,@rs", 0, - "CZSV--", 745, 32, "0101 1010 0000 dddd address_src", "divl rqd,address_src", 0, - "CZSV--", 746, 32, "0101 1010 ssN0 dddd address_src", "divl rqd,address_src(rs)", 0, - "CZSV--", 744, 32, "0001 1010 0000 dddd imm32", "divl rqd,imm32", 0, - "CZSV--", 744, 32, "1001 1010 ssss dddd", "divl rqd,rrs", 0, - - "------", 11, 16, "1111 dddd 0disp7", "djnz rd,disp7", 0, - "------", 7, 16, "0111 1100 0000 01ii", "ei i2", 0, - "------", 6, 16, "1010 1101 ssss dddd", "ex rd,rs", 0, - "------", 12, 16, "0010 1101 ssN0 dddd", "ex rd,@rs", 0, -"------", 15, 16, "0110 1101 0000 dddd address_src", "ex rd,address_src", 0, - "------", 16, 16, "0110 1101 ssN0 dddd address_src", "ex rd,address_src(rs)", 0, - - "------", 12, 8, "0010 1100 ssN0 dddd", "exb rbd,@rs", 0, -"------", 15, 8, "0110 1100 0000 dddd address_src", "exb rbd,address_src", 0, - "------", 16, 8, "0110 1100 ssN0 dddd address_src", "exb rbd,address_src(rs)", 0, - "------", 6, 8, "1010 1100 ssss dddd", "exb rbd,rbs", 0, - - "------", 11, 16, "1011 0001 dddd 1010", "exts rrd", 0, - "------", 11, 8, "1011 0001 dddd 0000", "extsb rd", 0, - "------", 11, 32, "1011 0001 dddd 0111", "extsl rqd", 0, - - "------", 8, 16, "0111 1010 0000 0000", "halt", 0, - "------", 10, 16, "0011 1101 ssN0 dddd", "in rd,@rs", 0, - "------", 12, 16, "0011 1101 dddd 0100 imm16", "in rd,imm16", 0, - "------", 12, 8, "0011 1100 ssN0 dddd", "inb rbd,@rs", 0, - "------", 10, 8, "0011 1100 dddd 0100 imm16", "inb rbd,imm16", 0, - "-ZSV--", 11, 16, "0010 1001 ddN0 imm4m1", "inc @rd,imm4m1", 0, - "-ZSV--", 14, 16, "0110 1001 ddN0 imm4m1 address_dst", "inc address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 16, "0110 1001 0000 imm4m1 address_dst", "inc address_dst,imm4m1", 0, - "-ZSV--", 4, 16, "1010 1001 dddd imm4m1", "inc rd,imm4m1", 0, - "-ZSV--", 11, 8, "0010 1000 ddN0 imm4m1", "incb @rd,imm4m1", 0, - "-ZSV--", 14, 8, "0110 1000 ddN0 imm4m1 address_dst", "incb address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 8, "0110 1000 0000 imm4m1 address_dst", "incb address_dst,imm4m1", 0, - "-ZSV--", 4, 8, "1010 1000 dddd imm4m1", "incb rbd,imm4m1", 0, - "---V--", 21, 16, "0011 1011 ssN0 1000 0000 aaaa ddN0 1000", "ind @rd,@rs,ra", 0, - "---V--", 21, 8, "0011 1010 ssN0 1000 0000 aaaa ddN0 1000", "indb @rd,@rs,rba", 0, - "---V--", 21, 8, "0011 1100 ssN0 0000 0000 aaaa ddN0 1000", "inib @rd,@rs,ra", 0, - "---V--", 21, 16, "0011 1100 ssN0 0000 0000 aaaa ddN0 0000", "inibr @rd,@rs,ra", 0, - "CZSVDH", 13, 16, "0111 1011 0000 0000", "iret", 0, - "------", 10, 16, "0001 1110 ddN0 cccc", "jp cc,@rd", 0, - "------", 7, 16, "0101 1110 0000 cccc address_dst", "jp cc,address_dst", 0, - "------", 8, 16, "0101 1110 ddN0 cccc address_dst", "jp cc,address_dst(rd)", 0, - "------", 6, 16, "1110 cccc disp8", "jr cc,disp8", 0, - - "------", 7, 16, "0000 1101 ddN0 0101 imm16", "ld @rd,imm16", 0, - "------", 8, 16, "0010 1111 ddN0 ssss", "ld @rd,rs", 0, - "------", 15, 16, "0100 1101 ddN0 0101 address_dst imm16", "ld address_dst(rd),imm16", 0, - "------", 12, 16, "0110 1111 ddN0 ssss address_dst", "ld address_dst(rd),rs", 0, - "------", 14, 16, "0100 1101 0000 0101 address_dst imm16", "ld address_dst,imm16", 0, -"------", 11, 16, "0110 1111 0000 ssss address_dst", "ld address_dst,rs", 0, - "------", 14, 16, "0011 0011 ddN0 ssss imm16", "ld rd(imm16),rs", 0, - "------", 14, 16, "0111 0011 ddN0 ssss 0000 xxxx 0000 0000", "ld rd(rx),rs", 0, - "------", 7, 16, "0010 0001 ssN0 dddd", "ld rd,@rs", 0, - "------", 9, 16, "0110 0001 0000 dddd address_src", "ld rd,address_src", 0, - "------", 10, 16, "0110 0001 ssN0 dddd address_src", "ld rd,address_src(rs)", 0, - "------", 7, 16, "0010 0001 0000 dddd imm16", "ld rd,imm16", 0, - "------", 3, 16, "1010 0001 ssss dddd", "ld rd,rs", 0, - "------", 14, 16, "0011 0001 ssN0 dddd imm16", "ld rd,rs(imm16)", 0, - "------", 14, 16, "0111 0001 ssN0 dddd 0000 xxxx 0000 0000", "ld rd,rs(rx)", 0, - - "------", 7, 8, "0000 1100 ddN0 0101 imm8 imm8", "ldb @rd,imm8", 0, - "------", 8, 8, "0010 1110 ddN0 ssss", "ldb @rd,rbs", 0, - "------", 15, 8, "0100 1100 ddN0 0101 address_dst imm8 imm8", "ldb address_dst(rd),imm8", 0, - "------", 12, 8, "0100 1110 ddN0 ssN0 address_dst", "ldb address_dst(rd),rbs", 0, - "------", 14, 8, "0100 1100 0000 0101 address_dst imm8 imm8", "ldb address_dst,imm8", 0, -"------", 11, 8, "0110 1110 0000 ssss address_dst", "ldb address_dst,rbs", 0, - "------", 14, 8, "0011 0010 ddN0 ssss imm16", "ldb rd(imm16),rbs", 0, - "------", 14, 8, "0111 0010 ddN0 ssss 0000 xxxx 0000 0000", "ldb rd(rx),rbs", 0, - "------", 7, 8, "0010 0000 ssN0 dddd", "ldb rbd,@rs", 0, -"------", 9, 8, "0110 0000 0000 dddd address_src", "ldb rbd,address_src", 0, - "------", 10, 8, "0110 0000 ssN0 dddd address_src", "ldb rbd,address_src(rs)", 0, - "------", 5, 8, "1100 dddd imm8", "ldb rbd,imm8", 0, - "------", 3, 8, "1010 0000 ssss dddd", "ldb rbd,rbs", 0, - "------", 14, 8, "0011 0000 ssN0 dddd imm16", "ldb rbd,rs(imm16)", 0, - "------", 14, 8, "0111 0000 ssN0 dddd 0000 xxxx 0000 0000", "ldb rbd,rs(rx)", 0, - - "------", 11, 32, "0001 1101 ddN0 ssss", "ldl @rd,rrs", 0, - "------", 14, 32, "0101 1101 ddN0 ssss address_dst", "ldl address_dst(rd),rrs", 0, - "------", 15, 32, "0101 1101 0000 ssss address_dst", "ldl address_dst,rrs", 0, - "------", 17, 32, "0011 0111 ddN0 ssss imm16", "ldl rd(imm16),rrs", 0, - "------", 17, 32, "0111 0111 ddN0 ssss 0000 xxxx 0000 0000", "ldl rd(rx),rrs", 0, - "------", 11, 32, "0001 0100 ssN0 dddd", "ldl rrd,@rs", 0, - "------", 12, 32, "0101 0100 0000 dddd address_src", "ldl rrd,address_src", 0, - "------", 13, 32, "0101 0100 ssN0 dddd address_src", "ldl rrd,address_src(rs)", 0, - "------", 11, 32, "0001 0100 0000 dddd imm32", "ldl rrd,imm32", 0, - "------", 5, 32, "1001 0100 ssss dddd", "ldl rrd,rrs", 0, - "------", 17, 32, "0011 0101 ssN0 dddd imm16", "ldl rrd,rs(imm16)", 0, - "------", 17, 32, "0111 0101 ssN0 dddd 0000 xxxx 0000 0000", "ldl rrd,rs(rx)", 0, - - "------", 12, 16, "0111 0110 0000 dddd address_src", "lda prd,address_src", 0, - "------", 13, 16, "0111 0110 ssN0 dddd address_src", "lda prd,address_src(rs)", 0, - "------", 15, 16, "0011 0100 ssN0 dddd imm16", "lda prd,rs(imm16)", 0, - "------", 15, 16, "0111 0100 ssN0 dddd 0000 xxxx 0000 0000", "lda prd,rs(rx)", 0, - "------", 15, 16, "0011 0100 0000 dddd disp16", "ldar prd,disp16", 0, - "------", 7, 32, "0111 1101 ssss 1ccc", "ldctl ctrl,rs", 0, - "------", 7, 32, "0111 1101 dddd 0ccc", "ldctl rd,ctrl", 0, - - "------", 5, 16, "1011 1101 dddd imm4", "ldk rd,imm4", 0, - - "------", 11, 16, "0001 1100 ddN0 1001 0000 ssss 0000 nminus1", "ldm @rd,rs,n", 0, - "------", 15, 16, "0101 1100 ddN0 1001 0000 ssN0 0000 nminus1 address_dst", "ldm address_dst(rd),rs,n", 0, - "------", 14, 16, "0101 1100 0000 1001 0000 ssss 0000 nminus1 address_dst", "ldm address_dst,rs,n", 0, - "------", 11, 16, "0001 1100 ssN0 0001 0000 dddd 0000 nminus1", "ldm rd,@rs,n", 0, - "------", 15, 16, "0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address_src", "ldm rd,address_src(rs),n", 0, - "------", 14, 16, "0101 1100 0000 0001 0000 dddd 0000 nminus1 address_src", "ldm rd,address_src,n", 0, - - "CZSVDH", 12, 16, "0011 1001 ssN0 0000", "ldps @rs", 0, - "CZSVDH", 16, 16, "0111 1001 0000 0000 address_src", "ldps address_src", 0, - "CZSVDH", 17, 16, "0111 1001 ssN0 0000 address_src", "ldps address_src(rs)", 0, - - "------", 14, 16, "0011 0011 0000 ssss disp16", "ldr disp16,rs", 0, - "------", 14, 16, "0011 0001 0000 dddd disp16", "ldr rd,disp16", 0, - "------", 14, 8, "0011 0010 0000 ssss disp16", "ldrb disp16,rbs", 0, - "------", 14, 8, "0011 0000 0000 dddd disp16", "ldrb rbd,disp16", 0, - "------", 17, 32, "0011 0111 0000 ssss disp16", "ldrl disp16,rrs", 0, - "------", 17, 32, "0011 0101 0000 dddd disp16", "ldrl rrd,disp16", 0, - - "CZS---", 7, 16, "0111 1011 0000 1010", "mbit", 0, - "-ZS---", 12, 16, "0111 1011 dddd 1101", "mreq rd", 0, - "------", 5, 16, "0111 1011 0000 1001", "mres", 0, - "------", 5, 16, "0111 1011 0000 1000", "mset", 0, - - "CZSV--", 70, 16, "0001 1001 ssN0 dddd", "mult rrd,@rs", 0, - "CZSV--", 70, 16, "0101 1001 0000 dddd address_src", "mult rrd,address_src", 0, - "CZSV--", 70, 16, "0101 1001 ssN0 dddd address_src", "mult rrd,address_src(rs)", 0, - "CZSV--", 70, 16, "0001 1001 0000 dddd imm16", "mult rrd,imm16", 0, - "CZSV--", 70, 16, "1001 1001 ssss dddd", "mult rrd,rs", 0, - "CZSV--", 282, 32, "0001 1000 ssN0 dddd", "multl rqd,@rs", 0, - "CZSV--", 282, 32, "0101 1000 0000 dddd address_src", "multl rqd,address_src", 0, - "CZSV--", 282, 32, "0101 1000 ssN0 dddd address_src", "multl rqd,address_src(rs)", 0, - "CZSV--", 282, 32, "0001 1000 0000 dddd imm32", "multl rqd,imm32", 0, - "CZSV--", 282, 32, "1001 1000 ssss dddd", "multl rqd,rrs", 0, - "CZSV--", 12, 16, "0000 1101 ddN0 0010", "neg @rd", 0, - "CZSV--", 15, 16, "0100 1101 0000 0010 address_dst", "neg address_dst", 0, - "CZSV--", 16, 16, "0100 1101 ddN0 0010 address_dst", "neg address_dst(rd)", 0, - "CZSV--", 7, 16, "1000 1101 dddd 0010", "neg rd", 0, - "CZSV--", 12, 8, "0000 1100 ddN0 0010", "negb @rd", 0, - "CZSV--", 15, 8, "0100 1100 0000 0010 address_dst", "negb address_dst", 0, - "CZSV--", 16, 8, "0100 1100 ddN0 0010 address_dst", "negb address_dst(rd)", 0, - "CZSV--", 7, 8, "1000 1100 dddd 0010", "negb rbd", 0, - - "------", 7, 16, "1000 1101 0000 0111", "nop", 0, - - "CZS---", 7, 16, "0000 0101 ssN0 dddd", "or rd,@rs", 0, - "CZS---", 9, 16, "0100 0101 0000 dddd address_src", "or rd,address_src", 0, - "CZS---", 10, 16, "0100 0101 ssN0 dddd address_src", "or rd,address_src(rs)", 0, - "CZS---", 7, 16, "0000 0101 0000 dddd imm16", "or rd,imm16", 0, - "CZS---", 4, 16, "1000 0101 ssss dddd", "or rd,rs", 0, - - "CZSP--", 7, 8, "0000 0100 ssN0 dddd", "orb rbd,@rs", 0, -"CZSP--", 9, 8, "0100 0100 0000 dddd address_src", "orb rbd,address_src", 0, - "CZSP--", 10, 8, "0100 0100 ssN0 dddd address_src", "orb rbd,address_src(rs)", 0, - "CZSP--", 7, 8, "0000 0100 0000 dddd imm8 imm8", "orb rbd,imm8", 0, - "CZSP--", 4, 8, "1000 0100 ssss dddd", "orb rbd,rbs", 0, - - "---V--", 0, 16, "0011 1111 ddN0 ssss", "out @rd,rs", 0, - "---V--", 0, 16, "0011 1011 ssss 0110 imm16", "out imm16,rs", 0, - "---V--", 0, 8, "0011 1110 ddN0 ssss", "outb @rd,rbs", 0, - "---V--", 0, 8, "0011 1010 ssss 0110 imm16", "outb imm16,rbs", 0, - "---V--", 0, 16, "0011 1011 ssN0 1010 0000 aaaa ddN0 1000", "outd @rd,@rs,ra", 0, - "---V--", 0, 8, "0011 1010 ssN0 1010 0000 aaaa ddN0 1000", "outdb @rd,@rs,rba", 0, - "---V--", 0, 8, "0011 1100 ssN0 0010 0000 aaaa ddN0 1000", "outib @rd,@rs,ra", 0, - "---V--", 0, 16, "0011 1100 ssN0 0010 0000 aaaa ddN0 0000", "outibr @rd,@rs,ra", 0, - - "------", 12, 16, "0001 0111 ssN0 ddN0", "pop @rd,@rs", 0, - "------", 16, 16, "0101 0111 ssN0 ddN0 address_dst", "pop address_dst(rd),@rs", 0, - "------", 16, 16, "0101 0111 ssN0 0000 address_dst", "pop address_dst,@rs", 0, - "------", 8, 16, "1001 0111 ssN0 dddd", "pop rd,@rs", 0, - - "------", 19, 32, "0001 0101 ssN0 ddN0", "popl @rd,@rs", 0, - "------", 23, 32, "0101 0101 ssN0 ddN0 address_dst", "popl address_dst(rd),@rs", 0, - "------", 23, 32, "0101 0101 ssN0 0000 address_dst", "popl address_dst,@rs", 0, - "------", 12, 32, "1001 0101 ssN0 dddd", "popl rrd,@rs", 0, - - "------", 13, 16, "0001 0011 ddN0 ssN0", "push @rd,@rs", 0, - "------", 14, 16, "0101 0011 ddN0 0000 address_src", "push @rd,address_src", 0, - "------", 14, 16, "0101 0011 ddN0 ssN0 address_src", "push @rd,address_src(rs)", 0, - "------", 12, 16, "0000 1101 ddN0 1001 imm16", "push @rd,imm16", 0, - "------", 9, 16, "1001 0011 ddN0 ssss", "push @rd,rs", 0, - - "------", 20, 32, "0001 0001 ddN0 ssN0", "pushl @rd,@rs", 0, - "------", 21, 32, "0101 0001 ddN0 ssN0 address_src", "pushl @rd,address_src(rs)", 0, - "------", 21, 32, "0101 0001 ddN0 0000 address_src", "pushl @rd,address_src", 0, - "------", 12, 32, "1001 0001 ddN0 ssss", "pushl @rd,rrs", 0, - - "------", 11, 16, "0010 0011 ddN0 imm4", "res @rd,imm4", 0, - "------", 14, 16, "0110 0011 ddN0 imm4 address_dst", "res address_dst(rd),imm4", 0, - "------", 13, 16, "0110 0011 0000 imm4 address_dst", "res address_dst,imm4", 0, - "------", 4, 16, "1010 0011 dddd imm4", "res rd,imm4", 0, -"------", 10, 16, "0010 0011 0000 ssss 0000 dddd 0000 0000", "res rd,rs", 0, - - "------", 11, 8, "0010 0010 ddN0 imm4", "resb @rd,imm4", 0, - "------", 14, 8, "0110 0010 ddN0 imm4 address_dst", "resb address_dst(rd),imm4", 0, - "------", 13, 8, "0110 0010 0000 imm4 address_dst", "resb address_dst,imm4", 0, - "------", 4, 8, "1010 0010 dddd imm4", "resb rbd,imm4", 0, -"------", 10, 8, "0010 0010 0000 ssss 0000 dddd 0000 0000", "resb rbd,rs", 0, - - "CZSV--", 7, 16, "1000 1101 imm4 0011", "resflg imm4", 0, - "------", 10, 16, "1001 1110 0000 cccc", "ret cc", 0, - - "CZSV--", 6, 16, "1011 0011 dddd 00I0", "rl rd,imm1or2", 0, - "CZSV--", 6, 8, "1011 0010 dddd 00I0", "rlb rbd,imm1or2", 0, - "CZSV--", 6, 16, "1011 0011 dddd 10I0", "rlc rd,imm1or2", 0, - - "-Z----", 9, 8, "1011 0010 dddd 10I0", "rlcb rbd,imm1or2", 0, - "-Z----", 9, 8, "1011 1110 aaaa bbbb", "rldb rbb,rba", 0, - - "CZSV--", 6, 16, "1011 0011 dddd 01I0", "rr rd,imm1or2", 0, - "CZSV--", 6, 8, "1011 0010 dddd 01I0", "rrb rbd,imm1or2", 0, - "CZSV--", 6, 16, "1011 0011 dddd 11I0", "rrc rd,imm1or2", 0, - - "-Z----", 9, 8, "1011 0010 dddd 11I0", "rrcb rbd,imm1or2", 0, - "-Z----", 9, 8, "1011 1100 aaaa bbbb", "rrdb rbb,rba", 0, - "CZSV--", 5, 16, "1011 0111 ssss dddd", "sbc rd,rs", 0, - "CZSVDH", 5, 8, "1011 0110 ssss dddd", "sbcb rbd,rbs", 0, - - "CZSVDH", 33, 8, "0111 1111 imm8", "sc imm8", 0, - -"CZSV--", 15, 16, "1011 0011 dddd 1011 0000 ssss 0000 0000", "sda rd,rs", 0, -"CZSV--", 15, 8, "1011 0010 dddd 1011 0000 ssss 0000 0000", "sdab rbd,rs", 0, - "CZSV--", 15, 32, "1011 0011 dddd 1111 0000 ssss 0000 0000", "sdal rrd,rs", 0, - -"CZS---", 15, 16, "1011 0011 dddd 0011 0000 ssss 0000 0000", "sdl rd,rs", 0, -"CZS---", 15, 8, "1011 0010 dddd 0011 0000 ssss 0000 0000", "sdlb rbd,rs", 0, - "CZS---", 15, 32, "1011 0011 dddd 0111 0000 ssss 0000 0000", "sdll rrd,rs", 0, - - "------", 11, 16, "0010 0101 ddN0 imm4", "set @rd,imm4", 0, - "------", 14, 16, "0110 0101 ddN0 imm4 address_dst", "set address_dst(rd),imm4", 0, - "------", 13, 16, "0110 0101 0000 imm4 address_dst", "set address_dst,imm4", 0, - "------", 4, 16, "1010 0101 dddd imm4", "set rd,imm4", 0, -"------", 10, 16, "0010 0101 0000 ssss 0000 dddd 0000 0000", "set rd,rs", 0, - "------", 11, 8, "0010 0100 ddN0 imm4", "setb @rd,imm4", 0, - "------", 14, 8, "0110 0100 ddN0 imm4 address_dst", "setb address_dst(rd),imm4", 0, - "------", 13, 8, "0110 0100 0000 imm4 address_dst", "setb address_dst,imm4", 0, - "------", 4, 8, "1010 0100 dddd imm4", "setb rbd,imm4", 0, -"------", 10, 8, "0010 0100 0000 ssss 0000 dddd 0000 0000", "setb rbd,rs", 0, - - "CZSV--", 7, 16, "1000 1101 imm4 0001", "setflg imm4", 0, - - "------", 0, 8, "0011 1100 dddd 0101 imm16", "sinb rbd,imm16", 0, - "------", 0, 8, "0011 1101 dddd 0101 imm16", "sinb rd,imm16", 0, - "------", 0, 16, "0011 1011 ssN0 1000 0001 aaaa ddN0 1000", "sind @rd,@rs,ra", 0, - "------", 0, 8, "0011 1010 ssN0 1000 0001 aaaa ddN0 1000", "sindb @rd,@rs,rba", 0, - "------", 0, 8, "0011 1100 ssN0 0001 0000 aaaa ddN0 1000", "sinib @rd,@rs,ra", 0, - "------", 0, 16, "0011 1100 ssN0 0001 0000 aaaa ddN0 0000", "sinibr @rd,@rs,ra", 0, - - "CZSV--", 13, 16, "1011 0011 dddd 1001 0000 0000 imm8", "sla rd,imm8", 0, - "CZSV--", 13, 8, "1011 0010 dddd 1001 0000 0000 imm8", "slab rbd,imm8", 0, - "CZSV--", 13, 32, "1011 0011 dddd 1101 0000 0000 imm8", "slal rrd,imm8", 0, - - "CZS---", 13, 16, "1011 0011 dddd 0001 0000 0000 imm8", "sll rd,imm8", 0, - "CZS---", 13, 8, "1011 0010 dddd 0001 0000 0000 imm8", "sllb rbd,imm8", 0, - "CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0, - - "------", 0, 16, "0011 1011 ssss 0111 imm16", "sout imm16,rs", 0, - "------", 0, 8, "0011 1010 ssss 0111 imm16", "soutb imm16,rbs", 0, - "------", 0, 16, "0011 1011 ssN0 1011 0000 aaaa ddN0 1000", "soutd @rd,@rs,ra", 0, - "------", 0, 8, "0011 1010 ssN0 1011 0000 aaaa ddN0 1000", "soutdb @rd,@rs,rba", 0, - "------", 0, 8, "0011 1100 ssN0 0011 0000 aaaa ddN0 1000", "soutib @rd,@rs,ra", 0, - "------", 0, 16, "0011 1100 ssN0 0011 0000 aaaa ddN0 0000", "soutibr @rd,@rs,ra", 0, - - "CZSV--", 13, 16, "1011 0011 dddd 1001 1111 1111 nim8", "sra rd,imm8", 0, - "CZSV--", 13, 8, "1011 0010 dddd 1001 1111 1111 nim8", "srab rbd,imm8", 0, - "CZSV--", 13, 32, "1011 0011 dddd 1101 1111 1111 nim8", "sral rrd,imm8", 0, - - "CZSV--", 13, 16, "1011 0011 dddd 0001 1111 1111 nim8", "srl rd,imm8", 0, - "CZSV--", 13, 8, "1011 0010 dddd 0001 1111 1111 nim8", "srlb rbd,imm8", 0, - "CZSV--", 13, 32, "1011 0011 dddd 0101 1111 1111 nim8", "srll rrd,imm8", 0, - - "CZSV--", 7, 16, "0000 0011 ssN0 dddd", "sub rd,@rs", 0, -"CZSV--", 9, 16, "0100 0011 0000 dddd address_src", "sub rd,address_src", 0, - "CZSV--", 10, 16, "0100 0011 ssN0 dddd address_src", "sub rd,address_src(rs)", 0, - "CZSV--", 7, 16, "0000 0010 0000 dddd imm16", "sub rd,imm16", 0, - "CZSV--", 4, 16, "1000 0011 ssss dddd", "sub rd,rs", 0, - - "CZSVDH", 7, 8, "0000 0010 ssN0 dddd", "subb rbd,@rs", 0, -"CZSVDH", 9, 8, "0100 0010 0000 dddd address_src", "subb rbd,address_src", 0, - "CZSVDH", 10, 8, "0100 0010 ssN0 dddd address_src", "subb rbd,address_src(rs)", 0, - "CZSVDH", 7, 8, "0000 0010 0000 dddd imm8 imm8", "subb rbd,imm8", 0, - "CZSVDH", 4, 8, "1000 0010 ssss dddd", "subb rbd,rbs", 0, - - "CZSV--", 14, 32, "0001 0010 ssN0 dddd", "subl rrd,@rs", 0, - "CZSV--", 15, 32, "0101 0010 0000 dddd address_src", "subl rrd,address_src", 0, - "CZSV--", 16, 32, "0101 0010 ssN0 dddd address_src", "subl rrd,address_src(rs)", 0, - "CZSV--", 14, 32, "0001 0010 0000 dddd imm32", "subl rrd,imm32", 0, - "CZSV--", 8, 32, "1001 0010 ssss dddd", "subl rrd,rrs", 0, - - "------", 5, 16, "1010 1111 dddd cccc", "tcc cc,rd", 0, - "------", 5, 8, "1010 1110 dddd cccc", "tccb cc,rbd", 0, - - "-ZS---", 8, 16, "0000 1101 ddN0 0100", "test @rd", 0, - "------", 11, 16, "0100 1101 0000 0100 address_dst", "test address_dst", 0, - "------", 12, 16, "0100 1101 ddN0 0100 address_dst", "test address_dst(rd)", 0, - "------", 7, 16, "1000 1101 dddd 0100", "test rd", 0, - - "-ZSP--", 8, 8, "0000 1100 ddN0 0100", "testb @rd", 0, - "-ZSP--", 11, 8, "0100 1100 0000 0100 address_dst", "testb address_dst", 0, - "-ZSP--", 12, 8, "0100 1100 ddN0 0100 address_dst", "testb address_dst(rd)", 0, - "-ZSP--", 7, 8, "1000 1100 dddd 0100", "testb rbd", 0, - - "-ZS---", 13, 32, "0001 1100 ddN0 1000", "testl @rd", 0, -"-ZS---", 16, 32, "0101 1100 0000 1000 address_dst", "testl address_dst", 0, - "-ZS---", 17, 32, "0101 1100 ddN0 1000 address_dst", "testl address_dst(rd)", 0, - "-ZS---", 13, 32, "1001 1100 dddd 1000", "testl rrd", 0, - - "-ZSV--", 25, 8, "1011 1000 ddN0 1000 0000 aaaa ssN0 0000", "trdb @rd,@rs,rba", 0, - "-ZSV--", 25, 8, "1011 1000 ddN0 1100 0000 aaaa ssN0 0000", "trdrb @rd,@rs,rba", 0, - "-ZSV--", 25, 8, "1011 1000 ddN0 0000 0000 rrrr ssN0 0000", "trib @rd,@rs,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 ddN0 0100 0000 rrrr ssN0 0000", "trirb @rd,@rs,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 1110 0000 rrrr bbN0 1110", "trtdrb @ra,@rb,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 0010 0000 rrrr bbN0 0000", "trtib @ra,@rb,rr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 0110 0000 rrrr bbN0 1110", "trtirb @ra,@rb,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtrb @ra,@rb,rbr", 0, - - "--S---", 11, 16, "0000 1101 ddN0 0110", "tset @rd", 0, - "--S---", 14, 16, "0100 1101 0000 0110 address_dst", "tset address_dst", 0, - "--S---", 15, 16, "0100 1101 ddN0 0110 address_dst", "tset address_dst(rd)", 0, - "--S---", 7, 16, "1000 1101 dddd 0110", "tset rd", 0, - - "--S---", 11, 8, "0000 1100 ddN0 0110", "tsetb @rd", 0, - "--S---", 14, 8, "0100 1100 0000 0110 address_dst", "tsetb address_dst", 0, - "--S---", 15, 8, "0100 1100 ddN0 0110 address_dst", "tsetb address_dst(rd)", 0, - "--S---", 7, 8, "1000 1100 dddd 0110", "tsetb rbd", 0, - - "-ZS---", 7, 16, "0000 1001 ssN0 dddd", "xor rd,@rs", 0, -"-ZS---", 9, 16, "0100 1001 0000 dddd address_src", "xor rd,address_src", 0, - "-ZS---", 10, 16, "0100 1001 ssN0 dddd address_src", "xor rd,address_src(rs)", 0, - "-ZS---", 7, 16, "0000 1001 0000 dddd imm16", "xor rd,imm16", 0, - "-ZS---", 4, 16, "1000 1001 ssss dddd", "xor rd,rs", 0, - - "-ZSP--", 7, 8, "0000 1000 ssN0 dddd", "xorb rbd,@rs", 0, -"-ZSP--", 9, 8, "0100 1000 0000 dddd address_src", "xorb rbd,address_src", 0, - "-ZSP--", 10, 8, "0100 1000 ssN0 dddd address_src", "xorb rbd,address_src(rs)", 0, - "-ZSP--", 7, 8, "0000 1000 0000 dddd imm8 imm8", "xorb rbd,imm8", 0, - "-ZSP--", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0, - "*", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0, - "*", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -int -count () -{ - struct op *p = opt; - int r = 0; - - while (p->name) - { - r++; - p++; - } - return r; - -} - -static -int -func (a, b) - struct op *a; - struct op *b; -{ - return strcmp ((a)->name, (b)->name); -} - - -/* opcode - - literal 0000 nnnn insert nnn into stream - operand 0001 nnnn insert operand reg nnn into stream -*/ - -struct tok_struct -{ - - char *match; - char *token; - int length; -}; - -struct tok_struct args[] = -{ - - {"address_src(rs)", "CLASS_X+(ARG_RS)",}, - {"address_dst(rd)", "CLASS_X+(ARG_RD)",}, - - {"rs(imm16)", "CLASS_BA+(ARG_RS)",}, - {"rd(imm16)", "CLASS_BA+(ARG_RD)",}, - {"prd", "CLASS_PR+(ARG_RD)",}, - {"address_src", "CLASS_DA+(ARG_SRC)",}, - {"address_dst", "CLASS_DA+(ARG_DST)",}, - {"rd(rx)", "CLASS_BX+(ARG_RD)",}, - {"rs(rx)", "CLASS_BX+(ARG_RS)",}, - - {"disp16", "CLASS_DISP",}, - {"disp12", "CLASS_DISP",}, - {"disp7", "CLASS_DISP",}, - {"disp8", "CLASS_DISP",}, - {"flags", "CLASS_FLAGS",}, - - {"imm16", "CLASS_IMM+(ARG_IMM16)",}, - {"imm1or2", "CLASS_IMM+(ARG_IMM1OR2)",}, - {"imm32", "CLASS_IMM+(ARG_IMM32)",}, - {"imm4m1", "CLASS_IMM +(ARG_IMM4M1)",}, - {"imm4", "CLASS_IMM +(ARG_IMM4)",}, - {"n", "CLASS_IMM + (ARG_IMMN)",}, - {"ctrl", "CLASS_CTRL",}, - {"rba", "CLASS_REG_BYTE+(ARG_RA)",}, - {"rbb", "CLASS_REG_BYTE+(ARG_RB)",}, - {"rbd", "CLASS_REG_BYTE+(ARG_RD)",}, - {"rbs", "CLASS_REG_BYTE+(ARG_RS)",}, - {"rbr", "CLASS_REG_BYTE+(ARG_RR)",}, - - {"rrd", "CLASS_REG_LONG+(ARG_RD)",}, - {"rrs", "CLASS_REG_LONG+(ARG_RS)",}, - - {"rqd", "CLASS_REG_QUAD+(ARG_RD)",}, - - {"rd", "CLASS_REG_WORD+(ARG_RD)",}, - {"rs", "CLASS_REG_WORD+(ARG_RS)",}, - - {"@rd", "CLASS_IR+(ARG_RD)",}, - {"@ra", "CLASS_IR+(ARG_RA)",}, - {"@rb", "CLASS_IR+(ARG_RB)",}, - {"@rs", "CLASS_IR+(ARG_RS)",}, - - {"imm8", "CLASS_IMM+(ARG_IMM8)",}, - {"i2", "CLASS_IMM+(ARG_IMM2)",}, - {"cc", "CLASS_CC",}, - - {"rr", "CLASS_REG_WORD+(ARG_RR)",}, - {"ra", "CLASS_REG_WORD+(ARG_RA)",}, - {"rs", "CLASS_REG_WORD+(ARG_RS)",}, - - {"1", "CLASS_IMM+(ARG_IMM_1)",}, - {"2", "CLASS_IMM+(ARG_IMM_2)",}, - - 0, 0 -}; - -struct tok_struct toks[] = -{ - "0000", "CLASS_BIT+0", 1, - "0001", "CLASS_BIT+1", 1, - "0010", "CLASS_BIT+2", 1, - "0011", "CLASS_BIT+3", 1, - "0100", "CLASS_BIT+4", 1, - "0101", "CLASS_BIT+5", 1, - "0110", "CLASS_BIT+6", 1, - "0111", "CLASS_BIT+7", 1, - "1000", "CLASS_BIT+8", 1, - "1001", "CLASS_BIT+9", 1, - "1010", "CLASS_BIT+0xa", 1, - "1011", "CLASS_BIT+0xb", 1, - "1100", "CLASS_BIT+0xc", 1, - "1101", "CLASS_BIT+0xd", 1, - "1110", "CLASS_BIT+0xe", 1, - "1111", "CLASS_BIT+0xf", 1, - - "00I0", "CLASS_BIT_1OR2+0", 1, - "00I0", "CLASS_BIT_1OR2+1", 1, - "00I0", "CLASS_BIT_1OR2+2", 1, - "00I0", "CLASS_BIT_1OR2+3", 1, - "01I0", "CLASS_BIT_1OR2+4", 1, - "01I0", "CLASS_BIT_1OR2+5", 1, - "01I0", "CLASS_BIT_1OR2+6", 1, - "01I0", "CLASS_BIT_1OR2+7", 1, - "10I0", "CLASS_BIT_1OR2+8", 1, - "10I0", "CLASS_BIT_1OR2+9", 1, - "10I0", "CLASS_BIT_1OR2+0xa", 1, - "10I0", "CLASS_BIT_1OR2+0xb", 1, - "11I0", "CLASS_BIT_1OR2+0xc", 1, - "11I0", "CLASS_BIT_1OR2+0xd", 1, - "11I0", "CLASS_BIT_1OR2+0xe", 1, - "11I0", "CLASS_BIT_1OR2+0xf", 1, - - "ssss", "CLASS_REG+(ARG_RS)", 1, - "dddd", "CLASS_REG+(ARG_RD)", 1, - "aaaa", "CLASS_REG+(ARG_RA)", 1, - "bbbb", "CLASS_REG+(ARG_RB)", 1, - "rrrr", "CLASS_REG+(ARG_RR)", 1, - - "ssN0", "CLASS_REGN0+(ARG_RS)", 1, - "ddN0", "CLASS_REGN0+(ARG_RD)", 1, - "aaN0", "CLASS_REGN0+(ARG_RA)", 1, - "bbN0", "CLASS_REGN0+(ARG_RB)", 1, - "rrN0", "CLASS_REGN0+(ARG_RR)", 1, - - "cccc", "CLASS_CC", 1, - "nnnn", "CLASS_IMM+(ARG_IMMN)", 1, - "xxxx", "CLASS_REG+(ARG_RX)", 1, - "xxN0", "CLASS_REGN0+(ARG_RX)", 1, - "nminus1", "CLASS_IMM+(ARG_IMMNMINUS1)", 1, - - "disp16", "CLASS_DISP+(ARG_DISP16)", 4, - "disp12", "CLASS_DISP+(ARG_DISP12)", 3, - "flags", "CLASS_FLAGS", 1, - "address_dst", "CLASS_ADDRESS+(ARG_DST)", 4, - "address_src", "CLASS_ADDRESS+(ARG_SRC)", 4, - "imm4m1", "CLASS_IMM+(ARG_IMM4M1)", 1, - "imm4", "CLASS_IMM+(ARG_IMM4)", 1, - - "imm8", "CLASS_IMM+(ARG_IMM8)", 2, - "imm16", "CLASS_IMM+(ARG_IMM16)", 4, - "imm32", "CLASS_IMM+(ARG_IMM32)", 8, - "nim8", "CLASS_IMM+(ARG_NIM8)", 2, - "0ccc", "CLASS_0CCC", 1, - "1ccc", "CLASS_1CCC", 1, - "disp8", "CLASS_DISP8", 2, - "0disp7", "CLASS_0DISP7", 2, - "1disp7", "CLASS_1DISP7", 2, - "01ii", "CLASS_01II", 1, - "00ii", "CLASS_00II", 1, - 0, 0 - -}; - -char * -translate (table, x, length) - struct tok_struct *table; - char *x; - int *length; -{ - - int found; - - found = 0; - while (table->match) - { - int l = strlen (table->match); - - if (strncmp (table->match, x, l) == 0) - { - /* Got a hit */ - printf ("%s", table->token); - *length += table->length; - return x + l; - } - - table++; - } - fprintf (stderr, "Can't find %s\n", x); - printf ("**** Can't find %s\n", x); - while (*x) - x++; - return x; -} - -void -chewbits (bits, length) - char *bits; - int *length; -{ - int n = 0; - - *length = 0; - printf ("{"); - while (*bits) - { - while (*bits == ' ') - { - bits++; - } - bits = translate (toks, bits, length); - n++; - printf (","); - - } - while (n < BYTE_INFO_LEN - 1) - { - printf ("0,"); - n++; - } - printf ("}"); -} - - -static -int -chewname (name) - char *name; -{ - char *n; - int nargs = 0; - - n = name; - printf ("\""); - while (*n && !iswhite (*n)) - { - printf ("%c", *n); - n++; - } - printf ("\","); /* Scan the operands and make entires for - them -remember indirect things */ - - n = name; - printf ("OPC_"); - while (*n && !iswhite (*n)) - { - printf ("%c", *n); - n++; - } - printf (",0,{"); - - while (*n) - { - int d; - - while (*n == ',' || iswhite (*n)) - n++; - nargs++; - n = translate (args, n, &d); - printf (","); - } - if (nargs == 0) - { - printf ("0"); - } - printf ("},"); - return nargs; -} - -static -void -sub (x, c) - char *x; - char c; -{ - while (*x) - { - if (x[0] == c && x[1] == c && - x[2] == c && x[3] == c) - { - x[2] = 'N'; - x[3] = '0'; - } - x++; - } -} - - -#if 0 -#define D(x) ((x) == '1' || (x) =='0') -#define M(y) (strncmp(y,x,4)==0) -printmangled (x) - char *x; -{ - return; - while (*x) - { - if (D (x[0]) && D (x[1]) && D (x[2]) && D (x[3])) - { - printf ("XXXX"); - } - else if (M ("ssss")) - { - printf ("ssss"); - } - else if (M ("dddd")) - { - printf ("dddd"); - } - else - printf ("____"); - - x += 4; - - if (x[0] == ' ') - { - printf ("_"); - x++; - } - } - -} - -#endif -/*#define WORK_TYPE*/ -void -print_type (n) - struct op *n; -{ -#ifdef WORK_TYPE - while (*s && !iswhite (*s)) - { - l = *s; - s++; - } - switch (l) - { - case 'l': - printf ("32,"); - break; - case 'b': - printf ("8,"); - break; - default: - printf ("16,"); - break; - } -#else - printf ("%2d,", n->type); -#endif -} - - -void -internal () -{ - int c = count (); - struct op *new = xmalloc (sizeof (struct op) * c); - struct op *p = opt; - memcpy (new, p, c * sizeof (struct op)); - - /* sort all names in table alphabetically */ - qsort (new, c, sizeof (struct op), func); - - p = new; - while (p->flags[0] != '*') - { - /* If there are any @rs, sub the ssss into a ssn0, - (rs), (ssn0) - */ - int loop = 1; - - printf ("\"%s\",%2d, ", p->flags, p->cycles); - while (loop) - { - char *s = p->name; - - loop = 0; - while (*s) - { - if (s[0] == '@') - { - char c; - - /* skip the r and sub the string */ - s++; - c = s[1]; - sub (p->bits, c); - } - if (s[0] == '(' && s[3] == ')') - { - sub (p->bits, s[2]); - } - if (s[0] == '(') - { - sub (p->bits, s[-1]); - } - - s++; - } - - } - print_type (p); - printf ("\"%s\",\"%s\",0,\n", p->bits, p->name); - p++; - } -} - -static -void -gas () -{ - int c = count (); - struct op *p = opt; - int idx = 0; - char *oldname = ""; - struct op *new = xmalloc (sizeof (struct op) * c); - - memcpy (new, p, c * sizeof (struct op)); - - /* sort all names in table alphabetically */ - qsort (new, c, sizeof (struct op), func); - - printf (" /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */\n"); - - printf ("#define ARG_MASK 0x0f\n"); - - printf ("#define ARG_SRC 0x01\n"); - printf ("#define ARG_DST 0x02\n"); - - printf ("#define ARG_RS 0x01\n"); - printf ("#define ARG_RD 0x02\n"); - printf ("#define ARG_RA 0x03\n"); - printf ("#define ARG_RB 0x04\n"); - printf ("#define ARG_RR 0x05\n"); - printf ("#define ARG_RX 0x06\n"); - printf ("#define ARG_IMM4 0x01\n"); - printf ("#define ARG_IMM8 0x02\n"); - printf ("#define ARG_IMM16 0x03\n"); - printf ("#define ARG_IMM32 0x04\n"); - printf ("#define ARG_IMMN 0x05\n"); - printf ("#define ARG_IMMNMINUS1 0x05\n"); - printf ("#define ARG_IMM_1 0x06\n"); - printf ("#define ARG_IMM_2 0x07\n"); - printf ("#define ARG_DISP16 0x08\n"); - printf ("#define ARG_NIM8 0x09\n"); - printf ("#define ARG_IMM2 0x0a\n"); - printf ("#define ARG_IMM1OR2 0x0b\n"); - - printf ("#define ARG_DISP12 0x0b\n"); - printf ("#define ARG_DISP8 0x0c\n"); - printf ("#define ARG_IMM4M1 0x0d\n"); - printf ("#define CLASS_MASK 0x1fff0\n"); - printf ("#define CLASS_X 0x10\n"); - printf ("#define CLASS_BA 0x20\n"); - printf ("#define CLASS_DA 0x30\n"); - printf ("#define CLASS_BX 0x40\n"); - printf ("#define CLASS_DISP 0x50\n"); - printf ("#define CLASS_IMM 0x60\n"); - printf ("#define CLASS_CC 0x70\n"); - printf ("#define CLASS_CTRL 0x80\n"); - printf ("#define CLASS_ADDRESS 0xd0\n"); - printf ("#define CLASS_0CCC 0xe0\n"); - printf ("#define CLASS_1CCC 0xf0\n"); - printf ("#define CLASS_0DISP7 0x100\n"); - printf ("#define CLASS_1DISP7 0x200\n"); - printf ("#define CLASS_01II 0x300\n"); - printf ("#define CLASS_00II 0x400\n"); - printf ("#define CLASS_BIT 0x500\n"); - printf ("#define CLASS_FLAGS 0x600\n"); - printf ("#define CLASS_IR 0x700\n"); - printf ("#define CLASS_DISP8 0x800\n"); - - printf ("#define CLASS_BIT_1OR2 0x900\n"); - printf ("#define CLASS_REG 0x7000\n"); - printf ("#define CLASS_REG_BYTE 0x2000\n"); - printf ("#define CLASS_REG_WORD 0x3000\n"); - printf ("#define CLASS_REG_QUAD 0x4000\n"); - printf ("#define CLASS_REG_LONG 0x5000\n"); - printf ("#define CLASS_REGN0 0x8000\n"); - printf ("#define CLASS_PR 0x10000\n"); - - printf ("#define OPC_adc 0\n"); - printf ("#define OPC_adcb 1\n"); - printf ("#define OPC_add 2\n"); - printf ("#define OPC_addb 3\n"); - printf ("#define OPC_addl 4\n"); - printf ("#define OPC_and 5\n"); - printf ("#define OPC_andb 6\n"); - printf ("#define OPC_bit 7\n"); - printf ("#define OPC_bitb 8\n"); - printf ("#define OPC_call 9\n"); - printf ("#define OPC_calr 10\n"); - printf ("#define OPC_clr 11\n"); - printf ("#define OPC_clrb 12\n"); - printf ("#define OPC_com 13\n"); - printf ("#define OPC_comb 14\n"); - printf ("#define OPC_comflg 15\n"); - printf ("#define OPC_cp 16\n"); - printf ("#define OPC_cpb 17\n"); - printf ("#define OPC_cpd 18\n"); - printf ("#define OPC_cpdb 19\n"); - printf ("#define OPC_cpdr 20\n"); - printf ("#define OPC_cpdrb 21\n"); - printf ("#define OPC_cpi 22\n"); - printf ("#define OPC_cpib 23\n"); - printf ("#define OPC_cpir 24\n"); - printf ("#define OPC_cpirb 25\n"); - printf ("#define OPC_cpl 26\n"); - printf ("#define OPC_cpsd 27\n"); - printf ("#define OPC_cpsdb 28\n"); - printf ("#define OPC_cpsdr 29\n"); - printf ("#define OPC_cpsdrb 30\n"); - printf ("#define OPC_cpsi 31\n"); - printf ("#define OPC_cpsib 32\n"); - printf ("#define OPC_cpsir 33\n"); - printf ("#define OPC_cpsirb 34\n"); - printf ("#define OPC_dab 35\n"); - printf ("#define OPC_dbjnz 36\n"); - printf ("#define OPC_dec 37\n"); - printf ("#define OPC_decb 38\n"); - printf ("#define OPC_di 39\n"); - printf ("#define OPC_div 40\n"); - printf ("#define OPC_divl 41\n"); - printf ("#define OPC_djnz 42\n"); - printf ("#define OPC_ei 43\n"); - printf ("#define OPC_ex 44\n"); - printf ("#define OPC_exb 45\n"); - printf ("#define OPC_exts 46\n"); - printf ("#define OPC_extsb 47\n"); - printf ("#define OPC_extsl 48\n"); - printf ("#define OPC_halt 49\n"); - printf ("#define OPC_in 50\n"); - printf ("#define OPC_inb 51\n"); - printf ("#define OPC_inc 52\n"); - printf ("#define OPC_incb 53\n"); - printf ("#define OPC_ind 54\n"); - printf ("#define OPC_indb 55\n"); - printf ("#define OPC_inib 56\n"); - printf ("#define OPC_inibr 57\n"); - printf ("#define OPC_iret 58\n"); - printf ("#define OPC_jp 59\n"); - printf ("#define OPC_jr 60\n"); - printf ("#define OPC_ld 61\n"); - printf ("#define OPC_lda 62\n"); - printf ("#define OPC_ldar 63\n"); - printf ("#define OPC_ldb 64\n"); - printf ("#define OPC_ldctl 65\n"); - printf ("#define OPC_ldir 66\n"); - printf ("#define OPC_ldirb 67\n"); - printf ("#define OPC_ldk 68\n"); - printf ("#define OPC_ldl 69\n"); - printf ("#define OPC_ldm 70\n"); - printf ("#define OPC_ldps 71\n"); - printf ("#define OPC_ldr 72\n"); - printf ("#define OPC_ldrb 73\n"); - printf ("#define OPC_ldrl 74\n"); - printf ("#define OPC_mbit 75\n"); - printf ("#define OPC_mreq 76\n"); - printf ("#define OPC_mres 77\n"); - printf ("#define OPC_mset 78\n"); - printf ("#define OPC_mult 79\n"); - printf ("#define OPC_multl 80\n"); - printf ("#define OPC_neg 81\n"); - printf ("#define OPC_negb 82\n"); - printf ("#define OPC_nop 83\n"); - printf ("#define OPC_or 84\n"); - printf ("#define OPC_orb 85\n"); - printf ("#define OPC_out 86\n"); - printf ("#define OPC_outb 87\n"); - printf ("#define OPC_outd 88\n"); - printf ("#define OPC_outdb 89\n"); - printf ("#define OPC_outib 90\n"); - printf ("#define OPC_outibr 91\n"); - printf ("#define OPC_pop 92\n"); - printf ("#define OPC_popl 93\n"); - printf ("#define OPC_push 94\n"); - printf ("#define OPC_pushl 95\n"); - printf ("#define OPC_res 96\n"); - printf ("#define OPC_resb 97\n"); - printf ("#define OPC_resflg 98\n"); - printf ("#define OPC_ret 99\n"); - printf ("#define OPC_rl 100\n"); - printf ("#define OPC_rlb 101\n"); - printf ("#define OPC_rlc 102\n"); - printf ("#define OPC_rlcb 103\n"); - printf ("#define OPC_rldb 104\n"); - printf ("#define OPC_rr 105\n"); - printf ("#define OPC_rrb 106\n"); - printf ("#define OPC_rrc 107\n"); - printf ("#define OPC_rrcb 108\n"); - printf ("#define OPC_rrdb 109\n"); - printf ("#define OPC_sbc 110\n"); - printf ("#define OPC_sbcb 111\n"); - printf ("#define OPC_sda 112\n"); - printf ("#define OPC_sdab 113\n"); - printf ("#define OPC_sdal 114\n"); - printf ("#define OPC_sdl 115\n"); - printf ("#define OPC_sdlb 116\n"); - printf ("#define OPC_sdll 117\n"); - printf ("#define OPC_set 118\n"); - printf ("#define OPC_setb 119\n"); - printf ("#define OPC_setflg 120\n"); - printf ("#define OPC_sinb 121\n"); - printf ("#define OPC_sind 122\n"); - printf ("#define OPC_sindb 123\n"); - printf ("#define OPC_sinib 124\n"); - printf ("#define OPC_sinibr 125\n"); - printf ("#define OPC_sla 126\n"); - printf ("#define OPC_slab 127\n"); - printf ("#define OPC_slal 128\n"); - printf ("#define OPC_sll 129\n"); - printf ("#define OPC_sllb 130\n"); - printf ("#define OPC_slll 131\n"); - printf ("#define OPC_sout 132\n"); - printf ("#define OPC_soutb 133\n"); - printf ("#define OPC_soutd 134\n"); - printf ("#define OPC_soutdb 135\n"); - printf ("#define OPC_soutib 136\n"); - printf ("#define OPC_soutibr 137\n"); - printf ("#define OPC_sra 138\n"); - printf ("#define OPC_srab 139\n"); - printf ("#define OPC_sral 140\n"); - printf ("#define OPC_srl 141\n"); - printf ("#define OPC_srlb 142\n"); - printf ("#define OPC_srll 143\n"); - printf ("#define OPC_sub 144\n"); - printf ("#define OPC_subb 145\n"); - printf ("#define OPC_subl 146\n"); - printf ("#define OPC_tcc 147\n"); - printf ("#define OPC_tccb 148\n"); - printf ("#define OPC_test 149\n"); - printf ("#define OPC_testb 150\n"); - printf ("#define OPC_testl 151\n"); - printf ("#define OPC_trdb 152\n"); - printf ("#define OPC_trdrb 153\n"); - printf ("#define OPC_trib 154\n"); - printf ("#define OPC_trirb 155\n"); - printf ("#define OPC_trtdrb 156\n"); - printf ("#define OPC_trtib 157\n"); - printf ("#define OPC_trtirb 158\n"); - printf ("#define OPC_trtrb 159\n"); - printf ("#define OPC_tset 160\n"); - printf ("#define OPC_tsetb 161\n"); - printf ("#define OPC_xor 162\n"); - printf ("#define OPC_xorb 163\n"); - - printf ("#define OPC_ldd 164 \n"); - printf ("#define OPC_lddb 165 \n"); - printf ("#define OPC_lddr 166 \n"); - printf ("#define OPC_lddrb 167 \n"); - printf ("#define OPC_ldi 168 \n"); - printf ("#define OPC_ldib 169 \n"); - printf ("#define OPC_sc 170\n"); - printf ("#define OPC_bpt 171\n"); - printf ("#define OPC_ext0e 172\n"); - printf ("#define OPC_ext0f 172\n"); - printf ("#define OPC_ext8e 172\n"); - printf ("#define OPC_ext8f 172\n"); - printf ("#define OPC_rsvd36 172\n"); - printf ("#define OPC_rsvd38 172\n"); - printf ("#define OPC_rsvd78 172\n"); - printf ("#define OPC_rsvd7e 172\n"); - printf ("#define OPC_rsvd9d 172\n"); - printf ("#define OPC_rsvd9f 172\n"); - printf ("#define OPC_rsvdb9 172\n"); - printf ("#define OPC_rsvdbf 172\n"); -#if 0 - for (i = 0; toks[i].token; i++) - printf ("#define %s\t0x%x\n", toks[i].token, i * 16); -#endif - printf ("typedef struct {\n"); - - printf ("#ifdef NICENAMES\n"); - printf ("char *nicename;\n"); - printf ("int type;\n"); - printf ("int cycles;\n"); - printf ("int flags;\n"); - printf ("#endif\n"); - printf ("char *name;\n"); - printf ("unsigned char opcode;\n"); - printf ("void (*func)();\n"); - printf ("unsigned int arg_info[4];\n"); - printf ("unsigned int byte_info[%d];\n", BYTE_INFO_LEN); - printf ("int noperands;\n"); - printf ("int length;\n"); - printf ("int idx;\n"); - printf ("} opcode_entry_type;\n"); - printf ("#ifdef DEFINE_TABLE\n"); - printf ("opcode_entry_type z8k_table[] = {\n"); - - while (new->flags && new->flags[0]) - { - int nargs; - int length; - - printf ("\n\n/* %s *** %s */\n", new->bits, new->name); - printf ("{\n"); - - printf ("#ifdef NICENAMES\n"); - printf ("\"%s\",%d,%d,\n", new->name, new->type, new->cycles); - { - int answer = 0; - char *p = new->flags; - - while (*p) - { - answer <<= 1; - - if (*p != '-') - answer |= 1; - p++; - } - printf ("0x%02x,\n", answer); - } - - printf ("#endif\n"); - - nargs = chewname (new->name); - - printf ("\n\t"); - chewbits (new->bits, &length); - length /= 2; - if (length & 1) - abort(); - - printf (",%d,%d,%d", nargs, length, idx); - idx++; - oldname = new->name; - printf ("},\n"); - new++; - } - printf ("0,0};\n"); - printf ("#endif\n"); -} - - -int -main (ac, av) - int ac; - char **av; -{ - struct op *p = opt; - - if (ac == 2 && strcmp (av[1], "-t") == 0) - { - internal (); - } - else if (ac == 2 && strcmp (av[1], "-h") == 0) - { - while (p->name) - { - printf ("%-25s\t%s\n", p->name, p->bits); - p++; - } - } - - else if (ac == 2 && strcmp (av[1], "-a") == 0) - { - gas (); - } - else if (ac == 2 && strcmp (av[1], "-d") == 0) - { - /*dis();*/ - } - else - { - printf ("Usage: %s -t\n", av[0]); - printf ("-t : generate new z8.c internal table\n"); - printf ("-a : generate new table for gas\n"); - printf ("-d : generate new table for disassemble\n"); - printf ("-h : generate new table for humans\n"); - } -return 0; -} |