Merge commit 28de0fb48 from llvm git (by Luís Marques):

  [RISCV] Set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_x defines

  The RISCV target did not set the GCC atomic compare and swap defines,
  unlike other targets. This broke builds for things like glib on
  RISCV.

  Patch by Kristof Provost (kprovost)

  Differential Revision: https://reviews.llvm.org/D91784

This should fix building glib20 on RISC-V and unblock a number of
dependent ports.

Requested by:	kp
MFC after:	3 days

1 files changed, 7 insertions, 1 deletions

diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
index 4ba703c8dd1aa..6154c0f990029 100644
--- a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
+++ b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
@@ -115,8 +115,14 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
     Builder.defineMacro("__riscv_muldiv");
   }
 
-  if (HasA)
+  if (HasA) {
     Builder.defineMacro("__riscv_atomic");
+    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+    if (Is64Bit)
+      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+  }
 
   if (HasF || HasD) {
     Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");