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authorWarner Losh <imp@FreeBSD.org>2015-02-27 22:16:54 +0000
committerWarner Losh <imp@FreeBSD.org>2015-02-27 22:16:54 +0000
commitda75c2cc5808a45edc76752ba495dcc5dcd4346c (patch)
tree74a0899e9f467d761efca9e14d7d3213fb899de8 /include/dt-bindings/clock/stih410-clks.h
parentab9104d36764981b663e037d0e48496993a070a4 (diff)
Notes
Diffstat (limited to 'include/dt-bindings/clock/stih410-clks.h')
-rw-r--r--include/dt-bindings/clock/stih410-clks.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 0000000000000..2097a4bbe155d
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES 32
+#define CLK_RX_ICN_HADES 33
+#define CLK_ICN_REG_16 34
+#define CLK_PP_HADES 35
+#define CLK_CLUST_HADES 36
+#define CLK_HWPE_HADES 37
+#define CLK_FC_HADES 38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER 4
+#define CLK_USB2_PHY 5
+
+#endif