vendor/llvm/llvm-trunk-r306956

7 files changed, 158 insertions, 94 deletions

diff --git a/include/llvm/CodeGen/GlobalISel/CallLowering.h b/include/llvm/CodeGen/GlobalISel/CallLowering.h
index 3e9a9d514cb87..e7ce1946889e3 100644
--- a/include/llvm/CodeGen/GlobalISel/CallLowering.h
+++ b/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering --*- C++ -*-===//
+//===- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering ---*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -15,21 +15,31 @@
 #ifndef LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
 #define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
 
-#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/IR/Function.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/IR/CallSite.h"
+#include "llvm/IR/CallingConv.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetCallingConv.h"
+#include <cstdint>
+#include <functional>
 
 namespace llvm {
-// Forward declarations.
+
+class DataLayout;
+class Function;
 class MachineIRBuilder;
 class MachineOperand;
+struct MachinePointerInfo;
+class MachineRegisterInfo;
 class TargetLowering;
+class Type;
 class Value;
 
 class CallLowering {
   const TargetLowering *TLI;
+
 public:
   struct ArgInfo {
     unsigned Reg;
@@ -49,6 +59,12 @@ public:
   /// arugment should go, exactly what happens can vary slightly. This
   /// class abstracts the differences.
   struct ValueHandler {
+    ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+                 CCAssignFn *AssignFn)
+      : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {}
+
+    virtual ~ValueHandler() = default;
+
     /// Materialize a VReg containing the address of the specified
     /// stack-based object. This is either based on a FrameIndex or
     /// direct SP manipulation, depending on the context. \p MPO
@@ -89,12 +105,6 @@ public:
       return AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
     }
 
-    ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
-                 CCAssignFn *AssignFn)
-      : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {}
-
-    virtual ~ValueHandler() {}
-
     MachineIRBuilder &MIRBuilder;
     MachineRegisterInfo &MRI;
     CCAssignFn *AssignFn;
@@ -112,7 +122,6 @@ protected:
     return static_cast<const XXXTargetLowering *>(TLI);
   }
 
-
   template <typename FuncInfoTy>
   void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL,
                    const FuncInfoTy &FuncInfo) const;
@@ -126,7 +135,7 @@ protected:
 
 public:
   CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
-  virtual ~CallLowering() {}
+  virtual ~CallLowering() = default;
 
   /// This hook must be implemented to lower outgoing return values, described
   /// by \p Val, into the specified virtual register \p VReg.
@@ -200,6 +209,7 @@ public:
                  unsigned ResReg, ArrayRef<unsigned> ArgRegs,
                  std::function<unsigned()> GetCalleeReg) const;
 };
-} // End namespace llvm.
 
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index e292e8913db06..7061c014d9b7f 100644
--- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ---*- C++ -*-===//
+//===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -19,24 +19,33 @@
 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
 
-#include "Types.h"
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/Types.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/IR/Intrinsics.h"
+#include <memory>
+#include <utility>
 
 namespace llvm {
-// Forward declarations.
+
+class AllocaInst;
 class BasicBlock;
+class CallInst;
 class CallLowering;
 class Constant;
+class DataLayout;
 class Instruction;
 class MachineBasicBlock;
 class MachineFunction;
 class MachineInstr;
-class OptimizationRemarkEmitter;
 class MachineRegisterInfo;
+class OptimizationRemarkEmitter;
+class PHINode;
 class TargetPassConfig;
+class User;
+class Value;
 
 // Technically the pass should run on an hypothetical MachineModule,
 // since it should translate Global into some sort of MachineGlobal.
@@ -53,6 +62,7 @@ public:
 private:
   /// Interface used to lower the everything related to calls.
   const CallLowering *CLI;
+
   /// Mapping of the values of the current LLVM IR function
   /// to the related virtual registers.
   ValueToVReg ValToVReg;
@@ -67,7 +77,7 @@ private:
   // a mapping between the edges arriving at the BasicBlock to the corresponding
   // created MachineBasicBlocks. Some BasicBlocks that get translated to a
   // single MachineBasicBlock may also end up in this Map.
-  typedef std::pair<const BasicBlock *, const BasicBlock *> CFGEdge;
+  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
   DenseMap<CFGEdge, SmallVector<MachineBasicBlock *, 1>> MachinePreds;
 
   // List of stubbed PHI instructions, for values and basic blocks to be filled
@@ -165,7 +175,6 @@ private:
     return translateCompare(U, MIRBuilder);
   }
 
-
   /// Add remaining operands onto phis we've translated. Executed after all
   /// MachineBasicBlocks for the function have been created.
   void finishPendingPhis();
@@ -356,7 +365,7 @@ private:
   MachineFunction *MF;
 
   /// MachineRegisterInfo used to create virtual registers.
-  MachineRegisterInfo *MRI;
+  MachineRegisterInfo *MRI = nullptr;
 
   const DataLayout *DL;
 
@@ -430,5 +439,6 @@ public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 };
 
-} // End namespace llvm.
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
index b3ef7c2dc1859..ec60123e54b15 100644
--- a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
+++ b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
@@ -1,4 +1,4 @@
-//==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==//
+//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -16,15 +16,16 @@
 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
 
-#include "llvm/ADT/Optional.h"
 #include <bitset>
+#include <cstddef>
 #include <cstdint>
 #include <functional>
+#include <initializer_list>
 
 namespace llvm {
+
 class MachineInstr;
 class MachineInstrBuilder;
-class MachineFunction;
 class MachineOperand;
 class MachineRegisterInfo;
 class RegisterBankInfo;
@@ -60,7 +61,7 @@ public:
 /// Provides the logic to select generic machine instructions.
 class InstructionSelector {
 public:
-  virtual ~InstructionSelector() {}
+  virtual ~InstructionSelector() = default;
 
   /// Select the (possibly generic) instruction \p I to only use target-specific
   /// opcodes. It is OK to insert multiple instructions, but they cannot be
@@ -76,7 +77,7 @@ public:
   virtual bool select(MachineInstr &I) const = 0;
 
 protected:
-  typedef std::function<void(MachineInstrBuilder &)> ComplexRendererFn;
+  using ComplexRendererFn = std::function<void(MachineInstrBuilder &)>;
 
   InstructionSelector();
 
@@ -110,6 +111,6 @@ protected:
   bool isObviouslySafeToFold(MachineInstr &MI) const;
 };
 
-} // End namespace llvm.
+} // end namespace llvm
 
-#endif
+#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
diff --git a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 21354ae20ed14..c259e93fdd366 100644
--- a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -1,4 +1,4 @@
-//==-- llvm/CodeGen/GlobalISel/LegalizerInfo.h -------------------*- C++ -*-==//
+//===- llvm/CodeGen/GlobalISel/LegalizerInfo.h ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,33 +12,36 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZER_H
-#define LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZER_H
+#ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
+#define LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
 
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/CodeGen/LowLevelType.h"
+#include "llvm/ADT/None.h"
+#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/LowLevelTypeImpl.h"
 #include "llvm/Target/TargetOpcodes.h"
-
 #include <cstdint>
-#include <functional>
+#include <cassert>
+#include <tuple>
+#include <utility>
 
 namespace llvm {
-class LLVMContext;
+
 class MachineInstr;
 class MachineIRBuilder;
 class MachineRegisterInfo;
-class Type;
-class VectorType;
 
 /// Legalization is decided based on an instruction's opcode, which type slot
 /// we're considering, and what the existing type is. These aspects are gathered
 /// together for convenience in the InstrAspect class.
 struct InstrAspect {
   unsigned Opcode;
-  unsigned Idx;
+  unsigned Idx = 0;
   LLT Type;
 
-  InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Idx(0), Type(Type) {}
+  InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {}
   InstrAspect(unsigned Opcode, unsigned Idx, LLT Type)
       : Opcode(Opcode), Idx(Idx), Type(Type) {}
 
@@ -104,6 +107,19 @@ public:
   /// before any query is made or incorrect results may be returned.
   void computeTables();
 
+  static bool needsLegalizingToDifferentSize(const LegalizeAction Action) {
+    switch (Action) {
+    case NarrowScalar:
+    case WidenScalar:
+    case FewerElements:
+    case MoreElements:
+    case Unsupported:
+      return true;
+    default:
+      return false;
+    }
+  }
+
   /// More friendly way to set an action for common types that have an LLT
   /// representation.
   void setAction(const InstrAspect &Aspect, LegalizeAction Action) {
@@ -125,7 +141,6 @@ public:
     ScalarInVectorActions[std::make_pair(Opcode, ScalarTy)] = Action;
   }
 
-
   /// Determine what action should be taken to legalize the given generic
   /// instruction opcode, type-index and type. Requires computeTables to have
   /// been called.
@@ -145,8 +160,8 @@ public:
 
   /// Iterate the given function (typically something like doubling the width)
   /// on Ty until we find a legal type for this operation.
-  Optional<LLT> findLegalType(const InstrAspect &Aspect,
-                    function_ref<LLT(LLT)> NextType) const {
+  Optional<LLT> findLegalizableSize(const InstrAspect &Aspect,
+                                    function_ref<LLT(LLT)> NextType) const {
     LegalizeAction Action;
     const TypeMap &Map = Actions[Aspect.Opcode - FirstOp][Aspect.Idx];
     LLT Ty = Aspect.Type;
@@ -158,10 +173,9 @@ public:
         if (DefaultIt == DefaultActions.end())
           return None;
         Action = DefaultIt->second;
-      }
-      else
+      } else
         Action = ActionIt->second;
-    } while(Action != Legal);
+    } while (needsLegalizingToDifferentSize(Action));
     return Ty;
   }
 
@@ -203,18 +217,17 @@ private:
   static const int FirstOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START;
   static const int LastOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
 
-  typedef DenseMap<LLT, LegalizeAction> TypeMap;
-  typedef DenseMap<std::pair<unsigned, LLT>, LegalizeAction> SIVActionMap;
+  using TypeMap = DenseMap<LLT, LegalizeAction>;
+  using SIVActionMap = DenseMap<std::pair<unsigned, LLT>, LegalizeAction>;
 
   SmallVector<TypeMap, 1> Actions[LastOp - FirstOp + 1];
   SIVActionMap ScalarInVectorActions;
   DenseMap<std::pair<unsigned, LLT>, uint16_t> MaxLegalVectorElts;
   DenseMap<unsigned, LegalizeAction> DefaultActions;
 
-  bool TablesInitialized;
+  bool TablesInitialized = false;
 };
 
+} // end namespace llvm
 
-} // End namespace llvm.
-
-#endif
+#endif // LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H
diff --git a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
index f610bc02b6f26..676955c33fe9c 100644
--- a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
+++ b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
@@ -1,4 +1,4 @@
-//== llvm/CodeGen/GlobalISel/RegBankSelect.h - Reg Bank Selector -*- C++ -*-==//
+//=- llvm/CodeGen/GlobalISel/RegBankSelect.h - Reg Bank Selector --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -64,20 +64,27 @@
 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
 #define LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
 
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include <cassert>
+#include <cstdint>
+#include <memory>
 
 namespace llvm {
-// Forward declarations.
+
 class BlockFrequency;
-class MachineBranchProbabilityInfo;
 class MachineBlockFrequencyInfo;
+class MachineBranchProbabilityInfo;
+class MachineOperand;
 class MachineRegisterInfo;
+class Pass;
+class raw_ostream;
 class TargetPassConfig;
 class TargetRegisterInfo;
-class raw_ostream;
 
 /// This pass implements the reg bank selector pass used in the GlobalISel
 /// pipeline. At the end of this pass, all register operands have been assigned
@@ -105,6 +112,7 @@ public:
   protected:
     /// Tell if the insert point has already been materialized.
     bool WasMaterialized = false;
+
     /// Materialize the insertion point.
     ///
     /// If isSplit() is true, this involves actually splitting
@@ -128,7 +136,7 @@ public:
     virtual MachineBasicBlock::iterator getPointImpl() = 0;
 
   public:
-    virtual ~InsertPoint() {}
+    virtual ~InsertPoint() = default;
 
     /// The first call to this method will cause the splitting to
     /// happen if need be, then sub sequent calls just return
@@ -197,6 +205,7 @@ public:
   private:
     /// Insertion point.
     MachineInstr &Instr;
+
     /// Does the insertion point is before or after Instr.
     bool Before;
 
@@ -216,6 +225,7 @@ public:
   public:
     /// Create an insertion point before (\p Before=true) or after \p Instr.
     InstrInsertPoint(MachineInstr &Instr, bool Before = true);
+
     bool isSplit() const override;
     uint64_t frequency(const Pass &P) const override;
 
@@ -228,6 +238,7 @@ public:
   private:
     /// Insertion point.
     MachineBasicBlock &MBB;
+
     /// Does the insertion point is at the beginning or end of MBB.
     bool Beginning;
 
@@ -252,6 +263,7 @@ public:
       assert((Beginning || MBB.getFirstTerminator() == MBB.end()) &&
              "Invalid end point");
     }
+
     bool isSplit() const override { return false; }
     uint64_t frequency(const Pass &P) const override;
     bool canMaterialize() const override { return true; };
@@ -262,10 +274,12 @@ public:
   private:
     /// Source of the edge.
     MachineBasicBlock &Src;
+
     /// Destination of the edge.
     /// After the materialization is done, this hold the basic block
     /// that resulted from the splitting.
     MachineBasicBlock *DstOrSplit;
+
     /// P is used to update the analysis passes as applicable.
     Pass &P;
 
@@ -286,9 +300,11 @@ public:
   public:
     EdgeInsertPoint(MachineBasicBlock &Src, MachineBasicBlock &Dst, Pass &P)
         : InsertPoint(), Src(Src), DstOrSplit(&Dst), P(P) {}
+
     bool isSplit() const override {
       return Src.succ_size() > 1 && DstOrSplit->pred_size() > 1;
     }
+
     uint64_t frequency(const Pass &P) const override;
     bool canMaterialize() const override;
   };
@@ -311,9 +327,9 @@ public:
 
     /// \name Convenient types for a list of insertion points.
     /// @{
-    typedef SmallVector<std::unique_ptr<InsertPoint>, 2> InsertionPoints;
-    typedef InsertionPoints::iterator insertpt_iterator;
-    typedef InsertionPoints::const_iterator const_insertpt_iterator;
+    using InsertionPoints = SmallVector<std::unique_ptr<InsertPoint>, 2>;
+    using insertpt_iterator = InsertionPoints::iterator;
+    using const_insertpt_iterator = InsertionPoints::const_iterator;
     /// @}
 
   private:
@@ -324,7 +340,7 @@ public:
     /// Are all the insert points materializeable?
     bool CanMaterialize;
     /// Is there any of the insert points needing splitting?
-    bool HasSplit;
+    bool HasSplit = false;
     /// Insertion point for the repair code.
     /// The repairing code needs to happen just before these points.
     InsertionPoints InsertPoints;
@@ -407,10 +423,10 @@ private:
   private:
     /// Cost of the local instructions.
     /// This cost is free of basic block frequency.
-    uint64_t LocalCost;
+    uint64_t LocalCost = 0;
     /// Cost of the non-local instructions.
     /// This cost should include the frequency of the related blocks.
-    uint64_t NonLocalCost;
+    uint64_t NonLocalCost = 0;
     /// Frequency of the block where the local instructions live.
     uint64_t LocalFreq;
 
@@ -468,22 +484,22 @@ private:
 
   /// Interface to the target lowering info related
   /// to register banks.
-  const RegisterBankInfo *RBI;
+  const RegisterBankInfo *RBI = nullptr;
 
   /// MRI contains all the register class/bank information that this
   /// pass uses and updates.
-  MachineRegisterInfo *MRI;
+  MachineRegisterInfo *MRI = nullptr;
 
   /// Information on the register classes for the current function.
-  const TargetRegisterInfo *TRI;
+  const TargetRegisterInfo *TRI = nullptr;
 
   /// Get the frequency of blocks.
   /// This is required for non-fast mode.
-  MachineBlockFrequencyInfo *MBFI;
+  MachineBlockFrequencyInfo *MBFI = nullptr;
 
   /// Get the frequency of the edges.
   /// This is required for non-fast mode.
-  MachineBranchProbabilityInfo *MBPI;
+  MachineBranchProbabilityInfo *MBPI = nullptr;
 
   /// Current optimization remark emitter. Used to report failures.
   std::unique_ptr<MachineOptimizationRemarkEmitter> MORE;
@@ -644,6 +660,6 @@ public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 };
 
-} // End namespace llvm.
+} // end namespace llvm
 
-#endif
+#endif // LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
diff --git a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index e3549d8988cda..60905c7ec226d 100644
--- a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -1,4 +1,4 @@
-//==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==//
+//===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,26 +12,27 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
-#define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
+#ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
+#define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
 
-#include "llvm/ADT/APInt.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Hashing.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
-#include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType.
+#include "llvm/ADT/iterator_range.h"
 #include "llvm/Support/ErrorHandling.h"
-
 #include <cassert>
-#include <memory> // For unique_ptr.
+#include <initializer_list>
+#include <memory>
 
 namespace llvm {
+
 class MachineInstr;
 class MachineRegisterInfo;
+class raw_ostream;
+class RegisterBank;
 class TargetInstrInfo;
+class TargetRegisterClass;
 class TargetRegisterInfo;
-class raw_ostream;
 
 /// Holds all the information related to register banks.
 class RegisterBankInfo {
@@ -48,10 +49,12 @@ public:
     /// original value.  The bits are counted from less significant
     /// bits to most significant bits.
     unsigned StartIdx;
+
     /// Length of this mapping in bits. This is how many bits this
     /// partial mapping covers in the original value:
     /// from StartIdx to StartIdx + Length -1.
     unsigned Length;
+
     /// Register bank where the partial value lives.
     const RegisterBank *RegBank;
 
@@ -180,13 +183,16 @@ public:
     /// Identifier of the mapping.
     /// This is used to communicate between the target and the optimizers
     /// which mapping should be realized.
-    unsigned ID;
+    unsigned ID = InvalidMappingID;
+
     /// Cost of this mapping.
-    unsigned Cost;
+    unsigned Cost = 0;
+
     /// Mapping of all the operands.
     const ValueMapping *OperandsMapping;
+
     /// Number of operands.
-    unsigned NumOperands;
+    unsigned NumOperands = 0;
 
     const ValueMapping &getOperandMapping(unsigned i) {
       assert(i < getNumOperands() && "Out of bound operand");
@@ -213,7 +219,7 @@ public:
 
     /// Default constructor.
     /// Use this constructor to express that the mapping is invalid.
-    InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {}
+    InstructionMapping() = default;
 
     /// Get the cost.
     unsigned getCost() const { return Cost; }
@@ -264,7 +270,7 @@ public:
   /// Convenient type to represent the alternatives for mapping an
   /// instruction.
   /// \todo When we move to TableGen this should be an array ref.
-  typedef SmallVector<const InstructionMapping *, 4> InstructionMappings;
+  using InstructionMappings = SmallVector<const InstructionMapping *, 4>;
 
   /// Helper class used to get/create the virtual registers that will be used
   /// to replace the MachineOperand when applying a mapping.
@@ -273,12 +279,16 @@ public:
     /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
     /// Note: We use a SmallVector to avoid heap allocation for most cases.
     SmallVector<int, 8> OpToNewVRegIdx;
+
     /// Hold the registers that will be used to map MI with InstrMapping.
     SmallVector<unsigned, 8> NewVRegs;
+
     /// Current MachineRegisterInfo, used to create new virtual registers.
     MachineRegisterInfo &MRI;
+
     /// Instruction being remapped.
     MachineInstr &MI;
+
     /// New mapping of the instruction.
     const InstructionMapping &InstrMapping;
 
@@ -373,6 +383,7 @@ public:
 protected:
   /// Hold the set of supported register banks.
   RegisterBank **RegBanks;
+
   /// Total number of register banks.
   unsigned NumRegBanks;
 
@@ -729,6 +740,7 @@ operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
 /// Hashing function for PartialMapping.
 /// It is required for the hashing of ValueMapping.
 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
-} // End namespace llvm.
 
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
diff --git a/include/llvm/CodeGen/GlobalISel/Types.h b/include/llvm/CodeGen/GlobalISel/Types.h
index 7d974878d3b9f..7b22e343a7f86 100644
--- a/include/llvm/CodeGen/GlobalISel/Types.h
+++ b/include/llvm/CodeGen/GlobalISel/Types.h
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/GlobalISel/Types.h - Types used by GISel ----*- C++ -*-===//
+//===- llvm/CodeGen/GlobalISel/Types.h - Types used by GISel ----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -16,17 +16,19 @@
 #define LLVM_CODEGEN_GLOBALISEL_TYPES_H
 
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/IR/Value.h"
 
 namespace llvm {
 
+class Value;
+
 /// Map a value to a virtual register.
 /// For now, we chose to map aggregate types to on single virtual
 /// register. This might be revisited if it turns out to be inefficient.
 /// PR26161 tracks that.
 /// Note: We need to expose this type to the target hooks for thing like
 /// ABI lowering that would be used during IRTranslation.
-typedef DenseMap<const Value *, unsigned> ValueToVReg;
+using ValueToVReg = DenseMap<const Value *, unsigned>;
+
+} // end namespace llvm
 
-} // End namespace llvm.
-#endif
+#endif // LLVM_CODEGEN_GLOBALISEL_TYPES_H