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authorRoman Divacky <rdivacky@FreeBSD.org>2010-05-27 15:15:58 +0000
committerRoman Divacky <rdivacky@FreeBSD.org>2010-05-27 15:15:58 +0000
commitabdf259d487163e72081a8cf4991b1617206b41e (patch)
tree9fad9a5d5dd8c4ff54af48edad9c8cc26dd5fda1 /include/llvm/CodeGen/SchedulerRegistry.h
parent59161dfae3225dd9151afbc76ca9074598c0c605 (diff)
Notes
Diffstat (limited to 'include/llvm/CodeGen/SchedulerRegistry.h')
-rw-r--r--include/llvm/CodeGen/SchedulerRegistry.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index cf3274f4a961a..14c33e2187552 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -73,11 +73,17 @@ ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel);
-/// createBURRListDAGScheduler - This creates a bottom up register usage
-/// reduction list scheduler that schedules in source code order when possible.
+/// createBURRListDAGScheduler - This creates a bottom up list scheduler that
+/// schedules nodes in source code order when possible.
ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel);
+/// createHybridListDAGScheduler - This creates a bottom up hybrid register
+/// usage reduction list scheduler that make use of latency information to
+/// avoid stalls for long latency instructions.
+ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOpt::Level);
+
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,