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authorDimitry Andric <dim@FreeBSD.org>2017-01-14 15:37:50 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-01-14 15:37:50 +0000
commit581a6d8501ff5614297da837b81ed3b6956361ea (patch)
tree985ee91d0ca1d3e6506ac5ff7e37f5b67adfec09 /include/llvm/CodeGen/SelectionDAG.h
parent909545a822eef491158f831688066f0ec2866938 (diff)
Diffstat (limited to 'include/llvm/CodeGen/SelectionDAG.h')
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 7927982e782d1..54d0436e4ab83 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -626,12 +626,6 @@ public:
SDValue getCondCode(ISD::CondCode Cond);
- /// Returns the ConvertRndSat Note: Avoid using this node because it may
- /// disappear in the future and most targets don't support it.
- SDValue getConvertRndSat(EVT VT, const SDLoc &dl, SDValue Val, SDValue DTy,
- SDValue STy, SDValue Rnd, SDValue Sat,
- ISD::CvtCode Code);
-
/// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,
/// which must be a vector type, must match the number of mask elements
/// NumElts. An integer mask element equal to -1 is treated as undefined.