vendor/llvm/llvm-trunk-r302418

10 files changed, 113 insertions, 21 deletions

diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index fb8c8408fc779..180c0b5792488 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -226,6 +226,7 @@ public:
     FUNCTION_EXIT = 1,
     TAIL_CALL = 2,
     LOG_ARGS_ENTER = 3,
+    CUSTOM_EVENT = 4,
   };
 
   // The table will contain these structs that point to the sled, the function
@@ -242,7 +243,7 @@ public:
   };
 
   // All the sleds to be emitted.
-  std::vector<XRayFunctionEntry> Sleds;
+  SmallVector<XRayFunctionEntry, 4> Sleds;
 
   // Helper function to record a given XRay sled.
   void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind);
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index 2abe3bb115568..57fa0c73d2722 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -506,6 +506,7 @@ protected:
   bool selectCast(const User *I, unsigned Opcode);
   bool selectExtractValue(const User *I);
   bool selectInsertValue(const User *I);
+  bool selectXRayCustomEvent(const CallInst *II);
 
 private:
   /// \brief Handle PHI nodes in successor blocks.
diff --git a/include/llvm/CodeGen/FunctionLoweringInfo.h b/include/llvm/CodeGen/FunctionLoweringInfo.h
index 14ee5019ef2fb..e7544bd7b70c8 100644
--- a/include/llvm/CodeGen/FunctionLoweringInfo.h
+++ b/include/llvm/CodeGen/FunctionLoweringInfo.h
@@ -249,7 +249,7 @@ public:
   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
                          const KnownBits &Known) {
     // Only install this information if it tells us something.
-    if (NumSignBits == 1 && Known.Zero == 0 && Known.One == 0)
+    if (NumSignBits == 1 && Known.isUnknown())
       return;
 
     LiveOutRegInfo.grow(Reg);
diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 31ffdc0e2e78c..e292e8913db06 100644
--- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -78,7 +78,7 @@ private:
   /// this function.
   DenseMap<const AllocaInst *, int> FrameIndices;
 
-  /// Methods for translating form LLVM IR to MachineInstr.
+  /// \name Methods for translating form LLVM IR to MachineInstr.
   /// \see ::translate for general information on the translate methods.
   /// @{
 
diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 472f50576d966..6b662a7f74136 100644
--- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -45,7 +45,7 @@ class MachineIRBuilder {
   /// Debug location to be set to any instruction we create.
   DebugLoc DL;
 
-  /// Fields describing the insertion point.
+  /// \name Fields describing the insertion point.
   /// @{
   MachineBasicBlock *MBB;
   MachineBasicBlock::iterator II;
@@ -84,7 +84,7 @@ public:
   void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
   /// @}
 
-  /// Setters for the insertion point.
+  /// \name Setters for the insertion point.
   /// @{
   /// Set the MachineFunction where to build instructions.
   void setMF(MachineFunction &);
@@ -98,7 +98,7 @@ public:
   void setInstr(MachineInstr &MI);
   /// @}
 
-  /// Control where instructions we create are recorded (typically for
+  /// \name Control where instructions we create are recorded (typically for
   /// visiting again later during legalization).
   /// @{
   void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
diff --git a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
index daa8dcf2061b7..f610bc02b6f26 100644
--- a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
+++ b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
@@ -309,7 +309,7 @@ public:
       Impossible
     };
 
-    /// Convenient types for a list of insertion points.
+    /// \name Convenient types for a list of insertion points.
     /// @{
     typedef SmallVector<std::unique_ptr<InsertPoint>, 2> InsertionPoints;
     typedef InsertionPoints::iterator insertpt_iterator;
@@ -341,7 +341,7 @@ public:
                        const TargetRegisterInfo &TRI, Pass &P,
                        RepairingKind Kind = RepairingKind::Insert);
 
-    /// Getters.
+    /// \name Getters.
     /// @{
     RepairingKind getKind() const { return Kind; }
     unsigned getOpIdx() const { return OpIdx; }
@@ -349,7 +349,7 @@ public:
     bool hasSplit() { return HasSplit; }
     /// @}
 
-    /// Overloaded methods to add an insertion point.
+    /// \name Overloaded methods to add an insertion point.
     /// @{
     /// Add a MBBInsertionPoint to the list of InsertPoints.
     void addInsertPoint(MachineBasicBlock &MBB, bool Beginning);
@@ -362,7 +362,7 @@ public:
     void addInsertPoint(InsertPoint &Point);
     /// @}
 
-    /// Accessors related to the insertion points.
+    /// \name Accessors related to the insertion points.
     /// @{
     insertpt_iterator begin() { return InsertPoints.begin(); }
     insertpt_iterator end() { return InsertPoints.end(); }
@@ -561,7 +561,7 @@ private:
 
   /// Find the best mapping for \p MI from \p PossibleMappings.
   /// \return a reference on the best mapping in \p PossibleMappings.
-  RegisterBankInfo::InstructionMapping &
+  const RegisterBankInfo::InstructionMapping &
   findBestMapping(MachineInstr &MI,
                   RegisterBankInfo::InstructionMappings &PossibleMappings,
                   SmallVectorImpl<RepairingPlacement> &RepairPts);
diff --git a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index 600733ac6a2d8..f32233b3a9e44 100644
--- a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -264,7 +264,7 @@ public:
   /// Convenient type to represent the alternatives for mapping an
   /// instruction.
   /// \todo When we move to TableGen this should be an array ref.
-  typedef SmallVector<InstructionMapping, 4> InstructionMappings;
+  typedef SmallVector<const InstructionMapping *, 4> InstructionMappings;
 
   /// Helper class used to get/create the virtual registers that will be used
   /// to replace the MachineOperand when applying a mapping.
@@ -310,7 +310,7 @@ public:
     OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
                    MachineRegisterInfo &MRI);
 
-    /// Getters.
+    /// \name Getters.
     /// @{
     /// The MachineInstr being remapped.
     MachineInstr &getMI() const { return MI; }
@@ -378,15 +378,23 @@ protected:
 
   /// Keep dynamically allocated PartialMapping in a separate map.
   /// This shouldn't be needed when everything gets TableGen'ed.
-  mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>> MapOfPartialMappings;
+  mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>>
+      MapOfPartialMappings;
 
   /// Keep dynamically allocated ValueMapping in a separate map.
   /// This shouldn't be needed when everything gets TableGen'ed.
-  mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping> > MapOfValueMappings;
+  mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>>
+      MapOfValueMappings;
 
   /// Keep dynamically allocated array of ValueMapping in a separate map.
   /// This shouldn't be needed when everything gets TableGen'ed.
-  mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>> MapOfOperandsMappings;
+  mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>>
+      MapOfOperandsMappings;
+
+  /// Keep dynamically allocated InstructionMapping in a separate map.
+  /// This shouldn't be needed when everything gets TableGen'ed.
+  mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>>
+      MapOfInstructionMappings;
 
   /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks
   /// RegisterBank instances.
@@ -425,14 +433,14 @@ protected:
   ///   register, a register class, or a register bank.
   /// In other words, this method will likely fail to find a mapping for
   /// any generic opcode that has not been lowered by target specific code.
-  InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const;
+  const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
 
   /// Get the uniquely generated PartialMapping for the
   /// given arguments.
   const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
                                           const RegisterBank &RegBank) const;
 
-  /// Methods to get a uniquely generated ValueMapping.
+  /// \name Methods to get a uniquely generated ValueMapping.
   /// @{
 
   /// The most common ValueMapping consists of a single PartialMapping.
@@ -445,7 +453,7 @@ protected:
                                       unsigned NumBreakDowns) const;
   /// @}
 
-  /// Methods to get a uniquely generated array of ValueMapping.
+  /// \name Methods to get a uniquely generated array of ValueMapping.
   /// @{
 
   /// Get the uniquely generated array of ValueMapping for the
@@ -478,6 +486,33 @@ protected:
       std::initializer_list<const ValueMapping *> OpdsMapping) const;
   /// @}
 
+  /// \name Methods to get a uniquely generated InstructionMapping.
+  /// @{
+
+private:
+  /// Method to get a uniquely generated InstructionMapping.
+  const InstructionMapping &
+  getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
+                            unsigned Cost = 0,
+                            const ValueMapping *OperandsMapping = nullptr,
+                            unsigned NumOperands = 0) const;
+
+public:
+  /// Method to get a uniquely generated InstructionMapping.
+  const InstructionMapping &
+  getInstructionMapping(unsigned ID, unsigned Cost,
+                        const ValueMapping *OperandsMapping,
+                        unsigned NumOperands) const {
+    return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
+                                     OperandsMapping, NumOperands);
+  }
+
+  /// Method to get a uniquely generated invalid InstructionMapping.
+  const InstructionMapping &getInvalidInstructionMapping() const {
+    return getInstructionMappingImpl(/*IsInvalid*/ true);
+  }
+  /// @}
+
   /// Get the register bank for the \p OpIdx-th operand of \p MI form
   /// the encoding constraints, if any.
   ///
@@ -603,7 +638,8 @@ public:
   ///
   /// \note If returnedVal does not verify MI, this would probably mean
   /// that the target does not support that instruction.
-  virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const;
+  virtual const InstructionMapping &
+  getInstrMapping(const MachineInstr &MI) const;
 
   /// Get the alternative mappings for \p MI.
   /// Alternative in the sense different from getInstrMapping.
diff --git a/include/llvm/CodeGen/MIRPrinter.h b/include/llvm/CodeGen/MIRPrinter.h
new file mode 100644
index 0000000000000..c73adc3f2b114
--- /dev/null
+++ b/include/llvm/CodeGen/MIRPrinter.h
@@ -0,0 +1,46 @@
+//===- MIRPrinter.h - MIR serialization format printer --------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the functions that print out the LLVM IR and the machine
+// functions using the MIR serialization format.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_CODEGEN_MIRPRINTER_H
+#define LLVM_LIB_CODEGEN_MIRPRINTER_H
+
+namespace llvm {
+
+class MachineBasicBlock;
+class MachineFunction;
+class Module;
+class raw_ostream;
+template <typename T> class SmallVectorImpl;
+
+/// Print LLVM IR using the MIR serialization format to the given output stream.
+void printMIR(raw_ostream &OS, const Module &M);
+
+/// Print a machine function using the MIR serialization format to the given
+/// output stream.
+void printMIR(raw_ostream &OS, const MachineFunction &MF);
+
+/// Determine a possible list of successors of a basic block based on the
+/// basic block machine operand being used inside the block. This should give
+/// you the correct list of successor blocks in most cases except for things
+/// like jump tables where the basic block references can't easily be found.
+/// The MIRPRinter will skip printing successors if they match the result of
+/// this funciton and the parser will use this function to construct a list if
+/// it is missing.
+void guessSuccessors(const MachineBasicBlock &MBB,
+                     SmallVectorImpl<MachineBasicBlock*> &Successors,
+                     bool &IsFallthrough);
+
+} // end namespace llvm
+
+#endif
diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h
index 61be9f775c979..689f3cd9fd12b 100644
--- a/include/llvm/CodeGen/MachineFrameInfo.h
+++ b/include/llvm/CodeGen/MachineFrameInfo.h
@@ -520,6 +520,14 @@ public:
   bool hasTailCall() const { return HasTailCall; }
   void setHasTailCall() { HasTailCall = true; }
 
+  /// Computes the maximum size of a callframe and the AdjustsStack property.
+  /// This only works for targets defining
+  /// TargetInstrInfo::getCallFrameSetupOpcode(), getCallFrameDestroyOpcode(),
+  /// and getFrameSize().
+  /// This is usually computed by the prologue epilogue inserter but some
+  /// targets may call this to compute it earlier.
+  void computeMaxCallFrameSize(const MachineFunction &MF);
+
   /// Return the maximum size of a call frame that must be
   /// allocated for an outgoing function call.  This is only available if
   /// CallFrameSetup/Destroy pseudo instructions are used by the target, and
diff --git a/include/llvm/CodeGen/MachineModuleInfo.h b/include/llvm/CodeGen/MachineModuleInfo.h
index 182d23ef3c904..f46ef41879d17 100644
--- a/include/llvm/CodeGen/MachineModuleInfo.h
+++ b/include/llvm/CodeGen/MachineModuleInfo.h
@@ -116,7 +116,7 @@ class MachineModuleInfo : public ImmutablePass {
 
   // TODO: Ideally, what we'd like is to have a switch that allows emitting 
   // synchronous (precise at call-sites only) CFA into .eh_frame. However,
-  // even under this switch, we'd like .debug_frame to be precise when using.
+  // even under this switch, we'd like .debug_frame to be precise when using
   // -g. At this moment, there's no way to specify that some CFI directives
   // go into .eh_frame only, while others go into .debug_frame only.