diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2017-07-01 13:22:02 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2017-07-01 13:22:02 +0000 |
commit | 9df3605dea17e84f8183581f6103bd0c79e2a606 (patch) | |
tree | 70a2f36ce9eb9bb213603cd7f2f120af53fc176f /lib/CodeGen/RenameIndependentSubregs.cpp | |
parent | 08bbd35a80bf7765fe0d3043f9eb5a2f2786b649 (diff) |
Diffstat (limited to 'lib/CodeGen/RenameIndependentSubregs.cpp')
-rw-r--r-- | lib/CodeGen/RenameIndependentSubregs.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/CodeGen/RenameIndependentSubregs.cpp b/lib/CodeGen/RenameIndependentSubregs.cpp index d2eff950d861a..bd5ecbd28f293 100644 --- a/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/lib/CodeGen/RenameIndependentSubregs.cpp @@ -243,10 +243,14 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes, unsigned VReg = Intervals[ID]->reg; MO.setReg(VReg); - if (MO.isTied()) { + + if (MO.isTied() && Reg != VReg) { /// Undef use operands are not tracked in the equivalence class but need /// to be update if they are tied. MO.getParent()->substituteRegister(Reg, VReg, 0, TRI); + + // substituteRegister breaks the iterator, so restart. + I = MRI->reg_nodbg_begin(Reg); } } // TODO: We could attempt to recompute new register classes while visiting |