diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-26 19:45:00 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-26 19:45:00 +0000 |
| commit | 12f3ca4cdb95b193af905a00e722a4dcb40b3de3 (patch) | |
| tree | ae1a7fcfc24a8d4b23206c57121c3f361d4b7f84 /lib/Target/AMDGPU/GCNRegPressure.cpp | |
| parent | d99dafe2e4a385dd2a6c76da6d8258deb100657b (diff) | |
Diffstat (limited to 'lib/Target/AMDGPU/GCNRegPressure.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/GCNRegPressure.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AMDGPU/GCNRegPressure.cpp b/lib/Target/AMDGPU/GCNRegPressure.cpp index 4ecfa118fb275..bf16a82160013 100644 --- a/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -83,8 +83,8 @@ unsigned GCNRegPressure::getRegKind(unsigned Reg, const auto RC = MRI.getRegClass(Reg); auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); return STI->isSGPRClass(RC) ? - (RC->getSize() == 4 ? SGPR32 : SGPR_TUPLE) : - (RC->getSize() == 4 ? VGPR32 : VGPR_TUPLE); + (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : + (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); } void GCNRegPressure::inc(unsigned Reg, |