diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-29 16:25:25 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-29 16:25:25 +0000 |
| commit | ab44ce3d598882e51a25eb82eb7ae6308de85ae6 (patch) | |
| tree | 568d786a59d49bef961dcb9bd09d422701b9da5b /lib/Target/AMDGPU/R600ISelLowering.cpp | |
| parent | b5630dbadf9a2a06754194387d6b0fd9962a67f1 (diff) | |
Diffstat (limited to 'lib/Target/AMDGPU/R600ISelLowering.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/R600ISelLowering.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index 3590a9b05e1d0..60b913cfd39af 100644 --- a/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1618,6 +1618,14 @@ EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, return VT.changeVectorElementTypeToInteger(); } +bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT) const { + // Local and Private addresses do not handle vectors. Limit to i32 + if ((AS == AMDGPUASI.LOCAL_ADDRESS || AS == AMDGPUASI.PRIVATE_ADDRESS)) { + return (MemVT.getSizeInBits() <= 32); + } + return true; +} + bool R600TargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, |