diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-08 17:12:57 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-08 17:12:57 +0000 |
| commit | c46e6a5940c50058e00c0c5f9123fd82e338d29a (patch) | |
| tree | 89a719d723035c54a190b1f81d329834f1f93336 /lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
| parent | 148779df305667b6942fee7e758fdf81a6498f38 (diff) | |
Diffstat (limited to 'lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index b6a982aee6bee..adebb8c4a1c5b 100644 --- a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -122,9 +122,15 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) bool MaySpill = ST.isVGPRSpillingEnabled(*F); bool HasStackObjects = FrameInfo.hasStackObjects(); - if (HasStackObjects || MaySpill) + if (HasStackObjects || MaySpill) { PrivateSegmentWaveByteOffset = true; + // HS and GS always have the scratch wave offset in SGPR5 on GFX9. + if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 && + (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS)) + PrivateSegmentWaveByteOffsetSystemSGPR = AMDGPU::SGPR5; + } + if (ST.isAmdCodeObjectV2(MF)) { if (HasStackObjects || MaySpill) PrivateSegmentBuffer = true; |