summaryrefslogtreecommitdiff
path: root/lib/Target/ARM/ARM.h
diff options
context:
space:
mode:
authorRoman Divacky <rdivacky@FreeBSD.org>2010-05-27 15:15:58 +0000
committerRoman Divacky <rdivacky@FreeBSD.org>2010-05-27 15:15:58 +0000
commitabdf259d487163e72081a8cf4991b1617206b41e (patch)
tree9fad9a5d5dd8c4ff54af48edad9c8cc26dd5fda1 /lib/Target/ARM/ARM.h
parent59161dfae3225dd9151afbc76ca9074598c0c605 (diff)
Notes
Diffstat (limited to 'lib/Target/ARM/ARM.h')
-rw-r--r--lib/Target/ARM/ARM.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h
index b08f9425776ea..ae7ae59c92624 100644
--- a/lib/Target/ARM/ARM.h
+++ b/lib/Target/ARM/ARM.h
@@ -48,7 +48,7 @@ namespace ARMCC {
AL
};
- inline static CondCodes getOppositeCondition(CondCodes CC){
+ inline static CondCodes getOppositeCondition(CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
@@ -67,7 +67,7 @@ namespace ARMCC {
case LE: return GT;
}
}
-}
+} // namespace ARMCC
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
@@ -90,6 +90,10 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
}
}
+/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
+/// operations involving sub-registers.
+bool ModelWithRegSequence();
+
FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
CodeGenOpt::Level OptLevel);