diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2009-10-14 17:57:32 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2009-10-14 17:57:32 +0000 |
| commit | 59850d0874429601812bc13408cb1f776649027c (patch) | |
| tree | b21f6de4e08b89bb7931806bab798fc2a5e3a686 /lib/Target/ARM/ARMScheduleV6.td | |
| parent | 18f153bdb9db52e7089a2d5293b96c45a3124a26 (diff) | |
Notes
Diffstat (limited to 'lib/Target/ARM/ARMScheduleV6.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index 596a57f8aefd5..1ace718c9e178 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -1,4 +1,4 @@ -//===- ARMSchedule.td - ARM v6 Scheduling Definitions ------*- tablegen -*-===// +//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -11,12 +11,4 @@ // //===----------------------------------------------------------------------===// -def V6Itineraries : ProcessorItineraries<[ - InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>, - InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>, - InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>, - InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>, - InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>, - InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>, - InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]> -]>; +// TODO: Add model for an ARM11 |